Solutions2CMOS CircuitDesign Allen
-
Upload
anil-kumar -
Category
Documents
-
view
216 -
download
0
Transcript of Solutions2CMOS CircuitDesign Allen
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
1/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions : 9/20/2002 1
Chapter 1 Homework Solutions
1.1-1 Using Eq. (1) of Sec 1.1, give the base-10 value for the 5-bit binary number 11010(b4 b3 b2 b1 b0 ordering).
From Eq. (1) of Sec 1.1 we have
b N -1 2-1 + b N -2 2
-2 + b N -3 2-3 + ...+ b0 2
- N =!i=1
N
b N-i2-i
1 × 2-1 + 1× 2-2 + 0 × 2-3 + 1 × 2-4 + 0 × 2-5 =1
2 +
1
4 +
0
8 +
1
16 +
0
32
=16 + 8 + 0 + 2 + 0
32 =
26
32 =
13
16
1.1-2 Process the sinusoid in Fig. P1.2 through an analog sample and hold. The samplepoints are given at each integer value of t/T.
1 2 3 4 5 6 7 80
1
23
4
5
6
7
8 A m
p l i t u d e
t
T
__
9
10
11
12
13
14
15
9 10 11
Sample times
Figure P1.1-2
1.1-3 Digitize the sinusoid given in Fig. P1.2 according to Eq. (1) in Sec. 1.1 using afour-bit digitizer.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
2/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions : 9/20/2002 2
1 2 3 4 5 6 7 80
1
23
4
5
6
7
8 A m p l i t u d
e
t
T
__
9
10
11
12
13
14
15
9 10 11
Sample times
1000
1100
1110
1111
1101
1010
0110
0011
0010
0010
0101
1000
Figure P1.1-3
The figure illustrates the digitized result. At several places in the waveform, the digitizedvalue must resolve a sampled value that lies equally between two digital values. Theresulting digitized value could be either of the two values as illustrated in the list below.
Sample Time 4-bit Output
0 1000
1 11002 1110
3 1111 or 1110
4 1101
5 1010
6 0110
7 0011
8 0010 or 0001
9 0010
10 0101
11 1000
1.1-4 Use the nodal equation method to find vout / vin of Fig. P1.4.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
3/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions : 9/20/2002 3
vin
R1 R2
R3 R4v1 voutgmv1
Figure P1.1-4
A B
Node A:
0 = G1(v1-vin) + G3(v1) + G2(v1 - vout)
v1(G1 + G2 + G3) - G2(vout) = G1(vin)
Node B:
0 = G2(vout-v1) + gm1(v1) + G4( vout)
v1(gm1 - G2) + vout (G2 + G4) = 0
vout ="""
"""G1+G2 +G3 G1vin
gm1 - G2 0
"""
"""G1+G2 +G3 - G2
gm1 - G2 G2 + G4
vout vin
=
G1 (G2 - gm1)
G1 G2 + G1 G4 + G2 G4 + G3 G2 + G3 G4 + G2 gm1
1.1-5 Use the mesh equation method to find vout / vin of Fig. P1.4.
vin
R1 R2
R3 R4v1 voutgmv1ia
ibic
Figure P1.1-5
0 = -vin + R1(ia + ib + ic) + R3(ia)
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
4/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions : 9/20/2002 4
0 = -vin + R1(ia + ib + ic) + R2(ib + ic) + vout
ic =vout
R4
ib = gm v1 = gm ia R3
0 = -vin + R1# $%
&' (
ia + gm ia R3 +vout
R4 + R3ia
0 = -vin + R1# $%
&' (
ia + gm ia R3 +vout
R4 + R2
# $%
&' (
gm ia R3 +vout
R4 + vout
vin = ia ( R1 + R3 + gm R1 R2) + vout R1
R4
vin = ia ( R1 + gm R1 R3 + gm R2 R3) + vout # $%
&' ( R1 + R2+ R4
R4
vout ="""
""" R1+ R3 + gm R1 R3 vin
R1+ gm R1 R3 + gm R2 R3 vin
"""
""" R1+ R3 + gm R1 R3 R1 / R4
R1+ gm R1 R3 + gm R2 R3 ( R1+ R2+R4) / R4
vout =vin R3 R4 (1 - gm R2)
( R1 + R3 + gm R1 R3) ( R1 + R2 + R4) - ( R21 + gm R
21 R3 + gm R1 R2 R3)
vout =vin R3 R4 (1 - gm R2)
R1 R2 + R1 R4 + R1 R3 + R2 R3 + R3 R4 + gm R1 R3 R4
vout v
in
= R3 R4 (1 - gm R2)
R1 R
2 + R
1 R
4 + R
1 R
3 + R
2 R
3 + R
3 R
4 + g
m R
1 R
3 R
4
1.1-6 Use the source rearrangement and substitution concepts to simplify the circuitshown in Fig. P1.6 and solve for iout / iin by making chain-type calculations only.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
5/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions : 9/20/2002 5
iin
R1
R2
R3v1 ioutr mi
i
iin
R1
R2
R3v1 ioutr mi
i
r mi
iin
R1
R2
R3v1 iout R-r m
i
r mi
Figure P1.1-6
iout =-r m R3
i
i = R1
R + R1 - r m iin
iout iin
=-r m R1 / R3
R + R1 - r m
1.1-7 Find v2 / v1 and v1 / i1 of Fig. P1.7.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
6/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions : 9/20/2002 6
i1
R Lv1
gm(v1-v2)
v2
Figure P1.1-7
v2 v1
= gm (v1 - v2) R L
v2 (1 + gm R L ) = gm R L v1
v2 v1
= gm R L 1 + gm R L
v2 = i1 R L
substituting for v2 yields:
i1 R L
v1 =
gm R L 1 + gm R L
v1
i1 =
R L( 1 + gm R L )
gm R L
v1
i1 = R L +
1 gm
1.1-8 Use the circuit-reduction technique to solve for vout / vin of Fig. P1.8.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
7/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions : 9/20/2002 7
vin R1 R2v1
Av(vin - v1)
vout
vin R1 R2v1
Avv1
vout
Avvin
N 1 N 2
Figure P1.1-8a
Multiply R1 by (Av + 1)
vin
R1(Av+1)
R2v1 vout
Avvin
Figure P1.1-8b
vout =-Avvin R2
R2 + R1(Av+1)
vout vin
=-Av R2
R2 + R1(Av+1)
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
8/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions : 9/20/2002 8
vout vin
=
-Av -Av + 1
R2
R2
Av + 1 + R1
As Av approaches infinity,
vout vin
=- R2 R1
1.1-9 Use the Miller simplification concept to solve for vout / vin of Fig. A-3 (see
Appendix A).
vin
R1
R2
R3
vout
r mia
ia ib
Figure P1.1-9a (Figure A-3 Mesh analysis.)
v1
K =vout v1
=-r m ia ia R2
=-r m R2
Z 1 = R3
1 +r m R2
Z 2 =
R3 -r m
R2
-r m R2
- 1
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
9/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions : 9/20/2002 9
Z 2 =
r m
R3
R2
r m R2
+ 1
= R3
R2 r m
+ 1
vin
R1
R2 vout
r mia
ia
Z 1 Z 2
Figure P1.1-9b
ia =vin ( R2 || Z 1)
( R2 || Z 1) + R1 # $%
&' (
1 R2
vout = -r m ia
vout =-vin r m ( R2 || Z 1)
( R2 || Z 1) + R1 # $%
&' (1
R2
vout
vin =
-r m ( R2 || Z 1)
( R2 || Z 1) + R1 # $%
&' (1
R2
vout vin
=-r m R3
( R1 R2 + R1 R3 + R1r m + R2 R3)
1.1-10 Find vout / iin of Fig. A-12 and compare with the results of Example A-1.
R1 R3v1gmv1
R' 2 voutiin
Figure P1.1-10
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
10/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions : 9/20/2002 10
v1 = iin ( R1 || R'2)
vout = -gmv1 R3 = -gm R3 iin ( R1 || R'2)
vout
iin = -gm R3( R1 || R
'2)
R'2 =
R2
1 + gm R3
R1 || R'2 =
R1 R2 1 + g
m R
3
(1 + gm R3) R1 + R2
1 + gm R3
R1 || R'2 =
R1 R2 (1 + gm R3) R1 + R2
vout iin
=-gm R1 R2 R3
R1+ R2+ R3+ gm R1 R3
The A.1-1 result is:vout
iin =
R1 R3 - gm R1 R2 R3 R1+ R2+ R3+ gm R1 R3
if gm R2 >> 1 then the results are the same.
1.1-11 Use the Miller simplification technique described in Appendix A to solve for theoutput resistance, vo / io, of Fig. P1.4. Calculate the output resistance not using the Miller
simplification and compare your results.
vin
R1 R2
R3 R4v1 voutgmv1
Figure P1.1-11a
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
11/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions : 9/20/2002 11
Zo with Miller
K = -gm R4
Z 2 =- R2 gm R4 -gm R4 - 1
= R2 gm R4 1 + gm R4
Z 0 = R4 || Z 2 =
gm R2 R24
1 + gm R4
(1 + gm R4) R4 + gm R2 R
24
1 + gm R4
Z 0 = R4 || Z 2 =gm R2 R
24
R4 + gm R4 ( R4 + R2)
Zo without Miller
R1|| R3
R2
R4v1 vTgmv1
iT
Figure P1.1-11b
v1 = ( R1 || R3) # $%
&' (
i + gmv1 -vT
R4
v1 [1 + gm ( R1 || R3)] = ( R1 || R3 ) # $%
&' (
iT + -vT
R4
(1) v1 =( R1 || R3) (iT R4 + - vT)
R4 [1 + gm ( R1 || R3)]
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
12/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions : 9/20/2002 12
(2) v1 =vT ( R1 || R3)
R1 || R3 + R2
Equate (1) and (2)
vT ( R1 || R3)
R1 || R3 + R2 =
( R1 || R3) (iT R4 - vT)
R4 [1 + gm ( R1 || R3)]
vT R1 || R3 + R2
=iT R4 - vT
R4 [1 + gm ( R1 || R3)]
vT )*+
,-. R4 [1 + gm ( R1 || R3)] + R2+ R1|| R3 = iT R4 ( R2+ R1|| R3)
Z 0 = R4 ( R2+ R1|| R3 )
R2 + R4 + gm R4( R1|| R3) + R1|| R3
Z 0 =
R4 R2 + R1 R3 R4 R1 + R3
R2 + R4 +gm R4 R1 R3 + R1 R3
R1
+ R3
Z 0 = R4 R2 ( R1 + R3) + R1 R3 R4
( R2 + R4) ( R1 + R3) + R1 R3 + gm R1 R3 R4
Z 0 = R1 R2 R4 + R2 R3 R4 + R1 R3 R4
R1 R2 + R2 R3 + R3 R4 + R1 R4 + R1 R3 + gm R1 R3 R4
1.1-12 Consider an ideal voltage amplifier with a voltage gain of Av = 0.99. A resistance
R = 50 k Ω is connected from the output back to the input. Find the input resistanceof this circuit by applying the Miller simplification concept.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
13/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions : 9/20/2002 13
0.99v1
R=50K
v1 vout
i
Figure P1.1-12
Rin = R
1 - K
K = 0.99
Rin =50 K Ω
1 - 0.99 =50 K Ω
0.01 = 5 Meg Ω
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
14/508
CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 1
Chapter 2 Homework Solutions
Problem 2.1-1List the five basic MOS fabrication processing steps and give the purpose or function of each step.
Oxidation: Combining oxygen and silicon to form silicondioxide (SiO2).Resulting SiO2 formed by oxidation is used as an isolation barrier (e.g., betweengate polysilicon and the underlying channel) and as a dielectric (e.g., between twoplates of a capacitor).
Diffusion: Movement of impurity atoms from one location to another (e.g., fromthe silicon surface to the bulk to form a diffused well region).
Ion Implantation: Firing ions into an undoped region for the purpose of doping itto a desired concentration level. Specific doping profiles are achievable with ion
implantation which cannot be achieved by diffusion alone.
Deposition: Depositing various films on to the wafer. Used to deposit dielectricswhich cannot be grown because of the type of underlying material. Depositionmethods are used to lay down polysilicon, metal, and the dielectric between them.
Etching: Removal of material sensitive to the etch process. For example, etchingis used to eliminate unwanted polysilicon after it has been laid out by deposition.
Problem 2.1-2What is the difference between positive and negative photoresist and how is photoresist
used?
Positive: Exposed resist changes chemically so that it can dissolve upon exposureto light. Unexposed regions remain intact.
Negative: Unexposed resist changes chemically so that it can dissolve uponexposure to light. Exposed regions remain intact.
Photoresist is used as a masking layer which is paterned appropriately so thatcertain underlying regions are exposed to the etching process while those regionscovered by photoresist are resistant to etching.
Problem 2.1-3Illustrate the impact on source and drain diffusions of a 7° angle off perpendicular ionimplant. Assume that the thickness of polysilicon is 8000 Å and that out diffusion frompoint of ion impact is 0.07 µ m.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
15/508
CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 2
Figure P2.1-3
Ion implantation
After ion implantation
After diffusionPolysilicon
Gate
7o
Implanted ions
Implanted ions
diffused
Polysilicon
Gate
Polysilicon
Gate
Polysilicon
Gate
No overlap of
gate to diffusionSignificant overlap of
polysilicon to gate
(a)
(b)
(c)
Problem 2.1-4What is the function of silicon nitride in the CMOS fabrication process described inSection 2.1
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
16/508
CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 3
The primary purpose of silicon nitride is to provide a barrier to oxygen so that whendeposited and patterned on top of silicon, silicon dioxide does not form below where thesilicon nitride exists.
Problem 2.1-5
Give typical thickness for the field oxide (FOX), thin oxide (TOX), n+ or p+, p-well, andmetal 1 in units of µ m.FOX: ~ 1 µ mTOX: ~ 0.014 µ m for an 0.8 µ m processN+/p+: ~ 0.2 µ mWell: ~ 1.2 µ mMetal 1: ~ 0.5 µ m
Problem 2.2-1Repeat Example 2.2-1 if the applied voltage is -2 V.
N A = 5 × 1015 /cm3, N D = 1020 /cm3
φ o = kT
q ln
! ""#
$%% & N A N D
n2
i
=1.381×10-23×300
1.6×10-19 ln ! "#
$% &5×1015×1020
(1.45×1010)2 = 0.9168
xn='()
*+,2ε si(φ o−v D) N A
qN D( N A + N D)
1/2
='()
*+,2×11.7×8.854×10-14 (0.9168 +2.0) 5×1015
1.6×10-19×1020 ( 5×1015 + 1020)
1/2
= 43.5×10-12 m
x p = −'()
*+,2ε si(φ o − v D) N D
qN A( N A + N D)
1/2
='()
*+,2×11.7×8.854×10-14 (0.9168 +2.0) 1020
1.6×10-19×5×1015 ( 5×1015 + 1020)
1/2
= −0.869 µm
xd = xn − x p = 0 + 0.869 µm = 0.869 µm
C j0 = dQ jdv D = A
'()
*+,ε siqN A N D2( N A + N D) (φ o)
1/2
C j0 = 1×10-3×1×10-3 '()
*+,11.7×8.854×10-14×1.6×10-19×5×1015×1×1020
2(5×1015+1×1020) (0.917)
1/2
= 21.3 fF
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
17/508
CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 4
C j0 = C j0
! "#
$% &
1 − φ 0v D
1/2 =21.3 fF
! "#
$% &1 −
-20.917
1/2 = 11.94 fF
Problem 2.2-2Develop Eq. (2.2-9) using Eqs. (2.2-1), (2.2-7), and (2.2-8).
Eq. 2.2-1
xd = xn − x p
Eq. 2.2-7
xn = '()
*+,2ε si(φ o − v D) N A
qN D( N A + N D)
1/2
Eq. 2.2-8
x p = − '()
*+,2ε si(φ o − v D) N D
qN A( N A + N D)
1/2
xd = '(()
*++,2ε si(φ o − v D) N
2 A
+ 2ε si(φ o − v D) N 2
D
qN A N D ( N A + N D)
1/2
xd = (φ o − v D)1/2 '((
)
*++
,2ε si!
#
$
& N 2
A
+ N 2
DqN A N D ( N A + N D)
1/2
Assuming that 2 N A N D
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
18/508
CMOS Analog Circuit Design (2nd Ed.) Homework Solutions: 9/21/2002 5
Referring to Figure P2.2-3
N D
x0
ND - NA (cm-3)
x0
x p
E 0
x
x
xd
φ0− v D
-N A
qN D
-qN A
xn
Figure P2.2-3
E(x)
V(x)
ρ(x)
ND - NA = ax
Using Poisson’s equation in one dimension
d 2V
dx2 = -
ρ (x)
ε
ρ (x)= qax , when x p < x < xn
d 2V
dx2 = -
qax
ε
E(x) = -dV
dx =
qa
2ε x2 + C1
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
19/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 6
E(x p) = E(xn) = 0
then
0 =
qa
2ε x
2
p + C 1
C 1 = -qa
2ε x
2
p
E(x) = qa
2ε x2 −
qa
2ε x
2
p =qa
2ε ! #
$ & x2 − x
2
p
The voltage across the junction is given as
V = −-./
x p
xn E(x)dx = −
qa
2ε -./
x p
xn
! #
$ & x2 - x
2
p dx
V = −qa
2ε
000
! "#
$% & x3
3 − x
2
p x
xn
x p
V = −qa
2ε '(
()
*+
+,
! "
"#
$%
% & x3
n
3 − x2
p xn − ! "
"#
$%
% & x3
p
3 − x2
p x p
V = −qa
2ε '(()
*++,
! ""#
$%% & x
3
n
3 − x
2
p xn − x3
p! "#
$% &1
3 − 1 = −
qa
2ε '(()
*++, x
3
n
3 − x
2
p xn +2
3 x
3
p
Since - x p = xn
V = −qa
2ε
'(()
*++,
− x
3
p
3
+ x3
p +2
3
x3
p = −qa
2ε
x3
p'()
*+,
−1
3
+ 1 +2
3
= −qa
2ε
x3
p! "# $% &4
3
V = −2qa
3ε x
3
p
V represents the barrier potential across the junction, φ 0 − V D. Therefore
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
20/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 7
φ 0 − V D = 2qa
3ε x
3
p
x p = − xn = ! "#
$% &3ε
2qa
1/3
(φ 0 − V D)1/3
Problem 2.2-4
Plot the normalized reverse current, i RA / i R , versus the reverse voltage v R of a silicon pn
diode which has BV = 12 V and n = 6.
i RA
i R =
'()
*+,1
1 − (v R / BV )n
0
2
4
6
8
10
12
0 2 4 6 8 10 12 14
VR
iRA
/iR
Figure P2.2-4
Problem 2.2-5
What is the breakdown voltage of a pn junction with N A = N D = 1016 /cm3?
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
21/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 8
BV ≅ ε si( N A + N D)
2qN A N D E
2max
BV ≅ 11.7×8.854×10-14 (1016 + 1016)
2×1.6×10-19×1016 ×1016 (3×105)
2 = 58.27 volts
Problem 2.2-6
What change in v D of a silicon pn diode will cause an increase of 10 (an order of
magnitude) in the forward diode current?
i D = I s '()
*+,
exp! "#
$% &v D
V t − 1 ≅ I s exp !
"#
$% &v D
V t
10 i D i D
= I s exp !
"#
$% &v D1
V t
I s exp! "#
$% &v D2
V t
=exp !
"#
$% &v D1
V t
exp! "#
$% &v D2
V t
= exp! "#
$% &
v D1- v D2
V t
10 = exp! "#
$% &v D1- v D2
V t
V t ln(10) = v D1- v D2
25.9 mV × 2.303 = 59.6 mV = v D1- v D2
v D1- v D2 = 59.6 mV
Problem 2.3-1
Explain in your own words why the magnitude of the threshold voltage in Eq. (2.3-19)
increases as the magnitude of the source-bulk voltage increases (The source-bulk pn
diode remains reversed biased.)
Considering an n-channel device, as the gate voltage increases relative to the bulk,the region under the gate will begin to invert. What happens near the source? If the
source is at the same potential as the bulk, then the region adjacent to the edge of
the source inverts as the rest of the bulk region under the gate inverts. However, if
the source is at a higher potential than the bulk, then a greater gate voltage is
required to overcome the electric field induced by the source. While a portion of
the region under the gate still inverts, there is no path of current flow to the source
because the gate voltage is not large enough to invert right at the source edge. Once
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
22/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 9
the gate is greater than the source and increasing, then the region adjacent to the
source can begin to invert and thus provide a current path into the channel.
Problem 2.3-2
If V SB = 2 V, find the value of V T for the n-channel transistor of Ex. 2.3-1.
2φ F = -0.940
γ = 0.577
V T 0 = 0.306
V T = V T 0 + γ ( |−2φ F + vSB| − |−2φ F |)
V T = 0.306 + 0.577 ( |0.940 + 2| − |0.940|) = 0.736 volts
V T = 0.736 volts
Problem 2.3-3
Re-derive Eq. (2.3-27) given that V T is not constant in Eq. (2.3-22) but rather varies
linearly with v( y) according to the following equation.
V T = V T 0 + a v(y)
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
23/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 10
i D = W µ nC ox
L
'()
*+,
(vGS − V T 0 ) v DS − (1 + a)v DS
2
2
Problem 2.3-4
If the mobility of an electron is 500 cm2 /(V⋅s) and the mobility of a hole is 200 cm2 /(V⋅s),compare the performance of an n-channel with a p-channel transistor. In particular,
consider the value of the transconductance parameter and speed of the MOS transistor.
Since K’ = µC ox, the transconductance of an n-channel transistor will be 2.5 time greaterthan the transconductance of a p-channel transistor. Remember that mobility will degrade
as a function of terminal conditions so transconductance will degrade as well. The speed
of a circuit is determined in a large part by the capacitance at the terminals and the
transconductance. When terminal capacitances are equal for an n-channel and p-channel
transistor of the same dimensions, the higher transconductance of the n-channel results ina faster circuit.
Problem 2.3-5
Using Ex. 2.3-1 as a starting point, calculate the difference in threshold voltage between
two devices whose gate-oxide is different by 5% (i.e., t ox = 210 Å).
φ F (substrate) = −0.0259 ln'()
*+,3× 1016
1.45 × 1010 = −0.377 V
φ F (gate) = 0.0259 ln'()
*+,4 × 1019
1.45 × 1010 = 0.563 V
φ MS = φ F (substrate) − φ F (gate) = −0.940 V.
C ox = ε ox / t ox = 3.9 × 8.854 × 10-14
210 × 10-8 = 1.644 × 10-7 F/cm2
Qb0 = − ! #
$ &
2 × 1.6 × 10-19 × 11.7 × 8.854 × 10-14 × 2 × 0.377 × 3 × 10161/2
= − 8.66 × 10-8 C/cm2.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
24/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 11
Qb0
C ox =
−8.66 × 10-8
1.644 × 10-7 = −0.5268 V
Qss
C ox
= 1010 × 1.60 × 10-19
1.644 × 10-7 = 9.73 × 10
-3 V
V T 0 = − 0.940 + 0.754 + 0.5268 − 9.73 × 10-3 = 0.331 V
γ = ')
*,
2 × 1.6 × 10-19
× 11.7 × 8.854 × 10-14
× 3 × 1016
1/2
1.644 × 10-7 = 0.607 V
1/2
Problem 2.3-6
Repeat Ex. 2.3-1 using N A = 7 × 1016 cm-3, gate doping, N D = 1 × 10
19 cm-3.
φ F (substrate) = −0.0259 ln'()
*+,7× 1016
1.45 × 1010 = −0.3986 V
φ F (gate) = 0.0259 ln'()
*+,1 × 1019
1.45 × 1010 = 0.527 V
φ MS = φ F (substrate) − φ F (gate) = −0.9256 V.
C ox = ε ox / t ox = 3.9 × 8.854 × 10-14
200 × 10-8 = 1.727 × 10-7 F/cm2
Qb0 = − ! #
$ &
2 × 1.6 × 10-19 × 11.7 × 8.854 × 10-14 × 2 × 0.3986 × 7 × 10161/2
= − 13.6 × 10-8 C/cm2.
Qb0
C ox =
−13.6 × 10-8
1.727 × 10-7 = −0.7875 V
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
25/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 12
Qss
C ox =
1010 × 1.60 × 10-19
1.727 × 10-7 = 9.3 × 10
-3 V
V T 0
= − 0.9256 + 0.797 + 0.7875 − 9.3 × 10-3 = 0.6496 V
γ = ')
*,
2 × 1.6 × 10-19
× 11.7 × 8.854 × 10-14
× 7 × 1016
1/2
1.727 × 10-7 = 0.882 V
1/2
Problem 2.4-1
Given the component tolerances in Table 2.4-1, design the simple lowpass filter
illustrated in Fig P2.4-1 to minimize the variation in pole frequency over all process
variations. Pole frequency should be designed to a nominal value of 1MHz. You mustchoose the appropriate capacitor and resistor type. Explain your reasoning. Calculate the
variation of pole frequency over process using the design you have chosen.
R
Figure P2.4.1
Cvin vout
- To minimize distortion, we would choose minimum voltage coefficient for
resistor and capacitor.
- To minimize variation, we choose components with the lowest tolerance.
The obvious choice for the resistor is Polysilicon. The obvious choice for the capacitor is
the MOS capacitor. Thus we have the following:
We want ω-3dB=2π×106
= 1/RC
C = 2.2 fF/ µm2 to 2.7 fF/ µm2 ; R = 20 Ω / ! to 40 Ω / !
Nominal values are
C = 2.45 fF/ µm2 ; R = 30 Ω / !
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
26/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 13
In order to minimize total area used, you can do the following:
Set resistor width to 5µm (choosing a different width is OK).Define:
N = the number of squares for the resistor
AC = area for the capacitor.Then:
R = N × 30
C = AC × C’ (use C’ to avoid confusion)We want:
RC =1
2π×106
Total area = Atot= N×25+AC
Atot = 25×N + 1.59×106
N
To minimize area, set
∂Atot∂N
= 25 − 1.59×106
N2 = 0
N = 252 1 AC = 6308 µm2
Nominal values for R and C:
R = 7.56 k Ω ;
C = 15.45 pF
Minimum values for R and C:
R = 5.04 k Ω ;
C = 13.88 pF
Maximum values for R and C:
R = 10.08 k Ω ; C = 17.03 pF
Max pole frequency =1
(2π)(5.04k) (13.88pF) 1 2.275 MHz
Min pole frequency =1
(2π)(10.08k) (17.03pF) 1 927 kHz
Problem 2.4-2
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
27/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 14
List two sources of error that can make the actual capacitor, fabricated using a CMOS
process, differ from its designed value.
Sources of error are:
- Variations in oxide thickness between the capacitor plates
-
Dimensional variations of the plates due to the tolerance in-
Etch
- Mask
-
Registration error (between layers)
Problem 2.4-3
What is the purpose of the n+ implantation in the capacitor of Fig. 2.4-1(a)?
The implant is required to form a diffusion with a doping similar to that of the drain and
source. As the voltage across the capacitor varies, depleting the bottom plate of carriers
causes the capacitor to have a voltage coefficient which can have a bad effect on analog
performance. With a highly-doped diffusion below the top plate, voltage coefficient isminimized.
Problem 2.4-4
Consider the circuit in Fig. P2.4-4. Resistor R1 is an n-well resistor with a nominal value of
10 k Ω when the voltage at both terminals is 3 V. The input voltage, vin, is a sine wave with anamplitude of 2 VPP and a dc component of 3 V. Under these conditions, the value of R1 is given
as
R1 = Rnom
'
()
*
+,
1 + K
!
"#
$
% &vin + vout
2
where Rnom is 10K and the coefficient K is the voltage coefficient of an n-well resistor
and has a value of 10K ppm/V. Resistor R2 is an ideal resistor with a value of 10 k Ω.Derive a time-domain expression for vout . Assume that there are no frequency
dependencies.
TBD
Problem 2.4-5
Repeat problem 21 using a P+ diffused resistor for R1. Assume that a P+ resistor’svoltage coefficient is 200 ppm/V. The n-well in which R1 lies, is tied to a 5 volt supply.
TBD
Problem 2.4-6
Consider problem 2.4-5 again but assume that the n-well in which R1 lies is not
connected to a 5 volt supply, but rather is connected as shown in Fig. P2.4-6.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
28/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 15
R1
Figure P2.4-6
vin vout R2Rn-well
p- substrate
FOX
n-well
n+
FOX
p+ diffusion
Voltage effects a resistor’s value when the voltage between any point along the currentpath in the resistor and the material in which it lies. The voltage difference causes a
depletion region to form in the resistor, thus increasing its resistance. This idea is
illustrated in the diagram below.
n-well
p+ diffusion
+
Vx -
I
V
1
x
+
0 Volts
-
Voltage difference
causes depletion region
narrowing the current path
VDD
VDD
In order to keep the depletion region from varying along the direction of the current path,
the potential of the material below the p+ diffusion (n-well in this case) must vary in the
same way as the potential of the p+ diffusion. This is accomplished by causing current toflow in the underlying material (n-well) in parallel with the current in the p+ diffusion as
illustrated below.
n-well
p+ diffusion
Ip+
V1
x
In-well
∆Vp+
∆Vn-well
Rp+
Rn-well
Vx
VDD
VDD
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
29/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 16
It is easy to see that if ∆V p+ = ∆Vn-well then V x = 0. Thus by attaching the n-well inparallel with the desired current path, the effects of voltage coefficient of the p+ material
are eliminated. There is a second-order effect due to the fact that the n-well resistor will
have a voltage coefficient due to the underlying material (p- substrate) tied to ground.
Even with this non-ideal effect, significant improvement is achieved by this method.
Problem 2.5-1
Assume v D = 0.7 V and find the fractional temperature coefficient of I s and v D.
1
I s dI s
dT =
3
T +
1
T V Go
V t =
3
300 +
1
300
1.205
0.0259 = 0.1651
dv D
dT = −
'()
*+,V Go 1.942 × 10-3 v D
T −
3V t
T = −
'()
*+,1.205 − 0.7
300 −
3×0.0259300
= 1.942 × 10-3
1 v D
dv D
dT = 1.942 × 10
-3
0.7 = 2.775 × 10-3
Problem 2.5-2
Plot the noise voltage as a function of the frequency if the thermal noise is 100 nV/ Hz
and the junction of the 1/ f and thermal noise (the 1/ f noise corner) is 10,000 Hz.
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
10 µV/ Hz
1 µV/ Hz
100 nV/ Hz
frequency
noise
voltage
Problem 2.6-1
Given the polysilicon resistor in Fig. P2.6-1 with a resistivity of ρ = 8×10-4 Ω-cm,calculate the resistance of the structure. Consider only the resistance between contact
edges. ρ s = 50 Ω / ❑
Fix problem: Eliminate . ρ ρρ ρ s = 50 ΩΩΩΩ / ❑❑❑❑ because it conflicts with ρ ρρ ρ = 8××××10-4 ΩΩΩΩ-cm
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
30/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 17
R = ρ L
W T =
8×10-4 × 3×10-4
1×10-4 × 8000×10-8 = 30 Ω
Problem 2.6-2Given that you wish to match two transistors having a W/L of 100µm/0.8µm each.Sketch the layout of these two transistors to achieve the best possible matching.
Best matching is achieved using the following principles:
-
unit matching
- common centroid
- photolithographic invariance
Figure P2.6-2
Metal 2
Metal 2
Via 1
Metal 1
25 µm
0.8 µm
Problem 2.6-3
Assume that the edge variation of the top plate of a capacitor is 0.05µm and that capacitortop plates are to be laid out as squares. It is desired to match two equal capacitors to an
accuracy of 0.1%. Assume that there is no variation in oxide thickness. How large would
the capacitors have to be to achieve this matching accuracy?
Since capacitance is dominated by the area component, ignore the perimeter (fringe)
component in this analysis. The units in the analysis that follows is micrometers.
C = C AREA
(d ± 0.05)2
where d is one (both) sides of the square capacitor.
C 1
C 1 =
(d + 0.05)2
(d − 0.05)2 = 1.001
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
31/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 18
C 1
C 1 =
(d + 0.05)2
(d − 0.05)2 = 1.001
d2 + 0.1d + 0.052 = 1.001! #
$ &
d2 − 0.1d + 0.052
Solving this quadratic yields
d = 200.1
Problem 2.6-4
Show that a circular geometry minimizes perimeter-to-area ratio for a given area
requirement. In your proof, compare against rectangle and square.
Acircle = π r2
Asquare = d2
if Asquare = Acircle
then
r = d π
π
Pcircle Psquare
= 2d π
4d=
π 2
< 1
Ideally,C perimeter
C area = 0, so since
Pcircle
Psquare < 1, the impact of perimeter on a circle is less
than on a square.
Problem 2.6-5
Show analytically how the Yiannoulos-path technique illustrated in Fig. 2.6-5 maintains a
constant area-to-perimeter ratio with non-integer ratios.
Area of one unit is:
Au = L2
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
32/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 19
Total area = N × Au
Total periphery = 2(N + 1)
C Total = KA × N × Au + KP × 2(N + 1)
where KA and KP represent area and perimeter capacitance (per unit area and per unit
length) respectively.
Consider two capacitors with different numbers of units but drawn following the template
shown in Fig. 2.6-5(a). Their ratio would be
Figure P2.6-5 (a)
One unit
L
L
C 1 C 2
=K
A
× N1
× Au + K
P
× 2(N1
+ 1)
KA × N2 × Au + KP × 2(N2 + 1)
The ratio of the area and peripheral components by themselves are
! "#
$% &C 1
C 2 AREA =
KA × N1 × Au
KA × N2 × Au =
N1 N2
!
"#
$
% &C 1
C
2 PER
=KP × 2(N1 + 1)
KP
× 2(N2
+ 1) =
N1 + 1
N2
+ 1
N1 + 1
N2 + 1 ≠
N1
N2 unless N1= N2
Therefore, the structure in Fig. P2.6-5(a) cannot achieve constant area to perimeter ratio.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
33/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 20
Consider Fig. P2.6-5(b).
Figure P2.6-5 (b)
One unit
Total area = (N + 1) × Au
Total periphery = 2(N + 1) (as before)
Notice what has happened. By adding the extra unit area, two peripheral units areeliminated but two additional ones are added resulting in no change in total periphery.
However, one additional area has been added. Thus
C 1
C 2 =
KA × (N1 + 1) × Au + KP × 2(N1 + 1)
KA × (N2 + 1) × Au + KP × 2(N2 + 1)
The ratio of the area and peripheral components by themselves are
! "#
$% &C 1
C 2 AREA =
KA × (N1 + 1) × Au
KA × (N2 + 1) × Au =
N1 + 1
N2 + 1
! "#
$% &C 1
C 2 PER =
KP × 2(N1 + 1)
KP × 2(N2 + 1) =
N1 + 1
N2 + 1
N1 + 1
N2 + 1 =
N1 + 1
N2 + 1 !!!
Problem 2.6-6Design an optimal layout of a matched pair of transistors whose W/L are 8 µ m/1 µ m. The
matching should be photolithographic invariant as well as common centroid.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
34/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 21
Figure P2.6-6
Metal 2
Metal 2
Via 1
Metal 1
2 µm
1 µm
Problem 2.6-7
Figure P2.6-7 illustrates various ways to implement the layout of a resistor divider.
Choose the layout that BEST achieves the goal of a 2:1 ratio. Explain why the otherchoices are not optimal.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
35/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 22
A
B
A B
R
2R
A
B
A
B
(a)
AB2x x
(b)
A
B
(c)
A
B
(d) (e)
(f)
Figure P2.6-7
Option A suffers the following:
- Orientation of the 2R resistor is partly orthogonal to the 1R resistor. Matched resistors should
have the same orientation.
- Resistors do not have the appropriate etch compensating (dummy) resistors. Dummy stripesshould surround all active resistors.
Option B suffers the following:
-
Resistors do not have the appropriate etch compensating (dummy) resistors. Dummy stripesshould surround all active resistors.
- Resistors do not share a common centroid as they should.
Option C suffers the following:
- Resistors do not share a common centroid as they should.
- Uncertainty is introduced with the additional notch at the contact head.
Option D suffers the following:
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
36/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 23
- Resistors do not have the appropriate etch compensating (dummy) resistors. Dummy stripes
should surround all active resistors.
Option E suffers the following:
- Nothing
Option F suffers the following:- Violates the unit-matching principle
- Resistors do not have the appropriate etch compensating (dummy) resistors. Dummy stripes
should surround all active resistors.
- Resistors do not share a common centroid as they should.
Unit Matching Etch Comp. Orientation Common
Centroid
(a) Yes No No Yes
(b) Yes No Yes No
(c) Yes Yes Yes No
(d) Yes No Yes Yes
(e) Yes Yes Yes Yes(f) No No Yes No
Clearly, option (e) is the best choice.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
37/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 1
Chapter 3 Homework Solutions
Problem 3.1-1
Sketch to scale the output characteristics of an enhancement n-channel device if V T = 0.7
volt and I D = 500 µ A when V GS = 5 V in saturation. Choose values of V GS = 1, 2, 3, 4,
and 5 V. Assume that the channel modulation parameter is zero.
0.00E+00
1.00E-04
2.00E-04
3.00E-04
4.00E-04
5.00E-04
6.00E-04
0 1 2 3 4 5 6
V GS
I DS
Problem 3.1-2
Sketch to scale the output characteristics of an enhancement p-channel device if V T = -0.7
volt and I D = -500 µ A when V GS = -1, -2, -3, -4, and -6 V. Assume that the channelmodulation parameter is zero.
-6.00E-04
-5.00E-04
-4.00E-04
-3.00E-04
-2.00E-04
-1.00E-04
0.00E+00
-6 -5 -4 -3 -2 -1 0
V GS
I DS
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
38/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 2
Problem 3.1-3
In Table 3.1-2, why is γ P greater than γ N for a n-well, CMOS technology?
The expression for γ is:
γ = 2ε si q N SUB
C ox
Because γ is a function of substrate doping, a higher doping results in a larger value for γ .In general, for an nwell process, the well has a greater doping concentration than the
substrate and therefore devices in the well will have a larger γ .
Problem 3.1-4
A large-signal model for the MOSFET which features symmetry for the drain and source
is given as
i D = K 'W
L !"#
$%&
[(vGS − V TS )2 u(vGS − V TS )] − [(vGD − V TD)
2 u(vGD − V TD)]
where u( x) is 1 if x is greater than or equal to zero and 0 if x is less than zero (step
function) and V TX is the threshold voltage evaluated from the gate to X where X is either S
(Source) or D (Drain). Sketch this model in the form of i D versus v DS for a constant value
of vGS (vGS > V TS ) and identify the saturated and nonsaturated regions. Be sure to extendthis sketch for both positive and negative values of v DS . Repeat the sketch of i D versus
v DS for a constant value of vGD (vGD > V TD). Assume that both V TS and V TD are positive.
vGS constant
vGDconstant
vGD-V TD>0
vGS -V TS >0vGS -V TS
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
39/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 3
Problem 3.1-5
Equation (3.1-12) and Eq. (3.1-18) describe the MOS model in nonsaturation and
saturation region, respectively. These equations do not agree at the point of transition
between saturation and nonsaturation regions. For hand calculations, this is not an issue,
but for computer analysis, it is. How would you change Eq. (3.1-18) so that it would
agree with Eq. (3.1-12) at v DS = v DS (sat)?
i D = K' W
L '()
*+,
(vGS − V T ) − v DS
2 v DS (3.1-12)
i D = K'W
2 L (vGS − V T )
2(1 + λ v DS ), 0 v DS (sat) we can subtract
v DS (sat) from the v DS in the channel-length modulation term. Doing this results in the
following modification of Eq. (3.1-18).
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
40/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 4
i D = K'W
2 L (vGS − V T )
2 ')
*,1 + λ (v DS
− v DS (sat)) , 0
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
41/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 5
C GB = 700 × 10-12 (822 × 10-9) = 575 × 10-18
C GS = CGSO(W eff ) + 0.67C ox(W eff )( Leff )
C GS = 220 × 10-12 × 5 × 10-6 + 0.67 × 24.7 × 10-4 × 822 × 10-9 × 5 × 10-6
C GS = 7.868 × 10-15
C GD = C 3 ≅ C ox(LD)(W eff ) = CGDO(W eff )
C GD = CGDO(W eff ) = 220 × 10-12 × 5 × 10-6 = 1.1 × 10-15
Nonsaturated
C GB = 2C 5 = CGBO ( Leff )
C GB = CGBO ( Leff ) = 700 × 10-12
× 822 × 10-9
= 574 × 10-18
C GS = (CGSO + 0.5C ox Leff )W eff
C GS = (220 × 10-12 + 0.5 × 24.7 × 10-4 × 822 × 10-9) × 5 × 10-6 = 6.18 × 10-15
C GD = (CGDO + 0.5C ox Leff )W eff
C GD = (220 × 10-12 + 0.5 × 24.7 × 10-4 × 822 × 10-9) × 5 × 10-6 = 6.18 × 10-15
Problem 3.2-2
Find C BX at V BX = 0 V and 0.75 V of Fig. P3.7 assuming the values of Table 3.2-1 apply
to the MOS device where FC = 0.5 and PB = 1 V. Assume the device is n-channel andrepeat for a p-channel device.
Change problem to read: “|V BX |==== 0 V and 0.75 V (with the junction always reversebiased)…”
1.6µm
Figure P3.2-2
2.0µm
Polysilicon
Metal
Active Area
0.8µm
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
42/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 6
AX = 1.6 × 10-6 × 2.0 × 10-6 = 3.2 × 10-12
PX = 2×1.6 × 10-6 + 2.0 × 2.0 × 10-6 = 7.2 × 10-6
NMOS case:
C BX = (CJ)(AX)
'()
*+,
1 − - ./
01 2v BX
PB
MJ + (CJSW)(PX)
'()
*+,
1 − - ./
01 2v BX
PB
MJSW
C BX = (770 × 10-6)( 3.2 × 10-12)
'()
*+,
1 − - ./
01 20
PB
MJ + (380 × 10-12)( 7.2 × 10-6)
'()
*+,
1 − - ./
01 20
PB
MJSW = 5.2 × 10-15
PMOS case:
C BX = (560 × 10-6)( 3.2 × 10-12)
'()
*+,
1 − - ./
01 20
PB
MJ + (350 × 10-12)( 7.2 × 10-6)
'()
*+,
1 − - ./
01 20
PB
MJSW = 4.31 × 10-15
|v BX | = 0.75 volts reverse biased
NMOS case:
C BX = (CJ)(AX)
'()
*+,
1 − - ./
01 2v BX
PB
MJ + (CJSW)(PX)
'()
*+,
1 − - ./
01 2v BX
PB
MJSW ,
C BX = (770 × 10-6)( 3.2 × 10-12)
'()
*+,
1 − - ./
01 2-0.75
1
0.5 +
(380 × 10-12)( 7.2 × 10-6)
'()
*+,
1 − - ./
01 2-0.75
1
0.38
C BX = 2.464 × 10-15
1.323 +
2.736 × 10-15
1.237 = 4.07 × 10-15
PMOS case:
C BX = (560 × 10-6)( 3.2 × 10-12)
'()
*+,
1 − - ./
01 2-0.75
1
0.5 +
(350 × 10-12)( 7.2 × 10-6)
'()
*+,
1 − - ./
01 2-0.75
1
0.35
C BX = 1.79 × 10-15
1.323 +
2.52 × 10-15
1.216 = 3.425 × 10-15
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
43/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 7
Problem 3.2-3
Calculate the value of C GB, C GS , and C GD for an n-channel device with a length of 1 µ m
and a width of 5 µ m. Assume V D = 2 V, V G = 2.4 V, and V S = 0.5 V and let V B = 0 V.Use model parameters from Tables 3.1-1, 3.1-2, and 3.2-1.
LD = 220 × 10-12
24.7 × 10-4 ≅ 89 × 10-9
Leff = L - 2 × LD = 1 × 10-6 − 2 × 89 × 10-9 = 822 × 10-9
V T
= V T 0
+ γ [ ]2|φ F
| + vSB
− 2|φ F
|
V T = 0.7 + 0.4 [ ]0.7 + 0.5 − 0.7 = 0.803
vGS − vT =2.4 − 0.5 − 0.803 = 1.096 < v DS thus saturation region
C GB = CGBO x Leff = 700 × 10-12 × 822 × 10-9 = 0.575 fF
C GS = CGSO(W eff ) + 0.67C ox(W eff )( Leff )
C GS = 220 × 10-12 × 5 × 10-6 + 0.67 × 24.7 × 10-4 × 822 × 10-9 × 5 × 10-6
C GS = 7.868 × 10-15
C GD = C 3 ≅ C ox(LD)(W eff ) = CGDO(W eff )
C GD = CGDO(W eff ) = 220 × 10-12 × 5 × 10-6 = 1.1 × 10-15
Problem 3.3-1
Calculate the transfer function vout (s)/vin(s) for the circuit shown in Fig. P3.3-1. The
W/L of M1 is 2µm/0.8µm and the W/L of M2 is 4µm/4µm. Note that this is a small-signal analysis and the input voltage has a dc value of 2 volts.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
44/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 8
Figure P3.3-1
5 Volts
v IN
= 2V (dc)
+ 1mV (rms)
vout
+
-
W/L = 2/0.8
W/L = 4/4
M1
M2
v IN
= 2V (dc)
+ 1mV (rms)
RM1
CM2
Figure P3.3-1b
vout
+
-
vout(s)
vIN (s) =
1 /SC M2 RM1 + 1 /SC M2
=1
SC M2 RM1 + 1
V T 1 = V T 0 + γ [ ]2|φ F | + vSB − 2|φ F |
V T 1 = 0.7 + 0.4 [ ]0.7 + 2.0 − 0.7 = 1.02
RM1 =1
K'(W/L)M1 (vGS 1 − V T 1) = 1.837 k Ω
C M2 = W M2 × LM2 × C ox = 4 × 10-6 × 4 × 10-6 × 24.7 × 10-4 = 39.52 × 10-15
RM1
C M2
= 1.837 k Ω × 39.52 × 10-15 = 72.6 × 10-12
vout(s)
vIN (s) ==
1
S
13.77 × 109 + 1
Problem 3.3-2
Design a low-pass filter patterened after the circuit in Fig. P3.3-1 that achieves a -3dB
frequency of 100 KHz.
1
2π RC = 100,000
There is more than one answer to this problem because there are two free parameters.
Use the resistance from Problem 3.3-1.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
45/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 9
RM1 = 1.837 k Ω
CM2 =1
2π ×1.837× 103
×1 × 105 = 866.4 pF
Choose W = L
C M2 = W M2 × LM2 × C ox = W 2
M2 × 24.7 × 10-4 = 866.4 × 10-12
W 2
M2 = 350.8 × 10-9
W M2 = 592 × 10-6
Problem 3.3-3Repeat Examples 3.3-1 and 3.3-2 if the W / L ratio is 100 µ m/10 µ m.
Problem correction: Assume λλλλ = 0.01.
Repeat of Example 3.3-1
N-Channel Device
gm = (2K 'W / L)| I D|
gm = 2×110 × 10-6 ×10 × 50 × 10-6 = 332 × 10-6
gmbs = gm γ
2(2|φ F | + V SB)1/2
gmbs = 332 × 10-6
0.4
2(0.7+2.0)1/2 = 40.4 × 10-6
gds = I D λ
gds = 50 × 10-6 × 0.01 = 500 × 10-9
P-Channel Device
gm = (2K 'W / L)| I D|
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
46/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 10
gm = 2×50 × 10-6 ×10 × 50 × 10-6 = 224 × 10-6
gmbs = gm γ
2(2|φ F | + V SB)1/2
gmbs = 224 × 10-6
0.57 2(0.8+2.0)1/2
= 38.2 × 10-6
gds = I D λ
gds = 50 × 10-6 × 0.01 = 500 × 10-9
Repeat of Example 3.3-2
N-Channel Device
gm = β V DS = 110 × 10-6 × 10× 1 = 1.1 × 10-3
gmbs = βγ V DS
2(2|φ F | + VSB)1/2 =
110 × 10-6 ×0.4 ×1× 10
2(0.7+2)1/2 = 134 × 10-6
V T = V T 0 + γ [ ]2|φ F | + vSB − 2|φ F |
V T = 0.7 + 0.4 [ ]0.7 + 2.0 − 0.7 = 1.02
gds = β (V GS − V T − V DS ) = 10 ×110 × 10-6 (5 − 1.02 − 1) = 3.28 × 10-3
P-Channel Device
gm = β V DS = 50 × 10-6 × 10× 1 = 500 × 10-6
gmbs = βγ V DS
2(2|φ F | + VSB)1/2 =
50 × 10-6 ×0.57 ×1× 102(0.8+2)1/2
= 85.2 × 10-6
|V T | = |V T 0| + γ [ ]2|φ F | + v BS − 2|φ F |
|V T | = 0.7 + 0.57 [ ]0.8 + 2.0 − 0.8 = 1.144
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
47/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 11
gds = β (V GS − V T − V DS ) = 10 ×50 × 10-6 (5 − 1.144− 1) = 1.428 × 10-3
Problem 3.3-4
Find the complete small-signal model for an n-channel transistor with the drain at 4 V,gate at 4 V, source at 2 V, and the bulk at 0 V. Assume the model parameters from Tables
3.1-1, 3.1-2, and 3.2-1, and W / L = 10 µ m/1 µ m.
V T = V T 0 + γ [ ]2|φ F | + vSB − 2|φ F |
V T = 0.7 + 0.4 [ ]0.7 + 2.0 − 0.7 = 1.02
I D
= K 'W
2 L
( )v
GS
− vT
2 (1 + λ v
DS
) =110 × 10-6 ×10
2( )2 - 1.02 2(1 + 0.4×2) = 570 × 10-6
gm = (2K 'W / L)| I D|
gm = 2×110 × 10-6 ×10 × 570 × 10-6 = 1.12 × 10-3
gmbs = gm γ
2(2|φ F | + V SB)1/2
gmbs = 1.12 × 10-3
0.4
2(0.7+2.0)1/2 = 136 × 10
-6
gds = I D λ
gds = 570 × 10-6 × 0.04 = 22.8 × 10-9
LD = 220 × 10-12
24.7 × 10-4 ≅ 89 × 10-9
Leff = L - 2 × LD = 1 × 10-6 − 2 × 89 × 10-9 = 822 × 10-9
C GB = CGBO x Leff = 700 × 10-12 × 822 × 10-9 = 0.575 fF
C GS = CGSO(W eff ) + 0.67C ox(W eff )( Leff )
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
48/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 12
C GS = 220 × 10-12 × 10 × 10-6 + 0.67 × 24.7 × 10-4 × 822 × 10-9 × 10 × 10-6
C GS = 15.8 × 10-15
C GD = CGDO(W eff )
C GD = CGDO(W eff ) = 220 × 10-12 × 10 × 10-6 = 2.2 × 10-15
Problem 3.3-5
Consider the circuit in Fig P3.3-5. It is a parallel connection of n mosfet transistors.
Each transistor has the same length, L, but each transistor can have a different width, W .
Derive an expression for W and L for a single transistor that replaces, and is equivalent to,
the multiple parallel transistors.
The expression for drain current in saturation is:
I D = K 'W 2 L
( )vGS − vT 2 (1 + λ v DS )
For multiple transistors with the same drain, gate, and source voltage, the drain current
can be expressed simply as
I D(i) = - ./
01 2W
L i ( )vGS − vT
2 (1 + λ v DS )
The drain current in each transistor is additive to the total current, thus
I D(TOTAL) = ( )vGS − vT 2 (1 + λ v DS )
'()
*+,3- .
/ 01 2W
L i
Since the lengths are the same, we have
I D(TOTAL) = 1
L( )vGS − vT
2 (1 + λ v DS ) '
()
*+,3W i
Problem 3.3-6
Consider the circuit in Fig P3.3-6. It is a series connection of n mosfet transistors. Eachtransistor has the same width, W , but each transistor can have a different length, L.
Derive an expression for W and L for a single transistor that replaces, and is equivalent to,
the multiple parallel transistors. When using the simple model, you must ignore body
effect.
Error in problem statement : replace “parallel” with “series”
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
49/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 13
Figure P3.3-6
M1
M2
Mn
Assume that all devices are in the non-saturation region.
Consider the case for two transistors in series as illustrated below.
M1
M2
v1
v2
vG
M3
v2
vG
The drain current in M1 is
i1 = K'W
L '(()
*++,
(vGS − V T ) v DS − v
2
DS
2
i1 = β 1 '(
()
*+
+,
(vGS − V T ) v1 −
v2
1
2 = β 1 '(
()
*+
+,
(vG − V T ) v1 −
v2
1
2
i1 = β 1 '(()
*++,
V on v1 − v
2
1
2
where
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
50/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 14
V on = vG − V T
v1 = V on − V 2on
− 2i1
β 1
v2
1 = 2V on − 2V on V 2on
− 2i1
β 1 −
2i1
β 1
The drain current in M2 is
i2 = β 2
'
()
*
+,
(vG − v1 − V T )( v2 − v1) − ( v2 − v1)
2
2
i2 = β 2 '()
*+,
( V on − v1)( v2 − v1) − ( v2 − v1)
2
2
i2 = β 2 '(()
*++,
V on v2 − V onv1 + v
2
1
2 −
v2
2
2
Substitue the earlier expression for v1
and equate the drain currents (drain currents must
be equal)
i2 = β 1 β 2 β 1 + β 2
'(()
*++,
V on v2 − v
2
2
2
The expression for the current in M3 is
i3 = β 3 '(()
*++,
(vGS − V T ) v2 −
v2
2
2 = β 3 '(()
*++,
V on v2 −
v2
2
2
The drain current in M3 must be equivalent to the drain current in M1 and M2, thus
β 3 = β 1 β 2 β 1 + β 2
=- ./
01 21
β 1 +
1
β 2
-1
=- ./
01 2 L1
K'W 1 +
L2
K'W 2
-1
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
51/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 15
Since the widths are equal and the transconductances are equal
β 3 = 1
K'W ( L1 + L2)
This analysis is easily extended to address any number of transistors (repeat the analysis
with M3 and another transistor in series with it—two at a time)
LEQUIVALENT = 3 0
i Li
Problem 3.5-1
Calculate the value for V ON for n MOS transistor in weak inversion assuming that fs and
fn can be approximated to be unity (1.0).
Assume (from Level 1 parameters):
GAMMA = 0.4
PHI = 0.7
COX = 24.7 × 10-4 F/m2
vSB = 0
NFS = 7 × 1015 (m-2) from Table 3.4-1
von = V T + fast
where
fast =kT
q '(()
*++,
1 +q × NFS
COX +
GAMMA × f s (PHI + vSB)1/2 + f n (PHI + vSB)
2(PHI + vSB)
if
f s = f n =1
fast =kT
q '(()
*++,
1 +q × NFS
COX +
GAMMA × (PHI + vSB)1/2 + (PHI + vSB)
2(PHI + vSB)
fast = 0.0259'()
*+,
1 +1.6 × 10-19 × 7 × 1015
24.7 × 10-4 +
0.4 × (0.7 + 0)1/2 + (0.7 + 0)2(0.7 + 0)
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
52/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 16
fast = 0.0259 (1 + .453 + 0.739) = 56.77 × 10-3
von = V T + fast =0.0259 + 56.77 × 10-3 = 82.67 × 10-3
Problem 3.5-2Develop an expression for the small signal transconductance of a MOS device operating
in weak inversion using the large signal expression of Eq. (3.5-5).
i D ≅ W
L I DO exp -
./
01 2vGS
n(kT/q)
gm =∂ I D∂V GS
= W
L - ./
01 21
n(kT/q) I DO exp -
./
01 2vGS
n(kT/q) =
I D
n(kT/q)
Problem 3.5-3
Another way to approximate the transition from strong inversion to weak inversion is to
find the current at which the weak-inversion transconductance and the strong-inversion
transconductance are equal. Using this method and the approximation for drain current in
weak inversion (Eq. (3.5-5)), derive an expression for drain current at the transition
between strong and weak inversion.
gm = W
L - ./
01 21
n(kT/q) I DO exp -
./
01 2vGS
n(kT/q) = (2K 'W / L) I D
- ./
01 2W
L
2 - ./
01 21
n(kT/q)
2
I 2 DO
exp- ./
01 22vGS
n(kT/q) = (2K 'W / L) I D
I D = - ./
01 21
2K ' - ./
01 2W
L - ./
01 2 I DO
n(kT/q)
2
exp- ./
01 22vGS
n(kT/q)
I D = - ./
01 21
2K ' I DO -
./
01 21
n(kT/q)
2
exp- ./
01 2vGS
n(kT/q) ×
- ./
01 2W
L I DO exp -
./
01 2vGS
n(kT/q)
I D = - ./
01 21
2K ' I DO -
./
01 21
n(kT/q)
2
exp- ./
01 2vGS
n(kT/q) × I D
2K ' [n(kT/q)]2 = I DO exp -
./
01 2vGS
n(kT/q) =
I D
W/L
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
53/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 17
I D = 2K 'W
L [n(kT/q)]
2
Problem 3.6-1
Consider the circuit illustrated in Fig. P3.6-1. (a) Write a SPICE netlist that describes
this circuit. (b) Repeat part (a) with M2 being 2µm/1µm and it is intended that M3 andM2 are ratio matched, 1:2.
Part (a)Problem 3.6-1 (a)
M1 2 1 0 0 nch W=1u L=1u
M2 2 3 4 4 pch w=1u L=1u
M3 3 3 4 4 pch w=1u L=1u
R1 3 0 50k
Vin 1 0 dc 1
Vdd 4 0 dc 5
.MODEL nch NMOS VTO=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
.MODEL pch PMOS VTO=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
.op
.end
Part (b)Problem 3.6-1 (b)
M1 2 1 0 0 nch W=1u L=1u
M2 2 3 4 4 pch w=1u L=1u M=2
M3 3 3 4 4 pch w=1u L=1u
R1 3 0 50k
Vin 1 0 dc 1
Vdd 4 0 dc 5
.MODEL nch NMOS VTO=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
.MODEL pch PMOS VTO=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
.op
.end
Problem 3.6-2
Use SPICE to perform the following analyses on the circuit shown in Fig. P3.6-1: (a) Plot
vOUT versus v IN for the nominal parameter set shown. (b) Separately, vary K' and V T by
+10% and repeat part (a)—four simulations.
Parameter N-Channel P-Channel Units
V T 0.7 -0.7 V
K' 110 50 µ A/V2
l 0.04 0.05 V-1
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
54/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 18
vIN
vOUT
R =50k Ω
1
2
3
4
Figure P3.6-1
VDD = 5 V
M1
M2M3
W/L = 1µ/1µ W/L = 1µ/1µ
W/L = 1µ/1µ
Problem 3.6-2
M1 2 1 0 0 nch W=1u L=1u
M2 2 3 4 4 pch w=1u L=1u
M3 3 3 4 4 pch w=1u L=1uR1 3 0 50k
Vin 1 0 dc 1
Vdd 4 0 dc 5
*.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.04
*.MODEL pch PMOS VTO=-0.7 KP=50U LAMBDA=0.05
*
*.MODEL nch NMOS VTO=0.77 KP=110U LAMBDA=0.04
*.MODEL pch PMOS VTO=-0.7 KP=50U LAMBDA=0.05
*
*.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.04
*.MODEL pch PMOS VTO=-0.77 KP=50U LAMBDA=0.05
*
*.MODEL nch NMOS VTO=0.7 KP=121U LAMBDA=0.04
*.MODEL pch PMOS VTO=-0.7 KP=50U LAMBDA=0.05
*
.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.04
.MODEL pch PMOS VTO=-0.7 KP=55U LAMBDA=0.05
.dc vin 0 5 .1
.probe
.end
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
55/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 19
0V 2V 4V
0V
2V
4V
K'N
=121u
VTN
= 0.77
K'P= 55u
VTP
= -0.77
VOUT
VIN
Problem 3.6-3
Use SPICE to plot i2 as a function of v2 when i1 has values of 10, 20, 30, 40, 50, 60, and
70 µ A for Fig. P3.6-3. The maximum value of v2 is 5 V. Use the model parameters of V T = 0.7 V and K' = 110 µ A/V2 and λ = 0.01 V-1. Repeat with λ = 0.04 V-1.
v2
Figure P3.6-3
M1 M2
W/L = 10µm/2µm
i1
i2
W/L = 10µm/2µm
+
−
p3.6-3
M1 1 1 0 0 nch l = 2u w = 10u
M2 2 1 0 0 nch l = 2u w = 10u
I1 0 1 DC 0
V1 3 0 DC 0
V_I2 3 2 DC 0
.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.01 GAMMA = 0.4 PHI = 0.7
*.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.04 GAMMA = 0.4 PHI = 0.7
.dc V1 0 5 .1 I1 10u 80u 10u
.END
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
56/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 20
Lambda = 0.01
V
2
I
2
I
2
= 10uA
I
2
= 20uA
I
2
= 30uA
I
2
= 40uA
I
2
= 50uA
I
2
= 60uA
I
2
= 70uA
10uA
40uA
60uA
80uA
1 2 3 4 5
Lambda = 0.04
V2
I2
I
1
= 10uA
I
1
= 20uA
I
1
= 30uA
I
1
= 40uA
I
1
= 50uA
I
1
= 60uA
I
1
= 70uA
10uA
40uA
60uA
80uA
1 2 3 4 5
Problem 3.6-4
Use SPICE to plot i D as a function of v DS for values of vGS = 1, 2, 3, 4 and 5 V for an n-
channel transistor with V T = 1 V, K' = 110 µ A/V2, and l = 0.04 V-1. Show how SPICE
can be used to generate and plot these curves simultaneously as illustrated by Fig. 3.1-3.
p3.6-4
M1 2 3 0 0 nch l = 1u w = 5u
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
57/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 21
VGS 3 0 DC 0
VDS 4 0 DC 0
V_IDS 4 2 DC 0
.MODEL nch NMOS VTO=1 KP=110U LAMBDA=0.01 GAMMA = 0.4 PHI = 0.7
.dc VDS 0 5 .1 VGS 0 5 1
.END
V
DS
I
DS
2mA
4mA
1 2 3 4 5
0
V
GS
= 5
V
GS
= 4
V
GS
= 3
V
GS
= 2
Problem 3.6-5
Repeat Example 3.6-1 if the transistor of Fig. 3.6-5 is a PMOS having the model
parameters given in Table 3.1-2.
p3.6-5
V_IDS 5 2 DC 0VGS 3 0 DC 0
VDS 5 0 DC 0
M1 2 3 0 0 pch l = 1u w = 5u
.MODEL pch PMOS VTO=-0.7 KP=50U LAMBDA=0.051 GAMMA = 0.57 PHI = 0.8
.dc VDS 0 -5 -.1 VGS 0 -5 -1
.END
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
58/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 22
V
DS
I
DS
1mA
4 3 2 1 0
5
2mA
3mA
0mA
V
GS
= 5
V
GS
= 4
V
GS
= 3
V
GS
= 2
Problem 3.6-6
Repeat Examples 3.6-2 through 3.6-4 for the circuit of Fig. 3.6-2 if R1 = 200 KΩ.
0V 2V 4V
0V
2V
4V
V IN
V OUT
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
59/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 23
AC Analysis
-20
20
40
e2 e4 e6 e8
0
Frequency
vdb(2)
e2 e4 e6 e8
0
-90
Frequency
vp(2)
-45
Transient Analysis
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
60/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 24
2us 6us
0V
2V
4V
4us
0V
2V
4V
0
V(2)
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
61/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 1
Chapter 4 Homework Solutions
Problem 4.1-1
Using SPICE, generate a set of parametric I-V curves similar to Fig. 4.1-3 for a transistor
with a W/L = 10/1. Use model parameters from Table 3.1-2.
Figure P4.1-1
V 1 (volts)
V 1
V G
2.5
I
V G = 1 V
V G = 2 V
V G = 3 V
V G = 4 V
V G = 5 V A B
I (mA)
0.0
5.0
10.0
-2.5 0.0 2.5
Problem 4.1-2
The circuit shown in Fig. P4.1-2 illustrates a single-channel MOS resistor with a W/L of
2µm/1µm. Using Table 3.1-2 model parameters, calculate the small-signal on resistanceof the MOS transistor at various values for V S and fill in the table below.
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
62/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 2
Figure P4.1-2
V S
5 Volts
I = 0.0
The equation for threshold voltage with absolute values so that it can be applied to n-
channel or p-channel transistors without confusion.
|V T |= |V T 0 | + γ !"
#$2|φ F | + |vSB| − 2|φ F |
r ON = 1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T | − |V DS |) =
L
K'W (|V GS | − |V T |) (when V DS = 0)
For n-channel device,
V T 0 = 0.7
γ = 0.4
2|φ F | = 0.7
The table below shows the value of V GS and V SB for each value of V S
V S (volts) V GS (volts) V SB (volts)
0.0 5 0
1.0 4 1
2.0 3 2
3.0 2 3
4.0 1 45.0 0 5
Using V S = 0, calculate V T
|V T |= |V T 0 | + γ !"
#$2|φ F | + |vSB| − 2|φ F | = 0.7 + 0.4[ ]0.7 + 0.0 − 0.7 = 0.7
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
63/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 3
Calculate r on
r ON = 1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T | − |V DS |) =
1
110 µ × 2(5 − 0.7 − 0) = 1057 Ω
Repeat for V S = 1
|V T | = 0.7 + 0.4[ ]0.7 + 1.0 − 0.7 = 0.887
r ON = 1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T | − |V DS |) =
1
110 µ × 2(4 − 0.887 − 0) = 1460 Ω
Repeat for V S = 2
|V T | = 0.7 + 0.4[ ]0.7 + 2.0 − 0.7 = 1.023
r ON = 1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T | − |V DS |) =
1
110 µ × 2(3 − 1.023 − 0) = 2299 Ω
Repeat for V S = 3
|V T | = 0.7 + 0.4[ ]0.7 + 3.0 − 0.7 = 1.135
r ON = 1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T | − |V DS |)
=1
110 µ × 2(2 − 1.135 − 0)
= 5253 Ω
Repeat for V S = 4
|V T | = 0.7 + 0.4[ ]0.7 + 4.0 − 0.7 = 1.233
r ON = 1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T | − |V DS |) =
1
110 µ × 2(1 − 1.233 − 0) = -19549
Ω
The negative sign means that the device is off due to the fact that V GS < V T
Thus
r ON = infinity
Repeat for V S = 5
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
64/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 4
|V T | = 0.7 + 0.4[ ]0.7 + 5.0 − 0.7 = 1.320
r ON = 1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T | − |V DS |) =
1
110 µ × 2(0 − 1.320 − 0) = -3442 Ω
The negative sign means that the device is off due to the fact that V GS < V T
Thus
r ON = infinity
Summary:
V S (volts) R (ohms)
0.0 1057
1.0 1460
2.0 22993.0 5253
4.0 infinity
5.0 infinity
Problem 4.1-3
The circuit shown in Fig. P4.1-3 illustrates a single-channel MOS resistor with a W/L of
4µm/1µm. Using Table 3.1-2 model parameters, calculate the small-signal on resistanceof the MOS transistor at various values for V S and fill in the table below. Note that the
most positive supply voltage is 5 volts.
Figure P4.1-3
V S
I = 0.0
5 Volts
The equation for threshold voltage with absolute values so that it can be applied to n-
channel or p-channel transistors without confusion.
|V T |= |V T 0 | + γ !"
#$2|φ F | + |vSB| − 2|φ F |
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
65/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 5
r ON = 1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T | − |V DS |)
For p-channel device,
|V T 0 | = 0.7
K' = 50µ
γ ! = 0.57
2|φ F | = 0.8
The table below shows the value of V GS and V SB for each value of V S
V S (volts) V GS (volts) V BS (volts)
0.0 0 5
1.0 1 4
2.0 2 3
3.0 3 2
4.0 4 1
5.0 5 0
Using V S = 5, calculate V T
|V T |= |V T 0 | + γ !" #$2|φ F | + |vSB| − 2|φ F | = 0.7 + 0.57[ ]0.8 + 0.0 − 0.8 = 0.7Calculate r on
r ON = 1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T | − |V DS |) =
1
50 µ × 4(5 − 0.7 − 0) = 1163 Ω
Repeat for V S = 4
|V T | = 0.7 + 0.57[ ]0.8 + 1.0 − 0.8 = 0.955
r ON = 1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T | − |V DS |) =
1
50 µ × 4(4 − 0.955 − 0) = 1642 Ω
Repeat for V S = 3
|V T | = 0.7 + 0.57[ ]0.8 + 2.0 − 0.8 = 1.144
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
66/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 6
r ON = 1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T | − |V DS |) =
1
50 µ × 4(3 − 1.144 − 0) = 2694 Ω
Repeat for V S = 2
|V T | = 0.7 + 0.4[ ]0.8 + 3.0 − 0.8 = 1.301
r ON = 1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T | − |V DS |) =
1
50 µ × 4(2 − 1.301 − 0) = 7145 Ω
Repeat for V S = 1
|V T | = 0.7 + 0.57[ ]0.8 + 4.0 − 0.8 = 1.439
r ON = 1∂ I D / ∂V DS = LK'W (|V GS | − |V T | − |V DS |)
= 150 µ × 4(1 − 1.439 − 0) = -11390
Ω
The negative sign means that the device is off due to the fact that V GS < V T
Thus
r ON = infinity
Repeat for V S = 0
|V T | = 0.7 + 0.57[ ]0.8 + 5.0 − 0.8 = 1.563
r ON = 1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T | − |V DS |) =
1
50 µ × 4(0 − 1.563 − 0) = 3199 Ω
The negative sign means that the device is off due to the fact that V GS < V T
Thus
r ON = infinity
Summary:
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
67/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 7
V S (volts) R (ohms)
0.0 infinity
1.0 infinity
2.0 7145
3.0 2694
4.0 1642
5.0 1163
Problem 4.1-4
The circuit shown in Fig. P4.3 illustrates a complementary MOS resistor with an n-
channel W/L of 2µm/1µm and a p-channel W/L of 4µm/1µm. Using Table 3.1-2 modelparameters, calculate the small-signal on resistance of the complementary MOS resistor
at various values for V S and fill in the table below. Note that the most positive supply
voltage is 5 volts.
Figure P4.3
V S
I = 0.0
5 Volts
Summary for n-channel device from Problem 4.1-2:
V S (volts) R (ohms)
0.0 1057
1.0 1460
2.0 2299
3.0 5253
4.0 infinity
5.0 infinity
Summary for p-channel device from Problem 4.1-3:
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
68/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 8
V S (volts) R (ohms)
0.0 infinity
1.0 infinity
2.0 7145
3.0 2694
4.0 1642
5.0 1163
Table showing both and their parallel combination:
V S (volts) R (ohms), n-channel R (ohms), p-channel R (ohms), parallel
0.0 1057 infinity 1057
1.0 1460 infinity 1460
2.0 2299 7145 1739
3.0 5253 2694 1781
4.0 infinity 1642 1642
5.0 infinity 1163 1163
Problem 4.1-5
For the circuit in Figure P4.1-5(a) assume that there are NO capacitance parasitics
associated with M1. The voltage source vin is a small-signal value whereas voltage
source V dc has a dc value of 3 volts. Design M1 to achieve the frequency response
shown in Figure P4.1-5(b).
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
69/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 9
Figure P4.4
vin
5 Volts
2 pF vout
V dc
M1
0 dB
-6 dB
-12 dB
-18 dB
-24 dB
2 0 M H z
1 0 M H z
5 M H z
2 . 5 M H z
4 0 M H z
8 0 M H z
1 6 0 M H z
vout
/vin
(a)
(b)
f(-3 dB) = 20 MHz, thus w = 40π M rad/sNote that since no dc current flows through the transistor, the dc value of the drain-source
voltage is zero.
r ON =
1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T | − |V DS |) =
L
K'W (|V GS | − |V T |)
Then
1
RC =
K'W (|V GS | − |V T |)
LC = 40
π Μ rad/s
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
70/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 10
W
L =
C × 40 π × 106
K' (|V GS | − |V T |)
Calculate VT due to the back bias.
V T = V T0 + γ % &
' (
|2φf | + |vbs| - |2φf | = 0.7 + 0.4 %
& ' (
0.7 + 3.0
- 0.7 = 1.135
W
L =
40 π × 106 × 2 × 10-12
110 × 10-6 (2 − 1.135) = 2.64
Problem 4.1-6
Using the result of Problem 4, calculate the frequency response resulting from changingthe gate voltage of M1 to 4.5 volts. Draw a Bode diagram of the resulting frequencyresponse.
r ON = 1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T | − |V DS |) =
L
K'W (|V GS | − |V T |)
Calculate VT due to the back bias (same as previous problem).
V T = V T0 + γ %
&
'
(|2φf | + |vbs|
− |2φf | = 0.7 + 0.4 %
&
'
(
0.7 + 3.0
− 0.7 = 1.135
r ON = 1
∂ I D / ∂V DS =
L
K'W (|V GS | − |V T |)
r ON = 1
110 × 10-6 × 2.64(4.5 − 3 − 1.135) == 9434 Ω
ω (-3 dB) = 1
r ON
C =
1
9.434 × 103 × 2 × 10
-12 = 53 × 106 rad/s
f (-3 dB) = 8.44 × 106 Hz
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
71/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 11
Figure P4.1-6
0 dB
-6 dB
-12 dB
-18 dB
-24 dB
2 0 M H z
1 0 M H z
5 M H z
2 . 5 M H z
4 0 M H z
8 0 M H z
1 6 0 M H z
vout
/vin
8.44 MHz
Problem 4.1-7
Consider the circuit shown in Fig. P4.1-7 Assume that the slow regime of charge
injection is valid for this circuit. Initially, the charge on C1 is zero. Calculate vOUT at
time t1 after φ1 pulse occurs. Assume that CGS0 and CGD0 are both 5 fF. C1=30 fF.
You cannot ignore body effect. L = 1.0 µm and W = 5.0 µm.
Figure P4.1-7
C1
vout
M1
2.0
φ1
t1
φ1
0 V
5 V
CHANGE PROBLEM:
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
72/508
CMOS Analog Circuit Design (2nd
Ed.) Homework Solutions: 9/21/2002 12
Use model parameters from Table 3.1-2 and 3.2-1 as required
U = 5 × 108
The equation for the slow regime is given as
V error = % )&
'* (W · CGD0 +
C channel2
C L
π U C L2 β
+ W · CGD0
C L (V S + V T − V L )
and
V S = 2.0 volts
V L = 0.0 volts
V T is calculated below
The source of the transistor is at 2.0 volts, so the threshold for the switch must be
calculated with a back-gate bias of 2.0 volts.
V T = V T0 + γ % &
' (
|2φf | + |vbs| − |2φf | = 0.7 + 0.4 %
& ' (
0.7 + 2.0
− 0.7 = 1.023
V T = 1.023
Cchannel = W × L × Cox = 5 × 10-6 × 1 × 10-6 × 24.7 × 10-4 = 12.35 × 10-15 F
V HT = V H − V S − V T = 5 − 2 − 1.023 = 1.98
Verify slow regime:
βV 2 HT
2C L =
110 × 10-6 × 3.91
2 × 30 × 10-15 = 7.17 × 109 >> 5 × 108 thus slow regime
V error = % )
&
'*
(W · CGD0 +C channel
2
C L
π U C L2 β +
W · CGD0
C L (V S + V T − V L )
V error = % )&
'* (5 × 10-6 × 220 × 10-12 + 12.35 × 10
-15
2
30 × 10-15 ×
-
8/17/2019 Solutions2CMOS CircuitDesign Allen
73/508
CMOS Analog