Santiago Celma Pueyo Concepción Aldea Chagoyen CMOS ...

ACSP · Analog Circuits and Signal Processing

Cecilia Gimeno GascaSantiago Celma PueyoConcepción Aldea Chagoyen

CMOS Continuous-Time Adaptive Equalizers for High-Speed Serial Links

Analog Circuits and Signal Processing

Series editors

Mohammed Ismail, Dublin, USAMohamad Sawan, Montreal, Canada

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Cecilia Gimeno Gasca · Santiago Celma Pueyo Concepción Aldea Chagoyen

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CMOS Continuous-Time Adaptive Equalizers for High-Speed Serial Links

Cecilia Gimeno GascaSantiago Celma Pueyo Concepción Aldea Chagoyen Faculty of Sciences, Electronics Area University of Zaragoza Zaragoza Spain

Springer Cham Heidelberg New York Dordrecht London

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ISSN 1872-082X ISSN 2197-1854 (electronic)ISBN 978-3-319-10562-8 ISBN 978-3-319-10563-5 (eBook)DOI 10.1007/978-3-319-10563-5

Library of Congress Control Number: 2014947702

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This book studies CMOS continuous-time adaptive equalizers for high-speed serial links. Continuous-time equalizers have been widely used in different data transmission applications such as short- and long-distance copper communica-tions, in printed circuit board transmissions and short-haul optical communications through plastic optical fibers (POF). The equalizer compensates the bandwidth limitation of the communication channel to reach the required transmission speed.

CMOS Continuous-Time Adaptive Equalizers for High-Speed Serial Links first explores the theoretical fundamentals of continuous-time adaptive equalizers. After this, different structures are proposed for the different blocks that consti-tute it and a complete continuous-time adaptive equalizer is designed. The main objectives are low-voltage supply, low-power consumption, and high-speed opera-tion. Experimental measurements certify the correct operation of the proposed equalization approach. Finally, a cost-effective CMOS receiver which includes the proposed continuous-time adaptive equalizer is designed for 1.25 Gb/s optical communications through 50-m length, 1-mm diameter POF.

This work has been partially supported by MICINN-FEDER (TEC2008-05455, TEC2011-23211) and FPU fellowship program from the MICINN to C. Gimeno (AP2009-1288), DGA-FSE (PI127/08), and CAI through CAI-Europe for research stays.

Zaragoza, Spain, July 2014 Cecilia GimenoSantiago Celma

Concepción Aldea

Preface

vii

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Equalization for High-Speed Serial Links . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 Transmitter Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1.2 Receiver Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.1.3 Adaptation Criteria and Related Algorithms . . . . . . . . . . . . . 121.1.4 Equalization for Short-Reach Optical Communications . . . . 17

1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221.3 Book Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2 Theoretical Study of Continuous-Time Equalizers . . . . . . . . . . . . . . . . 312.1 Basic Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312.2 Power Spectral Density of NRZ Data Encoding . . . . . . . . . . . . . . . . 332.3 Unified Model for CT Equalizers in the Frequency Domain . . . . . . . 34

2.3.1 CT Adaptive Equalizer with a Slicer . . . . . . . . . . . . . . . . . . . 382.3.2 CT Adaptive Equalizer with Spectrum-Balancing

Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432.3.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2.4 Loop Filter Selection Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3 Continuous-Time Linear Equalizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533.1 Degenerated Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543.2 Split-Path Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563.3 Comparative Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.4 Experimental Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.4.1 Layout Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

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3.4.2 Electrical Set-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713.4.3 Electrical Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4 Adaptation Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814.1 Design of the Adaptation Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.1.1 Line Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844.1.2 Loop Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844.1.3 Power Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874.1.4 Complete Continuous-Time Adaptive Equalizer . . . . . . . . . . 92

4.2 Experimental Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984.2.1 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994.2.2 Electrical Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . 994.2.3 Time-Domain Characterization . . . . . . . . . . . . . . . . . . . . . . . 101


5 Receiver Front-End for 1.25-Gb/s SI-POF . . . . . . . . . . . . . . . . . . . . . . . 1075.1 Receiver Front-End Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

5.1.1 Transimpedance Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095.1.2 Adaptive Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135.1.3 Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145.1.4 Clock and Data Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . 116

5.2 Experimental Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235.2.1 Optical Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125


6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356.1 General Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356.2 Further Research Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Appendix A: Plastic Optical Fibers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145





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Figures

Fig. 1.1 Basic communication system block diagram . . . . . . . . . . . . . . . . . 2Fig. 1.2 Concept of equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Fig. 1.3 4 tap FIR filter for transmitter pre-emphasis (in this

and the following pictures dc variable current sources are included to symbolize a control signal that depends on the different weight coefficients) . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Fig. 1.4 Block diagram of a 4 tap transmitter equalizer . . . . . . . . . . . . . . . . 6Fig. 1.5 Block diagram of de-emphasis equalizer . . . . . . . . . . . . . . . . . . . . 6Fig. 1.6 Illustration of de-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Fig. 1.7 Digital FIR equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Fig. 1.8 Analog FIR equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Fig. 1.9 Block diagram of a parallelized analog FIR equalizer . . . . . . . . . . 9Fig. 1.10 Circuit diagram of a differential passive

equalization filter [SUN05] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Fig. 1.11 Block diagram of a continuous-time split-path equalizer . . . . . . . . 11Fig. 1.12 Block diagram of a decision feedback equalizer . . . . . . . . . . . . . . 12Fig. 1.13 Eye diagrams derived from different compensations

caused by equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Fig. 1.14 Adaptive equalizer concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Fig. 1.15 Adaptive equalizer concept with a training sequence . . . . . . . . . . . 13Fig. 1.16 Frequency spectrum error criterion using a slicer . . . . . . . . . . . . . . 14Fig. 1.17 Adaptation circuit operation principle. The plotted

voltages are indicated in Fig. 1.16 . . . . . . . . . . . . . . . . . . . . . . . . . 15Fig. 1.18 Frequency spectrum error criterion using a slicer without filters . . . 15Fig. 1.19 Power spectral density: a ideal NRZ, b under-compensated

and c over-compensated. This corresponds to the particular case where f 1 and f 3 are zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Fig. 1.20 Block diagram of the spectrum-balancing technique . . . . . . . . . . . 17Fig. 1.21 Frequency response of a Mitsubishi GH SI-POF

for different fiber lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Fig. 1.22 Block diagram of an optical communication system . . . . . . . . . . . 20

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Fig. 2.1 Typical smoothed frequency response of the channel (line), the equalizer (pointed) and the frequency response of their combined action (dashed) . . . . . . . . . . . . . . . . . . . . . . . . . 33

Fig. 2.2 Ideal NRZ test pattern illustrated in a time domain, b autocorrelation of it, and c power spectrum of it . . . . . . . . . . . . . 34

Fig. 2.3 PSD of a 2N − 1 PRBS with a N = 3, b N = 4, c N = 5, and d N = 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Fig. 2.4 Normalized power spectral density of a NRZ data stream and how different filtering modifies it. The three spectrums have the same total power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Fig. 2.5 PSD of an ideal NRZ data stream and PSD of the data stream out of the channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Fig. 2.6 Line equalizer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Fig. 2.7 Conceptual scheme of the adaptive equalizers with

and without slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Fig. 2.8 NRZ PSD accumulated power . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Fig. 2.9 a Ideal pulse and b ideal pulse after low-pass filtering . . . . . . . . . . 39Fig. 2.10 a Autocorrelation and b PSD of a random signal with

transition times from 0 (red) to 100 % of the bit period (blue) . . . 40Fig. 2.11 Frequency dependence of the variation of the accumulated

power with respect to A (pointed), accumulated power for AOpt (dashed), and their product (line) for CT adaptive equalizers with a slicer and two HPFs . . . . . . . . . . . . . . . 42

Fig. 2.12 Frequency dependence of the variation of the accumulated power with respect to A (pointed), accumulated power for AOpt (dashed), and its product (line) for CT adaptive equalizers with a slicer and two BPFs . . . . . . . . . 42

Fig. 2.13 Some possible combination of filters for CT adaptive equalizer with spectrum-balancing technique . . . . . . . . . . . . . . . . . 43

Fig. 2.14 PSD of an ideal and an ideally equalized NRZ data stream . . . . . . 44Fig. 2.15 Dependency of fco on A for spectrum-balancing technique

with LPF and HPF. fco = 0.28 corresponds to A = 23 whereas for AOpt = 9 a value of fco = 0.22 is obtained . . . . . . . . . 45

Fig. 2.16 Variation of the PSD of the equalized signal with respect to A at AOpt. The maximum variation is obtained for f just above 0.2 · RB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Fig. 2.17 Equalizer input signal for two different POF lengths: L = 10 m from 0 to 0.1 µs and L = 40 m from 0.1 to 0.2 µs . . . . . 48

Fig. 2.18 Adaptive equalizer output for length changes: L↑ = +30 m and L↓ = −30 m . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Fig. 2.19 Example of control signal for length changes: L↑ = +30 m and L↓ = −30 m . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Fig. 3.1 Degenerated differential pair-based equalizer with a fixed elements, and b tunable elements . . . . . . . . . . . . . . . . 54

Figures xi

Fig. 3.2 Frequency responses of degenerated differential pair for different values of the control voltage a VC and b VC2 . . . . . . . 55

Fig. 3.3 Scheme of the differentiator implemented with transconductors . . . 56Fig. 3.4 Scheme of the proposed APF with cross-configuration . . . . . . . . . 57Fig. 3.5 Scheme of the proposed SPEQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Fig. 3.6 Transistor level topology of the SPEQ . . . . . . . . . . . . . . . . . . . . . . 59Fig. 3.7 Frequency responses of the proposed SPEQ

for different values of the voltage a VC, and b VCG . . . . . . . . . . . . . 60Fig. 3.8 Layout of the proposed equalizer SPEQ (6,050 µm2) . . . . . . . . . . . 61Fig. 3.9 Output frequency responses of the different equalizers

using a 50-m POF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Fig. 3.10 CMRR versus frequency of the different equalizers . . . . . . . . . . . . 63Fig. 3.11 Variation of the response of the equalizer with the input

common-mode dc voltage (VCM) for a degenerated differential pair-based equalizer, and b proposed equalizer . . . . . . 64

Fig. 3.12 Variation of the response of the equalizer with the supply voltage (VDD) for a degenerated differential pair-based equalizer, and b SPEQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Fig. 3.13 Variation of the response of the equalizer with the temperature (T) for a degenerated differential pair-based equalizer, and b SPEQ . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Fig. 3.14 Bandwidth of equalized 50-m POF versus a dc input voltage, b supply voltage, and c temperature . . . . . . . . . . . . 65

Fig. 3.15 Monte Carlo simulations for a bandwidth, and b gain. The parameter mu is the mean value, sd is the standard deviation, and N is the total number of samples . . . . . . . . . . . . . . . 66

Fig. 3.16 Monte Carlo simulations for a input noise, and b dc output voltage. The parameter mu is the mean value, sd is the standard deviation, and N is the total number of samples . . . . . 67

Fig. 3.17 Eye diagram degraded by inter-symbol interference . . . . . . . . . . . 68Fig. 3.18 Eye diagrams before equalization with a NRZ

PRBS 231-1 of data rate a 1.25 Gb/s, and b 2 Gb/s . . . . . . . . . . . . . 68Fig. 3.19 Eye diagrams after equalization with a NRZ PRBS

231-1 for 1.25 and 2 Gb/s for a the degenerated differential pair-based equalizer, and b the SPEQ . . . . . . . . . . . . . 69

Fig. 3.20 Block diagram of the fabricated line equalizer . . . . . . . . . . . . . . . . 69Fig. 3.21 Output driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Fig. 3.22 Bare die with wire bonding to the PCB . . . . . . . . . . . . . . . . . . . . . 71Fig. 3.23 Electrical test set-up that makes possible the

compensation for the off-chip parasitic elements during measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Fig. 3.24 POF electrical emulator on PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Fig. 3.25 Schematics of the complete electrical test

set-up for the integrated prototype . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figuresxii

Fig. 3.26 Electrical test bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Fig. 3.27 a Layout and b microphotograph of the

chip for testing the SPEQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Fig. 3.28 Microphotograph of the active area

of the SPEQ chip (0.012 mm2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Fig. 3.29 PCB for electrical measurements of the SPEQ chip . . . . . . . . . . . . 75Fig. 3.30 Measured S21 parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Fig. 3.31 Measured a S11, and b S22 parameters . . . . . . . . . . . . . . . . . . . . . . . 76Fig. 3.32 Measured S21 for different values of a VC, and b VCG . . . . . . . . . . . 76Fig. 3.33 Measured S21 for different values of a VDD, and b VCM . . . . . . . . . 76Fig. 3.34 Measured bandwidth improvement for 10- and 50-m POF . . . . . . 77Fig. 4.1 Block diagram of the proposed adaptive equalizer . . . . . . . . . . . . . 82Fig. 4.2 Block diagram of the a LPF and b APF . . . . . . . . . . . . . . . . . . . . . 85Fig. 4.3 Transistor level topology of the a LPF and b APF . . . . . . . . . . . . . 86Fig. 4.4 Frequency responses of the loop filers for

the LPF/LPF configuration: a differential, b common mode . . . . . 87Fig. 4.5 Frequency responses of the loop filers for

the LPF/APF configuration: a differential, b common mode . . . . . 87Fig. 4.6 Conceptual scheme of the adaptive equalizers:

a conventional and b squarer-based adaptation loop . . . . . . . . . . . 88Fig. 4.7 Schematics of the flipped-voltage follower

differential pair (FVFDP) based power comparator . . . . . . . . . . . . 89Fig. 4.8 Level-shifter amplifier schematics . . . . . . . . . . . . . . . . . . . . . . . . . 90Fig. 4.9 Simulated eye diagrams for bitstream at 1.25 Gb/s

of a −13.9 dBm and b −9.5 dBm . . . . . . . . . . . . . . . . . . . . . . . . . 91Fig. 4.10 Time response of the power comparator . . . . . . . . . . . . . . . . . . . . . 92Fig. 4.11 Output voltage versus input power difference

for different frequencies of a NRZ bitstream . . . . . . . . . . . . . . . . . 92Fig. 4.12 Example of the transient response at the different

building blocks of the adaptive equalizer implemented with a LPF/APF combination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Fig. 4.13 Eye diagrams after 50-m POF equalization with a 1.25 Gb/s NRZ PRBS 231-1 for the adaptation loop including LPF/LPF and LPF/APF for a typical behavior, b slow n and slow p (ss), c fast n and fast p (ff), d slow n and fast p (snfp), and e fast n and slow p (fnsp) . . . . . . . . 94

Fig. 4.14 Eye diagrams after 10-m POF equalization with a 1.25 Gb/s NRZ PRBS 231-1 for the adaptation loop including LPF/LPF and LPF/APF for a typical behavior, b slow n and slow p (ss), c fast n and fast p (ff), d slow n and fast p (snfp), and e fast n and slow p (fnsp) . . . . . . . . . . . . . 95

Fig. 4.15 Eye diagrams with a 1.25 Gb/s NRZ PRBS 231-1 for the adaptation loop including LPF/LPF and LPF/APF for a −40 ºC, b 120 ºC after 50-m POF equalization . . . . . . . . . . . 96

Figures xiii

Fig. 4.16 Eye diagrams with a 1.25 Gb/s NRZ PRBS 231-1 for the adaptation loop including LPF/LPF and LPF/APF for a −40 ºC, b 120 ºC after 10-m POF equalization . . . . . . . . . . . 97

Fig. 4.17 Eye diagrams with a 1.25 Gb/s NRZ PRBS 231-1 for the LPF/LPF and LPF/APF configuration for a supply voltage of a 1.1 V, b 0.9 V after 50-m POF equalization . . . 97

Fig. 4.18 Eye diagrams with a 1.25 Gb/s NRZ PRBS 231-1 for the LPF/LPF and LPF/APF configuration for a supply voltage of a 1.1 V, b 0.9 V after 10-m POF equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Fig. 4.19 Block diagram of the fabricated adaptive equalizer . . . . . . . . . . . . 99Fig. 4.20 a Layout and b microphotograph of the chip

for testing the adaptive equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . 100Fig. 4.21 Microphotograph of the active area of the chip (0.015 mm2) . . . . . 100Fig. 4.22 Printed circuit board (PCB) of the adaptive equalizer chip . . . . . . 101Fig. 4.23 Measured bandwidth improvement for 10- and 50-m POF . . . . . . 101Fig. 4.24 Block diagram of the time-domain measurement set-up . . . . . . . . 102Fig. 4.25 Eye diagrams for 1.25 Gb/s NRZ PRBS 231-1:

a unequalized and b equalized through 50-m POF; c unequalized and d equalized through 10-m POF . . . . . . . . . . . . . 102

Fig. 5.1 Optical receiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Fig. 5.2 Simple I-V conversion by using a resistor RF:

a circuit and b equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . 109Fig. 5.3 Basic structure of a shunt feedback TIA:

a circuit and b equivalent noise model . . . . . . . . . . . . . . . . . . . . . . 110Fig. 5.4 Block diagram of the whole transimpedance

amplifier and the AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111Fig. 5.5 Transistor level topology of the transimpedance amplifier . . . . . . . 112Fig. 5.6 Dependence of the input impedance on the frequency . . . . . . . . . . 113Fig. 5.7 Continuous-time adaptive equalizer . . . . . . . . . . . . . . . . . . . . . . . . 113Fig. 5.8 Response of the equalizer adaptive loop. Generated

error voltage VC for 10-m (0–1.5 and 3–4.5 µs) and 50-m (1.5–3 µs) POF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Fig. 5.9 Core of a limiting amplifier: a without downscaling, b with downscaling and c conventional passively loaded differential pair implementing each amplifier . . . . . . . . . . . 115

Fig. 5.10 Half-circuit of the balanced limiting amplifier . . . . . . . . . . . . . . . . 116Fig. 5.11 Detailed differential CDR block diagram . . . . . . . . . . . . . . . . . . . . 118Fig. 5.12 VCO delay stage schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Fig. 5.13 VCO control voltage circuit schematics . . . . . . . . . . . . . . . . . . . . . 120Fig. 5.14 Phase detector output characteristics: a linear,

and b bang-bang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Fig. 5.15 Multi-level bang-bang phase detector block diagram . . . . . . . . . . . 122Fig. 5.16 Output of the proposed multi-level BBPD as a function

of the phase difference between its inputs . . . . . . . . . . . . . . . . . . . 123

Figuresxiv

Fig. 5.17 CML DFF schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Fig. 5.18 CML XOR gate schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124Fig. 5.19 Block diagram of the fabricated POF receiver . . . . . . . . . . . . . . . . 124Fig. 5.20 Output driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125Fig. 5.21 Microphotograph of the chip for testing the POF receiver . . . . . . . 125Fig. 5.22 Layout of the active area. Its size is about 800 µm × 300 µm . . . . 125Fig. 5.23 Experimental optical test set-up for the integrated

prototype a block diagram, and b photograph of the test bench . . . 126Fig. 5.24 Microphotograph of the PD-receiver combination . . . . . . . . . . . . . 127Fig. 5.25 PCB of the receiver front-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127Fig. 5.26 a Jitter transfer plot and b jitter peaking for the proposed CDR . . . 128Fig. 5.27 a Eye diagram of recovered clock signal,

and b recovered clock jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Fig. 5.28 Eye diagrams for 1.25-Gb/s NRZ PRBS 231-1 at the input

for a 10-m POF, b 30-m POF, c 50-m POF and d at the output of the equalization/data recovery . . . . . . . . . . . . . . . . . . . . . 129

Fig. 5.29 Measured BER versus input optical power for 10- and 50-m POF for 1.25 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . 130

Fig. A.1 Step-index plastic optical fiber . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142Fig. A.2 Attenuation along a typical PMMA plastic optical fiber . . . . . . . . 142Fig. A.3 Frequency response of a Mitsubishi GH

SI-POF for different fiber lengths . . . . . . . . . . . . . . . . . . . . . . . . . . 142Fig. A.4 Equivalent circuit model that simulates the frequency

response of the fiber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143Fig. A.5 Comparison between the experimental and simulated

results for 10-m and 50-m fiber lengths . . . . . . . . . . . . . . . . . . . . . 143

xv

Tables

Table 2.1 Comparison between theoretical results and published papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 2.2 Comparative analysis between the different filters configurations. The rise time TR, fall time TF and constant time of the used integrator TINT are compared . . . . . . 49

Table 3.1 Performance summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Table 3.2 Corner analysis for equalization of 50-m SI-POF . . . . . . . . . . . . . 67Table 3.3 Summary and comparison with other

continuous-time equalizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Table 4.1 Performance comparison with the power

comparator based on the conventional differential pair . . . . . . . . . 92Table 4.2 Corner analysis of the two proposed adaptive equalizers . . . . . . . . 96Table 4.3 Jitter and ISI summary for different temperatures

and supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Table 4.4 Summary and comparison with other works . . . . . . . . . . . . . . . . . 104Table 5.1 Summary of CDR performances and comparison

with other works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Table 5.2 Performance comparison of receivers

(does not include the CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130Table A.1 Summary of values of main parameters

for the model of the POF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

xvii

Symbols

A Gain AC Common mode gain AD Differential gain AOpt Optimum gain for equalization C Capacitance clk Clock signalCgs, Cgd Gate-source and gate-drain capacitance Cint Integrating capacitor Coi Output node capacitance of the transistor i COX Oxide capacitance per unit of area CPD Photodiode capacitance Dclk Clock output data Din Input data D(x) X-bit digital control word f Frequency fco Cut-off frequency gm MOS transistor transconductance defined as δID/δVGS

gmb MOS transistor bulk-transconductance defined as δID/δVBS

GND Ground H(s) Transfer function IB Bias current ID MOS drain current IDS Drain-source current IN,IN

2 Input referred noise IO Output current Iout Output current IS Input current j Complex k Scaling factor between transistors K Boltzmann’s constant (1.38 × 10−23 J/K)

Symbolsxviii

L Transistor length Mi Transistor i p Pole Pacc Accumulated power q Electron charge (1.602 × 10−19 C) Q Quality factor RB Bit Rate RF Shunt-feedback or floating load resistance RL Load resistance r0 MOS transistor output resistance RO Output resistance Rvar Variable resistance Sin Power spectral density at the input Sout Power spectral density at the output sP Pole frequency Sxy S-parameters sZ Zero frequency T Temperature TB Bit period TF Fall time Ti Transconductor i TINT Constant time of the integrator TR Rise time ttrans Transition time UI Unit interval Vb Bias voltage VC Control voltage VCG Gain control voltage VCM Common-mode voltage VCT TIA control voltage VDD Supply voltage VDsat Drain saturation voltage of a MOS transistor Vfc Frequency control voltage VGS, VDS, VBS Gate-source, drain-source and bulk-source MOS transistor Vin Input voltage VO Output voltage VREF Reference voltage VS Equalizer input voltage VTH Threshold voltage of a MOS transistor W Transistor width z Zero ε Dielectric constant ε0 Vacuum dielectric constant (8.8542 10−12 F/m) ϕ Phase of a clock

Symbols xix

ω Angular frequency ω0 Characteristic frequency µN Electron mobility λ Channel-length modulation factor of a MOS transistor

xxi

Acronyms

ADC Analog-to-Digital ConverterADSL Asymmetric Digital Subscriber LineAGC Automatic Gain ControlAPF All-Pass FilterBPD Binary Phase DetectorBBPD Bang-Bang Phase DetectorBER Bit Error RateBFD Binary Phase DetectorBJT Bipolar Junction TransistorBPF Band-Pass FilterBW BandwidthCDR Clock and Data Recovery CircuitCML Current-Mode LogicCMOS Complementary Metal-Oxide-SemiconductorCMRR Common Mode Rejection RatioCP Charge-PumpCT Continuous-TimeDAC Digital to Analog ConverterDCA Digital Communications AnalyzerDEMUX DemultiplexerDFE Decision Feedback EqualizerDFF D-Flip-FlopsDUT Device Under TestEMI Electro Magnetic InterferenceESD Electrostatic DischargeFFE Feed-Forward EqualizerFIR Finite Impulse ResponseFPGA Field Programmable Gate ArrayFSG Fluorosilicate glassGI-POF Graded-Index Plastic Optical FiberGOF Glass Optical FiberHAN Home Area Networks

Acronymsxxii

HPF High-Pass FilterIC Integrated CircuitI-V Current-to-VoltageIIR Infinite Impulse ResponseISDN Integrated Services Digital NetworkISI Intersymbol InterferenceLA Limiting AmplifierLED Light-Emitting DiodeLMS Least Mean SquaresLPF Low-Pass FilterMIM Metal-Insulator-MetalMDAC Multi Digital to Analog ConverterMOST Media Oriented Systems TransportMSE Mean-Square ErrorMUX MultiplexerNRZ Non Return-to-ZeroPAM Pulse Amplitude ModulationPAN Personal Area NetworksPCB Printed Circuit BoardPD Photo DiodePLL Phased-Locked LoopPOF Plastic Optical FiberPRBS Pseudo Random Bit SequencePSD Power Spectral DensityPVT Process Voltage TemperatureRCLED Resonant-Cavity Light Emitting DiodesRMS Root Mean SquareRX ReceiverRZ Return-to-ZeroS&H Sample and Hold AmplifierSI-POF Step-Index Plastic Optical FiberSNR Signal-to-Noise RatioSOLT Short, Open, Load and ThroughSTP Shielded Twisted PairTIA TransImpedance AmplifierTX TransmitterUTP Unshielded Twisted PairVCO Voltage-Controlled OscillatorVCSEL Vertical-Cavity Surface-Emitting LaserVGA Variable Gain AmplifierWDM Wavelength Division MultiplexZF Zero Forcing Algorithm

1

In today’s world, there is an increasing demand to transmit information from one place to another. Whether it is for long-haul links such as cable or digital tel-evision networks, or for short-distance connections such as backplane routing or chip-to-chip interconnects, fast and robust systems are required to correctly drive all the transmitted data.

Because of their low cost and high bandwidth, high-speed CMOS serial link transceivers are widely used for backplane and optical communication networks.

In most systems, the communication channel has become the major bottleneck for the overall bandwidth, and hence the overall performance. Therefore, there is a great research interest in reducing the gap between the on-chip and off-chip band-widths. Equalization is a well-known technique used to overcome non-idealities introduced by the bandwidth-limiting channel.

In this introductory chapter, we will do a review of the state of the art of equal-izers for wireline applications, describing why they are necessary, their types, and their main applications. We avoid the study of equalization for wireless communi-cations, as they present specific equalization problems caused in the multipath fad-ing wireless channel that comes from the mobility of communicators to accomplish the goal of providing all the information asked for any possible location [CHI06, JAL12]. After that, we focus our attention on equalization for short-reach optical communications because that is the application our equalizers are designed for.

1.1 Equalization for High-Speed Serial Links

Recent advances in integrated circuit (IC) fabrication technology coupled with innovative circuit and architectural techniques led to the design of high-perfor-mance digital systems. These systems require efficient communication between multiple chips for proper functioning of the whole system. However, the off-chip

Chapter 1Introduction

© Springer International Publishing Switzerland 2015 C. Gimeno Gasca et al., CMOS Continuous-Time Adaptive Equalizers for High-Speed Serial Links, Analog Circuits and Signal Processing, DOI 10.1007/978-3-319-10563-5_1

2 1 Introduction

bandwidth (BW) scales at a much lower rate when comparing with the on-chip bandwidth, making the off-chip communication link the major bottleneck for the overall performance [LIU04]. Therefore, it is no longer sufficient to solely increase the speed of the ICs to achieve higher data rates.

A representative description of a communication link between two chips is shown in Fig. 1.1. It always involves three basic parts: the transmitter, the channel, and the receiver. Dedicated circuits designed for high-speed operation are used as transmitters and receivers of the data. The medium of transmission is called the channel, which, in the ideal wireline case, is a wire representing a short circuit.

However, the nonideal channel characteristics, e.g., channel bandwidth and crosstalk noise, make them behave as lossy transmission lines severely degrad-ing the quality of the received signal and causing error in data recovery. This is produced since in the practical communication system, the channel behaves like a low-pass filter; therefore, different frequency components of the transmitted sig-nal suffer different attenuation and phase distortion when propagating through the channel. The channel BW limitation decisively contributes to the corruption of the original signal, producing intersymbol interference (ISI): one single bit, which ide-ally should only occupy one unit interval, spreads over several unit intervals, and the adjacent bits will be interfered such that an error may occur.

According to the Shannon-Hartley theorem, the maximum data rate at which error-free signal can be transmitted through a bandwidth-limited channel in the presence of noise can be improved by widening the bandwidth of the transmission channel or improving the signal-to-noise ratio (SNR) of the signal. The general formula for the Shannon-Hartley theorem is expressed as

where RB is the data rate measured in bits per second (b/s), BW is the bandwidth of the signal measured in Hz, and SNR is the signal-to-noise ratio [LEE12].

Utilizing multilevel signaling scheme such as duo binary and 4-PAM (pulse amplitude modulation) instead of binary signaling provides spectral efficiencies higher than simple non return-to-zero (NRZ) modulation and can help in reducing the BW requirements of the system [MIN12]. On the other hand, the BW of the system can be improved with relatively low-cost electronics. Equalization is a cir-cuit technique targeting at increasing the data BW of the transmission channel to meet the high data rate requirement. The working principle of an equalizer circuit is aimed to flatten the frequency response of the impaired channel up to at least the Nyquist frequency.1 Conventional methods such as replacing the channel with

(1.1)RB = BW · log2 (1+ SNR)

1 The Nyquist frequency is the bandwidth of a sampled signal, and is equal to half the sampling frequency of that signal.

Fig. 1.1 Basic communication system block diagram

3

low-loss material, incorporating repeater in the channel, and reducing the channel length are no longer effective in solving high-speed communication issues.

Equalizers reduce ISI and can increase the achievable data rates tremendously. The conceptual diagram illustrating the way of performing equalization is shown in Fig. 1.2. In summary, equalization is used to improve the received signal quality for a correct clock and data recovery, so that the system achieves lower bit error rate for the goal of error-free data communications.

A classical equalization application was, and still is, sending fax through the telephone line; the connection tones we hear at the beginning of sending fax are for the purpose of equalization. The path connecting two phone terminals is differ-ent depending on the phone number; even with the same phone number, the switch network might connect them differently each time depending on the traffic. Thus, in this case, training sequences known to both the transmitter and the receiver are transmitted; the channel characteristics can be computed by comparing the known training sequence with the actual received signal [LIU04].

Other typical examples are Ethernet communications with transmission rate of several hundred Mb/s [BAB98], where over 100 m of transmission distance causes extreme channel loss, and the magnetic read/write channels for hard disk drives [ABB94, BUR00] with speed around 500 Mb/s, where adjacent track causes severe ISI at high storage densities. Equalization has also been widely used in communication applications such as voice-band modems, wireless [LIN03], digital subscriber lines, and integrated services digital network (ISDN) [INA88]. Recently, equalization has also been used in USB 3.0 redrivers that are used to equalize and reshape the distorted signals so that the following host or device can recover the data without failing the bit error rate specifications [LIU13].

With the increasing demand for higher-speed processing, the data rate in chip-to-chip communications for back-plane, front-plane, personal, and mainframe computer has been pushed to several Gb/s range and even beyond 10 Gb/s range. At this frequency range, the low-cost printed circuit board (PCB) trace introduces significant attenuation to the signal; equalization has become mandatory to ensure reasonable transmission distance [HAR06].

Equalization has been widely used to compensate the attenuation of coax-ial cable both in long- and short-distance communication links. For all metal-lic media, including PCB traces and metallic cables like unshielded twisted pair

Fig. 1.2 Concept of equalization


4 1 Introduction

(UTP) cables, shielded twisted pair (STP) cables, and coaxial cables, the channel losses at higher frequencies are mainly caused by skin effect, length of the cable, and dielectric loss [JOH03, LIU05]. This produces a limitation in the BW, which causes ISI, making equalization necessary to increase the rates of transmission over band-limited channels.

However, copper cable systems experience many problems. Therefore, optical communication is outperforming the copper-based communication links as they are cheaper, safer and immune to electromagnetic interference (EMI).

Equalization has also been used in long-distance communications through opti-cal-fiber channels, e.g., in modems and ADSL (asymmetric digital subscriber line), to compensate the dispersion produced by the fiber, principally modal and chromatic dispersion in multimode fibers [ZIE08], as well as other impairments [SHT03].

In medium-distance applications with silica fiber, equalization is not usu-ally necessary: the BW of the channel is several times higher than the transmis-sion frequency. However, in short-distance communications, such as local area networks (LAN) between computers, the economic viability requires the use of low-cost technologies for both microelectronic and optical components. Standard CMOS technologies should be used to implement the electronic part, and polym-ethylmethacrylate or “plastic” optical fibers (POF) are a cost-effective choice for the optical channel. Therefore, equalization is absolutely essential in this kind of applications to achieve high BW at competitive prices when comparing with trans-mission using copper wire [BAN08, DON10].

Equalization is not exclusively used for POF applications. For silica fibers, it is usually not necessary because the BW of the fiber and the photodiode (PD) is much higher than the frequency limitation of the electronics circuits. However, for trans-mission rates higher than 40 Gb/s, the necessity of using equalization arises [LIA08].

Recently, in short-distance and high-volume communication systems, such as: home area networks (HAN), personal area networks (PAN), backplane interconnect, and optical storage systems; optical receivers with monolithically integrated photo-detectors have drawn tremendous research interest. In contrast to the conventional multi-die solutions, which are composed of photo-detector implemented in more expensive GaAs or InP-InGaAs technology, the fully integrated optical receiver is much more cost-effective (a really appreciative characteristics as the communication channels are not shared between many users). Besides, the issues of parasitic capac-itance introduced by ESD (electrostatic discharge) pads and leading inductance for multi-die integration can be avoided. The main disadvantage of CMOS integrated PD is that the transmission rate is very low. In fact, in the design of integrated front-ends, this response limits the BW of the whole optical receiver. In the literature, there are some alternatives to improve the BW of the PDs; however, most of them use nonstandard CMOS technologies, which contradict the cost aspect previously mentioned. Therefore, equalization is a good alternative to compensate the limited intrinsic frequency response of the integrated PDs [HER06, RAD05, TAV06].

There are several techniques to implement the equalizer circuit. As the charac-teristics of the communication channels are very different depending on the type of channel (air, vacuum, seawater, twisted pair telephone lines, coaxial cables,

5

waveguides, printed circuit board (PCB) traces, fiber-optic cables, and magnetic read/write channels), choosing the right equalization strategy will depend on the particular application and channel characteristics. We now describe different equalization strategies and their trade-offs.

1.1.1 Transmitter Equalization

Depending on the localization of the equalizer, we can differentiate between trans-mitter equalization and receiver equalization.

Transmitter equalization can be divided into pre-emphasis [DAL97, FAR99, MAR03], if it pre-shapes the transmitted data increasing the high-frequency compo-nents, or de-emphasis, if it reduces the power of low-frequency components [FIE97, FOL02, LEE03]. Pre-emphasis can cause electromagnetic interference (EMI) and more severe crosstalk [LIU04], but de-emphasis reduces the emitted power.

Finite impulse response (FIR) filters are generally used for transmitter pre-emphasis. A simplified approach is to use two differential amplifiers, the first one controlled by the original code and the second by emphasis code (produced by inverting the original code and delaying one symbol period).

Figure 1.3 shows the block diagram of 4-tap sparse FIR filter for pre-emphasis equalizer with 4-PAM scheme [STO03]. Four 2-bit digital to analog converters (DAC) serve as the multiplier for FIR filter. Output currents of four multi digital to analog converters (MDACs) are summed up at their output node and converted to voltage.

When parallel data are not present, the tap delay line3 can be simply realized with digital delay unit without the need for high-speed analog to digital converter (ADC) or analog tap delay line [FAR99]. Figure 1.4 shows a block diagram of transmitter equalizer realized as 4-tap transversal FIR filter.

3 A tap delay line is a discrete element which allows a signal to be delayed by a number of sam-ples. It extracts a signal output from somewhere within the delay line, optionally scales it, and usually sums with other taps for forming an output signal.

Fig. 1.3 4 tap FIR filter for transmitter pre-emphasis2

2 In this and the following pictures dc variable current sources are included to symbolize a control signal that depends on the different weight coefficients.


6 1 Introduction

As mentioned earlier, transmitter equalizer can also be a de-emphasis fil-ter, which reduces the power of low-frequency component. The simplest way is increasing the signal amplitude at each transition edge and reducing the signal amplitude when there is no transition. In [FIE97], the de-emphasis equalizer uses the inverted signal of previous bit as emphasis signal. During “0” to “1” transition edge, signal amplitude is increased; in “1” to “0” transition edge, signal amplitude is further increased in the negative direction. In other periods when there is no transition, the emphasis signal is opposite to the current bit and the signal ampli-tude is reduced. Block diagram of de-emphasis equalizer is shown in Fig. 1.5. This de-emphasis is actually a 2-tap FIR filter with a high-pass frequency response. Figure 1.6 illustrates the effect of de-emphasis.

The implementation of transmitter equalization using FIR filter is relatively easier than that at the receiver side, because the parallel data bus naturally sup-plies the data input for FIR filter. However, there are several limitations in trans-mitter equalization. First, due to the signal attenuation, transmitter pre-emphasis cannot improve SNR. Second, it is essential to maximize the transmitted sig-nal swings to incorporate large amount of equalization, thus resulting in exces-sive crosstalk [ZER01]. Third, high-resolution DACs are required to implement pre-emphasis filters to equalizer channels containing large number of ISI terms [ZER03]. Finally, despite transmit pre-emphasis, there is a considerable residual ISI, which results in reduction of both timing and voltage margins, particularly at higher data rates.

Fig. 1.4 Block diagram of a 4 tap transmitter equalizer

Fig. 1.5 Block diagram of de-emphasis equalizer

7

In addition, since pre-emphasis is at the transmitter side, no channel char-acteristics information is present; so, it is simpler to implement an adaptive equalizer in the receiver because the error signal needed for adaptation is read-ily available. Although there are some authors who propose adaptive transmitter equalization [GOO11, KIM07], information needs to be sent from the receiver for dynamic or fine-tuned equalization, with special encoding packet or side-band signaling.

Alternatively, in some applications, although the definitive equalization is made on the receiver side, a fixed amount of pre-emphasis without consideration of the channel characteristics is chosen to improve the received signal quality to a certain degree [DON12, HAR06, MAS09]. Both transmitter and receiver equalizations present some problems: peak power constraint in the transmitter equalization, and several nonidealities such as limited bandwidth), noise enhancement, ampli-fier nonlinearity, in the receiver equalization, as it will be shown later. By using both transmitter and receiver equalizations together, some of the problems can be circumvented.

1.1.2 Receiver Equalization

Receiver equalization offers a method to mitigate ISI without any peak power con-straint. The loss in the channel is suppressed by boosting the high-frequency signal spectrum rather than attenuating the low-frequency content. Because of the inherent gain in the system, this method often results in larger noise margins.

We will present now different receiver equalizer architectures.

Fig. 1.6 Illustration of de-emphasis


8 1 Introduction

Discrete Time Digital FIR Equalizer

A finite impulse response filter (FIR)4 can be used on the receiver side to perform equalization [RYL01, STA00]. Here, the input to the receiver filter is the output of the channel, which is analog in nature. An analog-to-digital conversion is required to interface the channel output to the filter. Figure 1.7 shows the block diagram of a digital FIR equalizer.

Although digital circuits are more robust than analog circuits, there are two major bottlenecks in the practical implementation of this kind of equalizers. First, the critical path shown in Fig. 1.7 limits the maximum operation frequency to only few hundred megahertz. Well-known techniques such as transposition [AZA98] and parallelism [THO95] can be used to shorten the critical path. Nevertheless, these transposed filters are still speed-limited to less than a gigabit data rate. Second, the practical usefulness of this equalizer is severely limited by the high-speed ADC requirement at the front-end. Even though it is possible to design digital FIR equalizers with high-speed ADCs [CHU09, YAN01], they are hard to realize with CMOS technology at Gb/s data rate and they add large power and area overhead. Also, the front-end ADC can add unwanted latency in adaptive loops such as the timing recovery loop [KIM05]. Owing to these constraints, digital FIR equalizers are employed only in medium-rate interfaces. The price paid for high-speed operation using digital FIR is excessive power consumption.

Discrete Time Analog FIR Equalizer

An analog FIR equalizer [LEE01, RAO12, VAH06] obviates the need for a high-speed ADC and is therefore attractive for high-speed operation with potentially lower power consumption. Figure 1.8 shows a conceptual block diagram of this kind of equalizer. The high-speed ADC is replaced by a simpler sample and hold amplifier (S&H). As opposed to a digital delay in the case of digital FIR, an analog delay chain is required to implement the analog FIR.

Even though digital equalizers have more robustness and are less sensi-tive to environment parameters, analog equalizers commonly have higher SNR for a given number of taps because they offer the advantage of processing the

4 A finite impulse response (FIR) filter are distinguished by having an impulse response which become exactly zero past a certain time, thus being of finite duration. This is in contrast to a infinite impulse response (IIR) filter in which the impulse response does not become exactly zero past a certain point, but continues indefinitely.

Fig. 1.7 Digital FIR equalizer

9

unquantized signal. However, the FIR analog equalizer suffers from many imple-mentation difficulties. First, the settling time of the S&H block limits the overall operating speed. Moreover, each S&H cell introduces distortion and attenuation to the delayed signal. All distortion and attenuation due to nonlinearity, clock feed through, and limited bandwidth of S&H cell will be accumulated along the line [KIR97]. Second, the sampled signal experiences considerable attenuation due to the limited BW of the delay elements in the delay chain. Each unit must settle down in one symbol period, which requires high-frequency clock and wide-band-width S&H. Moreover, this limited bandwidth-induced error accumulates along the delay chain, thus limiting this technique to FIR filters with few taps. Finally, the precise generation of analog delay consumes excessive power at high data rates, thus invalidating the main benefit of an analog FIR equalizer.

To avoid error accumulation, parallel sampling units can be used permitting very high data rates [JAU04, MEK10, RAO12]. The conceptual block diagram of a parallelized analog FIR equalizer is shown in Fig. 1.9. Extra redundant S&H units have been added to relieve timing constraint on settling time of S&H. Phases Φi represent the different phases of a clock. This method lowers speed requirement of S&H at the cost of additional delay and area.

Employing parallelism and time-interleaving, this architecture is suitable for equalizing multi-gigabit serial links, at the expense of increased power and area incurred due to massive parallelism.

Continuous-Time Equalizer

The discrete-time receiver equalizers discussed thus far need sampling front-end to perform equalization. This requirement results in two main drawbacks. First, the sampling clock-jitter reduces the effectiveness of the equalization. Second, in a truly serial communication system, the clock is recovered from the incoming data. However, due to the sampling front-end, the clock-recovery loop needs to operate on raw channel output resulting in an excessive jitter in the recovered clock [BUC04].

Fig. 1.8 Analog FIR equalizer

Fig. 1.9 Block diagram of a parallelized analog FIR equalizer


10 1 Introduction

Therefore, practical serial links employing discrete-time FIR equalizers are limited to source synchronous interfaces [JAU04] containing a separate clock channel, such as high-speed interfaces between microchips, including DDR, SDRAM, etc.

Continuous-time circuits that can provide high-frequency boost are a very attractive alternative. A continuous-time equalizer is a simple one-tap continuous-time circuit with high-frequency gain boosting transfer function that effectively flattens the channel response. A continuous-time equalizer can exhibit a good trade-off for low-power high-speed applications, requiring less complexity and smaller area than discrete-time or purely digital approaches.

The simplest continuous-time solution is to use a passive receiver equalizer. Some authors [SUN05, SUN11] use this alternative because fixed passive equal-ization is easy to implement, it can work in a wide bit rate range, and has low power consumption. Figure 1.10 shows an example of a passive equalizer.

However, the implementation highly depends on the coding scheme, it is sensitive to the process variation, and has a low SNR level (equalization is per-formed by attenuating low-frequency signal spectrum) and narrow compensation range. Moreover, in most cases, inductors have to be used to avoid large imped-ance discontinuity at the channel and equalizer interface, making it less suitable for on-chip integration, as they require a big chip area to be implemented and are not available in every technology. Therefore, passive equalizers have limited use in high-speed serial links; they are preferred when the received signal has large amplitude and the receiver sensitivity is high.

It is desirable to have a greater gain to maximize the benefit from receiver-side equalization. Therefore, equalizers using active circuit elements rather than pas-sive components are required.

Active filters with a desired frequency response can be designed using standard filter design techniques [SCH01]. Such standard filters are typically implemented either with operational amplifiers in negative feedback or with Gm-C split-path amplifiers. Traditional filters using operational amplifiers in negative feedback provide precise gain and low nonlinearity [BAB98]. However, the negative feed-back greatly degrades the maximum operating frequency preventing the amplifier to work in the gigahertz range. Phase mismatch between feedback loop and input

Fig. 1.10 Circuit diagram of a differential passive equalization filter [SUN05]

11

signal also limit using a feedback loop amplifier in high-frequency range. Gm-C split-path amplifiers-based equalizers [CHE07, KUD03] divide the signal in two paths. One path comprises a high-pass filter or peak-response filter to amplify the high-frequency component. Another path is an all-pass filter or a low-pass filter to match the time delay of the first path. Weighted sum of the two paths is equivalent to a variant gain high-pass filter, whose gain factor can be varied by controlling the weight of those two paths. Figure 1.11 shows the block diagram of these equalizers.

Finally, continuous-time equalizers can also be implemented with FIR filters. Continuous-time transversal filters [LIN06], as opposed to discrete-time filters, can be implemented if one can design high-bandwidth analog-delay elements. Even though this method has a potential high-speed advantage, applying active continuous-time tap delay line in higher-frequency range is highly limited by the bandwidth of CMOS circuit. Therefore, it is not practical at medium to high data rates due to the requirement of very long well-controlled on-chip transmission lines or large number of area-consuming inductors [WU03].

Decision Feedback Equalizer

The gain-peaking transfer function of the continuous-time equalizer amplifies the high-frequency noise potentially degrading the noise margin. The same occurs with all the previously presented equalizers as they are linear equalizers. The prob-lem of noise enhancement can be completely eliminated by using decision feed-back equalizer (DFE) [GOU10, LE02, SOH03, VAH06]. Figure 1.12 shows the block diagram of a DFE. This filter is nonlinear with the nonlinearity specifically designed not to amplify noise.

This is possible by utilizing the previous decisions to estimate and cancel the ISI caused by previous symbols on the current symbol to be detected. The feed-back filter estimates the ISI based on previous decisions, and therefore, can only cancel ISI caused by previous symbols. Since the ISI cancellation is based on pre-vious decisions, without high-frequency boost, it is inherently immune to noise enhancement. Unfortunately, this approach cannot address the ISI from symbols yet to be decoded. The effectiveness of ISI cancellation is based on the assumption that all previous decisions are correct and therefore bit errors can exacerbate ISI instead of cancelling it. This problem is referred as error propagation. However, in the case of serial links with required bit error rate BER <10−12, error propagation does not degrade the performance [BAL03].

DFEs are the best choice for systems in which the noise limits the amount of equalization that can be done. However, because of the added complexity and the

Fig. 1.11 Block diagram of a continuous-time split-path equalizer


12 1 Introduction

associated timing difficulties, the simpler feedforward5 equalizer should be used when the noise is not prohibitive.

To remove the remaining ISI from symbols yet to be decoded, commonly a DFE in conjunction with a feedforward equalizer (FFE) is used. There are several examples of the combined use of DFE and FFE in literature with all the possible variations of FFE [GOU10, LE02, VAH06]. Sometimes, the FFE is implemented in the transceiver and the DFE at the receiver [BUL12], but more frequently both equalizers are implemented as a combined one at the receiver side [AGR12, THA13]. One widely used alternative consists of using a continuous-time FFE and a digital DFE [DOI13, PAR13, PRO11]. This justifies the necessity of research in the area of continuous-time equalizers as they can also be used in more sophisti-cated equalization schemes.

1.1.3 Adaptation Criteria and Related Algorithms

In a practical transmission system, the exact characteristics of the channel are not known a priori and they can vary significantly. The temperature, the properties of the material, the length, or other kind of effect such as connectors, bends, etc., are all variables and can cause the channel to change its attenuation and bandwidth substantially [HER06]. Therefore, it is mandatory to design an adaptive equalizer because otherwise it would result in an under- or over-compensation, as shown in Fig. 1.13, increasing the BER of the whole communication system.

Figure 1.14 shows a conceptual block diagram illustrating the operation of an adaptive equalizer. In this generic block diagram, the line equalizer could be of

5 We use here the term feedforward equalization to refer to the kind of equalization that corrects the received waveform with information about the waveform itself and not information about the logical decisions made on the waveform; in contrast, decision feedback equalization uses previ-ous decisions to estimate and cancel the ISI.

Fig. 1.12 Block diagram of a decision feedback equalizer

13

any type. The adaptive engine automatically adjusts the coefficients by measuring the equalizer performance so as to improve the performance on an average. In this way, an error signal related to the quality of the data is generated to tune the trans-fer function of the equalization filter.

There are several algorithms that can be used for adapting the equalizer. The most popular one for compact hardware implementation is mean-square error (MSE) calculated between the recovered signal and the training data in the time domain at sampling points [HAR06]. The main implementations are the least mean squares (LMS) [KRA08, LEE94], the zero forcing (ZF) [ABE05], or their variations. The LMS algorithm optimizes the filter coefficients based on mini-mizing the mean-squared error. It has a simple computational complexity but a slow convergence [ATE13]. The ZF algorithm brings down the ISI to zero in a free noise case. However, when the channel is noisy, the ZF equalizer will amplify the noise greatly [ATE13]. Figure 1.15 shows the adaptive equalizer concept with training sequences.

A second method, known as waveform monitor [ANA05, ELL00, SHO99], obtains the error signal by sampling the equalizer output waveform and then ana-lyzing its characteristics in the time domain. For example, the value of equalized

Fig. 1.13 Eye diagrams derived from different compensations caused by equalizer

Fig. 1.14 Adaptive equalizer concept

Fig. 1.15 Adaptive equalizer concept with a training sequence


14 1 Introduction

signal sampled at the peak or in the transition band can be used to decide whether it is over- or under-equalized [SHO99]. Another example is to monitor the eye-opening of the equalized signal [ANA05, ELL00]. However, when ISI is very severe, the received signal has closed eyes and it becomes impossible to compare the quality of two received signals.

These criteria and algorithms need a clock with accurate sampling phase to obtain time-domain information required for error calculation. However, clock recovery loop needs well-equalized data to converge. These two loops are not independent and may both fail [SHO99]. So, a third method to generate error sig-nal is using statistical spectrum information. This method has several advantages over the previous methods: (a) using statistical information as adaptation criteria relaxes the speed requirement of the tuning circuit since it is time-average result; (b) using continuous-time analog circuit to compare signals in frequency domain other than time domain, sampling clock with accurate phase is not needed; and (c) the desired spectrum is a statistical information and it is not necessary to have a training sequence [LIU04].

The typical method of frequency spectrum error criterion uses an adaptation loop to compare the different frequency spectra at the input and output of a slicer6 because the slicer output signal is supposed to have an ideal spectrum. It basically compares the slope at the input and output of the slicer. By assuming that the slicer output signal has sharp edges, the adaptation loop tries to modify the zero of the equalizer to maximize the slicer input signal slope. For that, different combina-tions of filters are used followed by a rectifier or a squarer circuit [BAB98, BAK96, CHO04, FAY08]. Figure 1.16 shows the block diagram of this adaptation loop and Fig. 1.17 shows the signal at different points of the loop for three possi-ble cases: under-equalization, optimal equalization, and over-equalization. At under-equalization, the control signal VC increases because of the faster edge slope at the output of the slicer than at the input. On the contrary, VC decreases at over-equalization. Only when the equalization is optimal, VC remains constant.

6 Also called comparator or binarizer.

Fig. 1.16 Frequency spectrum error criterion using a slicer

15

One variation of this strategy is using an adaptation loop like the one shown in Fig. 1.18. It compares the difference between the transition times of the equalizer filter output and the slicer output by means of two slope detectors and an integra-tor [ZHA05]. The main difference from the previously mentioned adaptation loop is that the slope detector in this case has been implemented with only one stage avoiding the use of filters to select the frequency range to compare and taking the whole spectrum. Although the authors claim that it is a new loop architecture, we will show in Chap. 2 that they all can be integrated in an unified model.

Unfortunately, the slicer usually has high slew-rate and is power-hungry [BAB98]. Therefore, the use of the slicer would limit the maximum speed [LEE06].

Fig. 1.17 Adaptation circuit operation principle. The plotted voltages are indicated in Fig. 1.16

Fig. 1.18 Frequency spectrum error criterion using a slicer without filters


http://dx.doi.org/10.1007/978-3-319-10563-5_2

16 1 Introduction

Although the frequency spectrum of the signal depends on the type of modu-lation, the signal can be essentially treated as a random sequence of bits with a known power spectrum. Therefore, some proposed approaches remove the slicer and use the spectrum-balancing technique as the decision mechanism [CHE10, LEE06, MAX03, SUN05]. It is a self-comparison method of data spectrum char-acteristics that can obviate the need for a slicer. In ideal random binary data, a nor-malized spectrum can be expressed as

where TB is the bit period of the data stream [CHE10].As the ratio of the signal power at any two frequency ranges is constant [CHE10],

and can be expressed as (1.2), the adaptation loop can examine the power spectrum at the output of the equalizer, determine whether the data stream is under- or over-compensated, as shown in Fig. 1.19, and adjust the boost accordingly.

Thus, an error signal can be obtained to control the equalizer using the block dia-gram shown in Fig. 1.20. This adaptation scheme reduces the circuit complexity and power dissipation by avoiding the need for more complex analog blocks such as slicers [CHE10, JOO10, LEE09, LIU09].

Different filter combinations have been used to implement the power compari-son: [LEE06] uses a low pass filter (LPF) and a high pass filter (HPF) to compare the low-frequency part and the high-frequency part of the spectrum; for sensing much power, an HPF can be replaced with an all pass filter7 (APF) [AZN12, CHE10, SUN05]; some authors use two band pass filters (BPF) [MAX03], but

(1.2)S(f ) = TB · sinc2(π · f · TB) = TB ·

(

sin (π · f · TB)

π · f · TB

)2

(1.3)P2

P1

=

∫ f4f3S(f )df

∫ f2f1S(f )df

=

∫ f4f3sinc2(f )df

∫ f2f1sinc2(f )df

= c

7 All pass filters pass all frequencies equally in gain, but changes the phase relationship between various frequencies.

Fig. 1.19 Power spectral density: a ideal NRZ, b under-compensated and c over-compensated. This corresponds to the particular case where f 1 and f 3 are zero

17

they usually consume much more power; finally, two LPFs can also be used [GIM13]. In all the cases, the used filters are simple first order RC or Gm-C filters. Its frequency response is usually fixed in an ad hoc manner after trial-and-error procedure.

1.1.4 Equalization for Short-Reach Optical Communications

Nowadays, there exists an increasing demand for fast and reliable communication systems for consumer short-reach applications, capable of achieving high data rates and providing good service quality. Designers face the challenge of fulfilling these requirements with low-cost, low-power systems that, moreover, should be easy to install and maintain. Optical links are preferred to implement these high-speed serial communication systems because they achieve a wider bandwidth, which can be above 100 times larger than that of high-speed microwave transmission [SEN09].

In short-haul communications, standard 1-mm step-index plastic optical fib-ers (SI-POF) are better than coaxial cables, because they are much lighter in weight, more robust against bends, shock, and vibration, and more compact in size. Therefore, POF cable is easier to install, hide, and adjust in a building. As an example, a POF cable can be terminated with simple office knives by an inexperi-enced personnel. This method is known as cut-and-plug installation [DON10]. In addition, POF systems provide better immunity to noisy EMI, better security, and a lower fabrication cost in high volumes due to their all-plastic nature [AZN10]. Moreover, the use of visible non-collimated light makes it intrinsically eye-safe and easy to troubleshoot, as the signal can be seen by the naked eye. Traditionally, glass optical fiber (GOF) channels have been used when high data rates were required but their high installation and maintenance costs make them unsuitable for domestic users. In short-haul communications, SI-POF also offers certain advantages over GOF: (1) simpler and less-expensive components; (2) ease in han-dling and connecting (POF diameters are 1 mm when comparing with 8–100 µm for glass [POL10]); (3) the possibility of resonant-cavity light emitting diodes (RCLED) or vertical-cavity surface-emitting laser-based (VCSEL) light emitters, and (4) mainly overall lower cost.

Fig. 1.20 Block diagram of the spectrum-balancing technique


18 1 Introduction

The 1-mm core SI-POF has already been a popular data communication medium for several years and is being used commercially in industry and home networking at speeds of up to 100 Mb/s over 50-m length and in automotive envi-ronments, where they replace copper wires to communicate information between the radio, navigation system, multimedia player, and mobile phone system, up to 150 Mb/s with the media oriented systems transport (MOST) standard [KIB04]. In fact, the goal set by some operators is to outperform the copper-based and all-radio-based solutions in the future [KOO11].

Nowadays, the extreme simplicity of POF has come at the expense of lower transmission capacity with respect to GOF. The main drawback of SI-POF is the bandwidth-length product of approximately 45 MHz · 100 m due to mainly strong chromatic and mode dispersion [ZIE08]. This small BW, quite unsuitable for giga-bit communications, limits the maximum non-return-to-zero (NRZ) data rate that can be properly transmitted through SI-POF, since, when the data rate is much higher than the BW of the channel, ISI appears and affects the BER of the whole communication system.

As consumers demand more multimedia services requiring higher transmission speed, more effort is put into the development of high-speed POF solutions. For example, the project funded by the EU Seventh Framework Program, POF-Plus [POF13], is dedicated to the development of a practical POF solution for gigabit Ethernet to deliver a high-speed digital signal to the residential user at a lower cost than that of other alternatives.

Different strategies can be used for achieving gigabit transmission over POF links. For example, more expensive graded index POF (GI-POF), which reduces the physical POF penalties [BAN08, DON10], or more elaborated modulation for-mats [ZEO11] that exploit the bandwidth better than the simple NRZ modulation and maximize the channel capacity. As we are looking for a simpler and cheaper communication system, it is preferable to use equalization of the simple NRZ-modulated signals instead. The equalizer should provide the inverse frequency response of the channel to achieve a flat response of the channel-equalizer combi-nation over the transmission spectrum.

In a practical transmission system, the exact characteristics of the channel are not known a priori, and they can vary significantly. Temperature, material proper-ties, fiber length, and other kinds of effects (connectors, bends, etc.) can cause the bandwidth of the fiber to change substantially [HER06]. For example, Fig. 1.21 shows the dependence of the frequency response of a Mitsubishi GH SI-POF on its length [MAS09]. Therefore, it is highly desirable to design an adaptive equal-izer to compensate for the variation of the characteristics of the channel with all these effects. Otherwise, it would result in over- or under-compensation, increas-ing the BER.

Figure 1.22 shows an example of an optical communication system. It consists of the transmitter, the transmission channel, that it would be the POF now, and the receiver.

The transmitter is made-up as a serializer, a driver, and the light emitter. Several synchronous digital signals are multiplexed into a transmitted digital signal by the

19

serializer. It consists of a multiplexer (MUX) and a frequency synthesizer, based on a phased-locked loop (PLL). Non-idealities caused by the MUX are absorbed by the retimer. The laser driver must provide the proper modulated current to the light emitter and usually incorporates power control. Although a laser is com-monly used because of its higher output power and more spectral purity, for low-cost solutions, a light-emitting diode (LED) can be adopted as the light emitter.

The receiver consists of a photodiode (PD), an analog front-end, and a deserial-izer. The PD converts the transmitted optical power into a current, which can be electronically processed by the analog front-end to provide a signal with sufficient quality. For POF systems, the cost-effective viability requires the use of standard CMOS technologies and PIN PD on the receiver side. Because a typical POF has a core diameter close to 1 mm, a large area PD is preferred for high-efficiency light coupling but supposes a huge parasitic capacitance. Therefore, to neutralize the effect of this parasitic capacitance over the frequency response, a transimpedance amplifier (TIA) with very low input impedance has to be included at the input of the receiver front-end. The TIA converts the photocurrent that comes from the PD into a voltage, and, later, the post-amplifier boosts such a voltage swing to logical levels, adequate for subsequent digital circuitry. The post-amplifier may consist of a simple cascade amplifier chain, denominated limiting amplifier, or present addi-tional circuitry to control the gain, called automatic gain control (AGC) amplifier. Finally, the deserializer must target two main functions: clock and data recovery and demultiplexing (DEMUX). First, from the received signal, it must recover the associated clock signal. Then, the received signal is converted to a digital signal by deciding between the two possible states indicated by the recovered clock. Finally, the digital signal is demultiplexed.

As previously explained, in short-reach optical communication circuits through POF, it is necessary to include an equalizer to compensate the limited frequency response of the POF. Moreover, this equalizer should be adaptive to track the variation in the response of the fiber. As aforementioned, there are many kinds of equalizers; so, which one is recommendable for short-reach optical communica-tions through SI-POF?

Some authors [NES10a] propose to use pre-equalization (through an FIR fil-ter) of the signal in the transmitted side, as shown in Fig. 1.22 (pre-equalizer).

Fig. 1.21 Frequency response of a Mitsubishi GH SI-POF for different fiber lengths


20 1 Introduction

However, if the frequency response changes, as a result of different lengths of the POF or bends in the fiber, etc., the result will be too much or too little compensa-tion; therefore, the BER will increase. As it is difficult to communicate informa-tion about the channel from the receiver back to the transmitter equalizer in real time, pre-equalization is combined with an adaptive receiver equalizer. Moreover, pre-equalization lowers the modulation depth of the emitted light; this reduces the effective power per pulse when comparing with rectangular pulses without peak-ing. This is at the expense of the system power budget. As SI-POFs have high

Fig. 1.22 Block diagram of an optical communication system

21

losses per meter (fiber losses are about 0.14 dB/m at 650 nm), we cannot afford to reduce the received power. See Appendix A for more information about the POF.

There are also several authors who use DFE equalization (always with a previ-ous FFE equalizer). For example, [GAU10] uses a mixed-signal equalizer com-posed of a DFE with previous feedforward correction; this adaptive equalizer is placed at the output of the postamplifier. In these cases, the DFE often restores and retimes the binary signal performing in this way the CDR (clock and data recov-ery) function together with the equalization. But the DFE (FFE + DFE) can also be placed after the CDR; for example, [BRE07] implements an FFE with 15 sym-bol-spaced taps with reference tap at the 8th tap and a DFE with 9 symbol-spaced forward and 7 backward taps; [NES10b] implements an adaptive DFE in combina-tion with an FIR FFE in a field programmable gate array (FPGA).

In reference to the adaptive equalizer, most DFE equalizers for POF applica-tions use LMS or MMS algorithms [BRE07, GAU10, NES10b]; although there are some authors who use a training sequence [BRE07] to optimize the coeffi-cients, it is more common to implement a “blind equalizer” so that neither training sequence nor “a priori” knowledge of the channel is needed [GAU10, NES10b].

It is well known that decision feedback equalization, including a forward filter, is an effective strategy for a channel with severe ISI; [KAS82] shows its effective-ness for a long length of multimode fiber, where the impulse response becomes “Gaussian.” However, for short lengths (up to 100 m), the impulse response tends to an exponential. In this regime, the advantage in performance gain between a DFE and a linear one is much less, since the latter´s noise enhancement is less, and it may not justify the more complicated hardware required. In [BAT92] the validity of the exponential impulse approximation and the effectiveness of a sim-ple linear equalization strategy are illustrated. This can also be shown in the fre-quency domain. As shown in Fig. 1.21, the roll-off slope in SI-POF is 12 dB/dec approximately; the equalizer peaking required is not very important, and the noise is not greatly amplified. Therefore, although they have been used in POF appli-cations, the reduction in noise obtained with DFE does not justify its increase of complexity, area, and power consumption.

Analog continuous-time equalizers are a good alternative, as they present a good trade-off for low-power high-speed applications, requiring less complexity and smaller area. Several works proposed in literature [ATE13, AZN10, DON10] validate this strategy. They are usually placed at the analog front-end after the transimpedance amplifier but they can also be placed after the post-amplifier. In this book, we are going to work with analog continuous-time equalizers placed between the TIA and the post-amplifier as they will need less input dynamic range, which will reduce the circuit complexity and power consumption.

In the adaptation loop, we prefer a blind to a trained equalization technique since the former does not require any “bootstrap” protocol between the transmit-ter and the receiver. Therefore, to continue with the low-power, low-area require-ments, we chose the spectrum-balancing technique as the decision mechanism as they avoid the use of more complex blocks such as slicers.


22 1 Introduction

1.2 Objectives

It has been seen that equalization circuits are an essential block for several high-speed data transmission applications such as optical communication networks for short-haul through POF links. Because the role of an equalizer circuit is compen-sation of the limited bandwidth of a channel and/or PD, the specifications that an equalizer has to fulfill strongly depend on the application for which it is intended.

The equalizer that will be designed in this book is intended for the receiver of a serial short-haul low-cost optical communication link through a 50-m length POF channel. Simple continuous-time equalizers are preferred because their operation is independent of the clock and data recovery circuit (CDR) and it is suitable for low-power high-speed applications.

The technology in which the equalizer will be designed is a cost-effective 0.18-µm CMOS process: UMC L180 MM/RF 1.8 V/3.3 V 1P6M technology. It is a CMOS process based on general P-Sub structure with 1 layer of poly, 6 lay-ers of aluminum metal, and fluorosilicate glass (FSG) low-k dielectrics. Moreover, the MM/RF process also includes several optional layers, which are defined and decided by customer´s application designs.

As we pretend that the proposed design will be compatible with most mod-ern nano CMOS technologies, a supply voltage of 1 V has been chosen as a test bench for all the circuits proposed in the book. This has been done because as the technologies downscale, the transition frequency of the transistors increases, the supply voltage decreases but the transistor threshold voltages do not decrease pro-portionally to the supply voltage. Therefore, with the downscale of the technology, the provided dynamic range of the devices will decrease. The 1-V circuit design in a standard 1.8-V 0.18-µm CMOS technology supposes a real challenge.

Overall, the main aspects developed throughout this book are the following:

• First, theoretical fundamentals of the continuous-time adaptive equalization will be studied, analyzing the equalizer circuit as a closed-loop system using math-ematical models for its building blocks. Also, different topologies of adaptation loops will be theoretically analyzed.

• The most important block of the adaptive equalizer, the line equalizer, will be carefully designed. A new structure will be proposed, designed, and characterized.

• To prove and get better understanding of their operation, both Spectre simula-tions using Cadence and experimental measurements will be carried out. The main results will be compared with the most widely used line equalizer, the degenerated pair-based equalizer.

• The adaptation loop will also be designed, using the spectrum-balancing tech-nique. Special attention will be paid to the different blocks that compose the loop: filters and error comparator. Basic building blocks will be studied and new architectures will be proposed for each of them.

• To test the functionality of the adaptive equalizer, simulation and experimental measurements will be carried out.

23

• To properly test the functionality of the proposed equalizers for low-cost, short-haul, high-speed applications, a low-cost CMOS receiver, which includes the proposed adaptive equalizer, will be presented. It will be designed for 1.25 Gb/s transmission through 50-m length, 1-mm diameter POF. Special attention will be paid to the transimpedance amplifier because its design is critical to obtain high sensitivity and high bandwidth in conjunction with the large-area PD.

1.3 Book Organization

This book is divided into six chapters, of which the first one is the introduction and the last one presents the general conclusions of the work. In all other chap-ters, a section is reserved at the end for conclusions drawn for that chapter and the bibliography employed. To facilitate the reading of the book, contents, figures and tables index, and the list of symbols and abbreviations employed are offered at the beginning. Finally, an appendix is added.

The introductory chapter provides an introduction to equalization circuits and their importance in high-speed serial links. The different equalization archi-tectures and adaptation loops and the main applications where equalization is highly desirable are described. Special attention is paid to equalization for short-reach optical communication as this is going to be the application the work is focused on.

The second chapter covers the theoretical fundamentals of continuous-time adaptive equalization. First, the equalization basic theory is analyzed focusing on the line equalizer transfer function. Second, the power spectrum characteristics of transferred data will be analyzed, focusing on the NRZ data stream. Next, an uni-fied analysis of continuous-time adaptive equalizers will be presented, which will lead to a design criteria for the adaptation loop. After this analysis, a functional simulation of continuous-time adaptive equalizers will be presented to try to deter-mine which filters are preferred in the adaptation loop, and finally some conclu-sions of the chapter will be drawn.

The core of this book is offered in Chaps. 3–5. The design and verification of the blocks that form the adaptive equalizer (line equalizer and adaptation loop) are presented along with the introduction of this adaptive equalizer in a complete opti-cal receiver for short-reach optical communications through SI-POF.

Chapter 3 is centered on the line equalizer block. First, a new topology is pre-sented and compared with the most widely used analog continuous-time equalizer, the degenerated differential pair. Its operation is then verified by means of experi-mental measurements.

Chapter 4 presents the adaptive equalizer. First, the main blocks that constitute it are presented and two possible filter choices are compared. The operation of the best alternative is verified by means of experimental measurements.

1.2 Objectives

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24 1 Introduction

Chapter 5 presents a complete prototype of an optical receiver for short-reach applications, including building blocks designed in previous chapters. Experimental measurements validate the suitability of the proposed front-end.

Finally, the main conclusions of the work will be summarized in Chap. 6, along with a proposal for future research directions.

At the end of this book, an appendix presents the main characteristics of plastic optical fibers and the model that has been used for simulate its behavior.

References

[ABB94] W.L. Abbott, H.C. Nguyen, B.N. Kuo, K.M. Ovens, Y. Wong, J. Casasanta, A dig-ital chip with adaptive equalizer for PRML detection in hard-disk drives, in IEEE International Solid-State Circuits Conference: Digest of Technical Papers, Feb 1994, pp. 284–285

[ABE05] S.S. Abeysekera, Y. Ye, Zero based blind equalizer implementation using zero forcing, MMSE and decision feedback concepts, in Proceedings of Fifth International Conference on Information, Communications and Signal Processing, Feb 2005, pp. 96–100

[AGR12] A. Agrawal, J.F. Bulzacchelli, T.O. Dickson, Y. Liu, J.A. Tierno, D.J. Friedman, A 19-Gb/s serial link receiver with both 4-Tap FFE and 5-Tap DFE functions in 45-nm SOI CMOS. IEEE J. Solid-State Circuits 47(12), 3220–3231 (2012)

[ANA05] B. Analui, A. Rylyakov, R.S.M. Meghelli, A. Hajimiri, A 10-Gb/s two-dimensional eye-opening monitor in 0.13-µm standard CMOS. IEEE J. Solid-State Circuits 40(12), 2689–2699 (2005)

[ATE13] M. Atef, H. Zimmermann, Optical Communication over Plastic Optical Fibers (Springer, Berlin, 2013)

[AZA98] K. Azadet, C. Nicole, Low-power equalizer architectures for high speed modems. IEEE Commun. Mag. 118–126, Oct 1998

[AZN10] F. Aznar, S. Celma, B. Calvo, A 0.18-µm CMOS 1.25-Gbps front-end receiver for low-cost short reach optical communications, in Proceedings of the European Solid-State Circuits Conference (ESSCIRC10), Sept 2010, pp. 554–557

[AZN12] F. Aznar, C. Sánchez-Azqueta, S. Celma, B. Calvo, Gigabit receiver over 1-mm SI-POF for home area networks. J. Lightwave Technol. 30(16), 2668–2674 (2012)

[BAB98] J.N. Babanezhad, A 3.3 V analog adaptive line-equalizer for fast ethernet data com-munication, in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), May 1998, pp. 343–346

[BAK96] A.J. Baker, An adaptive cable equalizer for serial digital video rates to 400 Mb/s, in IEEE International Solid-State Circuits Conference (ISSCC), Feb 1996, pp. 174–175

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31

In this chapter, the principles of continuous-time adaptive equalization will be explored. First, basic theory of continuous-time equalization will be analyzed, focus-ing on its transfer function and how it should compensate the response of the channel. Second, the power spectrum characteristics of the transferred data will be analyzed, focusing on the non-return-to-zero (NRZ) data encoding and pseudo random bit sequence (PRBS), which is the typical signal used to test serial communication pro-totypes. Next, a thorough and unified analysis of continuous-time adaptive equalizers that will lead to a set of design criteria to select the proper bandwidth of the filters used in the adaptation loop will be presented. It has into account the characteristics of the communications system such as the data rate, channel bandwidth and the specific line equalizer used. After this analysis, a functional simulation of continuous-time adaptive equalizers will be presented to determine which filters are preferred in the adaptation loop. Finally, some conclusions of the chapter will be drawn.

2.1 Basic Theory

The effect of the channel on the signal can be divided into two categories. On the one hand, the signal is corrupted with noise, which results in decreased signal-to-noise ratio (SNR) and in timing jitter; these two effects are compensated at the clock and data recovery circuit (CDR) [SAN11]. On the other hand, the limited channel bandwidth causes the transitions of the data stream to lose sharpness due to the attenuation experienced by high frequency components. This also increases the intersymbol interference (ISI), thereby reducing the opening of the eye dia-gram and increasing the bit error rate (BER): these softer transitions take longer to complete, which causes the value of each bit of information to be affected by its neighbors [HOL06]. As explained in the previous chapter, equalization is a tech-nique which is widely used to reduce ISI.

Chapter 2Theoretical Study of Continuous-Time Equalizers


32 2 Theoretical Study of Continuous-Time Equalizers

The relationship between the Laplace transforms of the received data R(s) and the transmitted data T(s) can be described by the following equation

ISI is contained in HCh(s), which describes how a signal is affected by the chan-nel. The ideal equalizer comes from the inverse of the transfer function, so it receives the signal back just as it was transmitted (except for random noise):

Consider that the channel can be modeled as a linear time-invariant system with a frequency response with a dominant pole pCh. Its approximate frequency response is

Where all the rest of the frequency dependency is included in ACh(s).To overcome the extreme frequency limitations caused by the channel, the

equalizer has to boost the frequency components of the incoming signal which are just above its BW; in this way, an equalizer produces an effective extension of the receiver bandwidth beyond the one inherent to the channel. So the transfer func-tion of the equalizer must not only have at least one zero placed close to the chan-nel pole to neutralize its effect, but also at least one pole in order to be feasible.

The transfer function of the equalizer HEq(s) is given by

where zEq and pEq are the zero and the dominant pole, respectively, of the line equalizer. So, the net effect of the channel and the equalizer can be written as

Optimal equalizationhappens when the zero of the line equalizer cancels the chan-nel pole (zEq = pCh). This way

The line equalizer main pole gives the BW of the whole channel-equalizer combi-nation in the dominant pole approach. For this reason, it must be higher than the

(2.1)R(s) = HCh(s) · T(s)

(2.2)H−1

Ch (s) · HCh(s) · T(s) = H−1

Ch (s) · R(s) = T(s)

(2.3)HCh(s) = ACh(s) ·

1(

1+s

pCh

)

(2.4)HEq(s) = AEq(s) ·

1+s

zEq(

1+s

pEq

)

(2.5)HT (s) = ACh(s) ·1

(

1+s

pCh

) · AEq(s) ·

(

1+s

zEq

)

(

1+s

pEq

)

(2.6)HT (s) = ACh(s) · AEq(s) ·

1(

1+s

pEq

)

33

channel pole and large enough for the system to operate correctly at the intended bit rate. Figure 2.1 shows the effect of equalization.

2.2 Power Spectral Density of NRZ Data Encoding

NRZ signaling is widely used for data transmission in digital communication sys-tems. In NRZ signaling, each binary bit is assigned a unique time slot of duration, referred to as the bit period (TB), and therefore the bit rate (RB) of the signal (num-ber of pulses transmitted in one second) is RB = 1/TB. The signal is either high (representing a one) or low (representing a zero) over the entire bit period.

For a random NRZ data stream, each bit in the sequence has an equal prob-ability (50 %) of being a one or a zero, regardless of the state of the preceding bits. It is therefore possible to have large sequences of consecutive identical digits. Long sequences of identical digits produce a very low frequency content which requires a good low bandwidth limit making designing high-speed systems more complicated. Moreover, because of the slow signal transition density, the ac cou-pling, offset cancellation and clock recovery can create operation problems as they are sensitive to low densities transmission.

A PRBS is used as a general-purpose test pattern in NRZ applications. The PRBS is typically denoted as a 2N − 1 PRBS, where N indicates the shift register length used to create the pattern. Each 2N − 1 PRBS contains every possible com-bination of N number of bits (except one).

Each NRZ test pattern has an associated power spectral density (PSD). Two methods exist for computing the PSD: (a) squaring the magnitude of the Fourier transform of the pattern; or (b) computing the Fourier transform of the pattern autocorrelation function [GOO85]. The first method is generally simpler for sig-nals that can be mathematically written in a finite, closed form, such as sinusoidal signals. The second method is used for more complicated signals, such as long sequences of NRZ data (like test patterns) or random bit stream.

It can be argued that the autocorrelation of an ideal NRZ random data stream with a bit period equal to TB is non-zero only when the bits superimpose each other due to the random nature of the signal so that it resembles a triangular

Fig. 2.1 Typical smoothed frequency response of the channel (line), the equalizer (pointed) and the frequency response of their combined action (dashed)

2.1 Basic Theory


function extending from −TB to −TB [HAY01]. Its Fourier transform is a sinc2 function. Figure 2.2 illustrates this.

So, the PSD, S(f ), of an ideal NRZ random data stream with period TB is

A signal as random as possible must be generated for test purposes. However, soft-ware and hardware sequence generators are based on recurrence rules, so the gener-ated signal is not strictly random. The PRBS spectrum is the combination of the ideal NRZ spectrum and a delta train with a period equal to N · TB. The delta train trans-form is also a delta train, but the period is equal to RB/(2

N− 1), and therefore, the

sinc2 function is now restricted to certain frequencies. Figure 2.3 shows the PSD of

a PRBS with different pattern lengths. Thus, the PRBS signal behaves like a random signal due to the lack of correlation within the pattern if its length is adequately high.

Finally, as mentioned, the channel behaves like a low-pass filter (LPF) filter-ing the signal and modifying the spectrum; moreover, if the equalizer is wrongly tuned, it can over-boost the signal, acting as a high-pass filter (HPF) for the PSD of the NRZ signal. Therefore, it can be illustrative to show how LPF or HPF affects the spectrum of an ideal NRZ signal. Figure 2.4 shows this effect.

2.3 Unified Model for CT Equalizers in the Frequency Domain

The frequency response of a typical communication channel is a complex function of its length, the frequency of the transmitted signal and other material properties of the channel [HOO04]. This function depends greatly on the specific channel; however, for a theoretical analysis, it is sufficient to describe the channel by a first-order LPF [BEY08, HOO04, YOO06]. We suppose that the normalized transfer function of the channel HCh(s) is given by

(2.7)S(f ) = TB · sinc2(π · f · TB) = TB ·

(

sin (π · f · TB)

π · f · TB

)2

(2.8)HCh(s) =1

1+s

pCh

Fig. 2.2 Ideal NRZ test pattern illustrated in a time domain, b autocorrelation of it, and c power spectrum of it

35

In the specific application of the work, the BW of the SI-POF channel ranges from about 100 MHz for 50-m length to roughly 400 MHz for 10-m length. Figure 2.5 shows the power spectrum of the NRZ data stream after passing through the chan-nel along with the power spectrum of an ideal NRZ data stream. Furthermore, in this book we are working with split-path continuous-time equalizers. The model for a split-path equalizer is given in Fig. 2.6, where the all-pass filter has been sub-stituted by a shortcut to simplify the calculations. The high-pass filter has a pole at pEq and a boosting gain A. Its normalized transfer function HEq(s) is given by

Fig. 2.3 PSD of a 2N − 1 PRBS with a N = 3, b N = 4, c N = 5, and d N = 6

Fig. 2.4 Normalized power spectral density of a NRZ data stream and how different filtering modifies it. The three spectrums have the same total power



And the combined frequency response of the channel and equalizer can be written as

To obtain optimal equalization the zero of the line equalizer should compensate the channel pole. Looking back at (2.8) and (2.9), the optimal boosting gain is equal to

When optimal equalization has been achieved, (2.9) can be written as

Finally, the combined frequency response of the channel and equalizer for optimal equalization can be written as

(2.9)HEq(s) =

1+ s ·1+ A · pEq

pEq

1+s

pEq

(2.10)HT (s) = HCh(s) · HEq(s) =1

1+s

pCh

·

1+ s ·1+ A · pEq

pEq

1+s

pEq

(2.11)AOpt =pEq − pCh

pEq · pCh

(2.12)HEq(s) =

1+s

pCh

1+s

pEq

=pEq · s+ pEq · pCh

pCh · s+ pEq · pCh

(2.13)HT (s)|AOpt =

1

1+s

pEq

Fig. 2.5 PSD of an ideal NRZ data stream and PSD of the data stream out of the channel

Fig. 2.6 Line equalizer block diagram

37

HT (s)|AOpt depends only on the position of the main equalizer pole, which is a nat-ural consequence of the fact that optimal equalization has been achieved.Moreover, the equalizer is required to be adaptive to compensate the variations of the channel characteristics, i.e., changes of the position of its pole. As explained in the previous chapter, two main architectures have been used for the design of the adaptation loop in continuous-time adaptive equalizers: architectures which use a slicer and architectures based on the spectrum-balancing technique. Figure 2.7 shows the adaptation loop block diagram including both alternatives. Both architectures compare the signal at the output of the equalizer with an ideal one (that comes from the output of the slicer or the ideal spectrum is known in advance). This is achieved by means of two filters and an error comparator which can be implemented in many different ways, such as by using rectifiers, or squar-ers. It is important to mention here, that the filters used to select the spectrum range are simple first order filters implemented with an RC circuit or as a simple Gm-C filter.

Typically, the design of the control loop of an adaptive equalizer using a slicer is carried out in the time domain; in contrast, adaptive equalizers based on the spectrum-balancing technique are analyzed in the frequency domain. We are going to show how, in both cases, a unified description in the frequency domain is valid.

Moreover, the specific BW of the filters used to separate the frequency regions for comparison is typically set ad hoc, after a trial and error process. We shall now present a thorough and unified analysis of continuous-time (CT) adap-tive equalizers that will lead to a set of design criteria to select the proper filter bandwidth according to the characteristics of the communications system such as the data rate, channel BW, or the specific line equalizer used [SAN13, SAN14]. To provide a general analysis, all frequencies used will be normalized to the data bit rate.

As a first design criterion, it is important to mention that the bandwidth of any filter used to implement CT adaptive equalizers should be placed within the first lobe, no matter which architecture is used. To explain the reason behind this, we must first analyze the accumulated power of the PSD of an NRZ data stream (Fig. 2.8). It can be seen that the accumulation of power increases rapidly for fre-quencies close to zero. Then, as the frequency approaches 1/TB, the rate of power

Fig. 2.7 Conceptual scheme of the adaptive equalizers with and without slicer



accumulation drops to zero, when it coincides with the first null of the PSD. Additionally, more than 90 % of the total power of the signal is concentrated within the first lobe. An extension of the bandwidth up to the next lobe (f = 2/TB) only increases the total power by less than 5 %.

To perform the calculations, typical numerical values for short-haul optical com-munication systems have been used. In particular, the data have been chosen to be a RB = 1.25 Gb/s NRZ data stream, the channel bandwidth has been set to 100 MHz (BW of a 50-m SI-POF), and the equalizer has been providing a 1.25 GHz band-width. These values yield an optimal gain for equalization of AOpt

∼= 9.

2.3.1 CT Adaptive Equalizer with a Slicer

In these kind of adaptive loops a slicer after the equalization filter further sharpens the transitions between the bits and therefore boosts the high-frequency content of the signal.

Although one might believe that the effect of the slicer, which is making bit transitions sharper, could suffice to overcome ISI and restore the data signal, this is not the case. To demonstrate this let us consider an ideal slicer and take into account only the filtering effect of the channel. At an ideal, when a transition takes place, its value changes from 1 to 0 or vice versa in a time which is theo-retically zero. For a real signal affected by a low-pass filtering, this transition time increases as the filtering that the signal undergoes becomes more restrictive. Even if an ideal slicer were used to implement the equalizer, it should be ensured that the incoming signal has, in all cases, enough time to cross the comparison thresh-old before the following transition takes place.

In the case of a randomly varying signal such as NRZ modulated data stream, the worst case happens when a single bit is located in a long run of identical bits.

Fig. 2.8 NRZ PSD accumulated power

39

Figure 2.9 depicts this situation. It can be seen that, even if there is no noise or jitter affecting the signal, when sufficient restrictive low-pass filtering affects the signal, the single transition has not enough time to cross the threshold of the slicer. Therefore, it is necessary to include an adaptive equalizer even though a slicer is used in the loop structure. The operation principle of this type of CT adaptive equalizer is based on the fact that the transition time of the ideally equalized signal is known in advance; therefore, if a slicer is designed to produce an output with that given transition time, it can be used as a reference to determine whether the equalized signal is under- or over-compensated and adjust the equalizer accord-ingly [ZHA05].

The transition time1 expected for the ideally equalized signal can be calculated by applying an ideal step to the combination of the channel and the equalizer transfer function particularized for A = AOpt. If this is carried out with the previ-ous model, the transition time ttrans is equal to

It can be seen that its value depends only on the dominant pole of the equalizer.To understand why comparing time transitions is equivalent to a comparison of

the spectral content of the signals both before and after the slicer, remember that the PSD of a signal is found by obtaining the Fourier transform of its autocorrela-tion [HAY01], which, in the case of an NRZ random data, is equal to a sinc2 func-tion, as previously shown. This description becomes more accurate as the length of the bit stream tends towards infinity.

If we consider a real data signal with finite transition times, the shape of its auto-correlation deviates from that of the ideal signal. Figure 2.10a shows the triangular shape of the auto-correlation when the transition times range from 0 to TB. We can see that it is smoothed and extends beyond ±TB. If its Fourier transform is obtained

1 The transition time is defined as the time taken by the signal to change from a specified low value to a specified high value or vice versa. In our case, these values are 10 and 90 % of the step height.

(2.14)ttrans =1

2 · π · pEq· ln 4

Fig. 2.9 a Ideal pulse and b ideal pulse after low-pass filtering



(Fig. 2.10b), the deviations from the triangular shape derived from the finite transi-tion times result in variations in the PSD, especially for high frequency components, which appear over-attenuated.

In other words, it is possible to assimilate changes in the transition time of the signal (time domain description) to changes in PSD (frequency domain description); so, considering the PSD of the slicer output signal as the reference to drive the adaptation loop is equivalent to considering its transition time. This way, the adaptation loop can be closed by comparing a certain frequency range of the PSD at the input and output of the slicer; the choice of frequencies for PSD comparison must be made in order to maximize the sensitivity of the adap-tation loop.

The PSD of the equalizer input signal is the combination of the PSD of the data stream (a sinc2 function) and the LPF that models the channel; the PSD of the equalizer output results from applying HEq(s) to its input.

The relationship between the power spectral densities at the input Sin(f ) and the output Sout(f ) of a system with a transfer function equal to H(f ) is given by

As the input data stream passes first through the channel, HCh(s), and then the equalizer, HEq(s,A), we can relate the PSD of the equalizer output (Sout,eq(f ,A)) with that of the transmitted signal (Sin(f )) by

As the slicer is designed so that the transition times of its output are those expected for the ideally equalized signal, we can state that the PSD of its output Sout,comp(f ) is equal to Sout,eq(f ,A) for optimal equalization (A = AOpt)

(2.15)Sout(f ) = Sin(f ) ·[

H(jf )]2

(2.16)

Sout,eq(f ,A) = Sin(f ) ·[

HCh(jf )]2

·

[

HEq(jf ,A)]2

=

(

sin (π · f )

π · f

)2

·

p2Ch

f 2 + p2Ch·

(1+ A · pEq)2· f 2 + p2Eq

f 2 + p2Eq

Fig. 2.10 a Autocorrelation and b PSD of a random signal with transition times from 0 (red) to 100 % of the bit period (blue)

41

The adaptation loop uses two filters to select only a certain part of the spectrum. In this way, two different frequency ranges are compared. The accumulated power for comparison, Pacc(A), can be obtained as the integral of Sout,eq(f ,A) within the pass-band of the filters.

The sensitivity of the equalizer is given by how it reacts to changes in the boosting gain A; therefore, the optimal frequency range for the filters in this design is that which maximizes it. To determine which frequency regions are the most susceptible to changes in A, the derivative of Pacc(A) with respect to A in the vicin-ity of AOpt must be calculated

Equation (2.18) has no analytic solution but it can be solved numerically. The choice of the filter characteristics for the implementation of a CT adaptive equal-izer with a slicer must be made to maximize the product

We shall particularize to two singular cases to see how the bandwidth of the filters should be chosen.

Two HPFs

If two high pass filters (HPFs) are used, the limits of the integral range from the cut-off frequency of the filters to infinity; in practical terms the upper limit can be set to RB as almost all spectral power is concentrated within the first lobe.

A plot of (2.18), (2.19), and the accumulated power for AOpt is given in Fig. 2.11. It can be seen that the relative variation of the accumulated power for changes in A increases with the cut-off frequency. The increase is initially fast but its rate decreases to reach a limit value for cut-off frequencies close to the bit rate. This figure also shows how the accumulated power decreases as the cut-off frequency increases, which results from the fact that a narrower frequency range that, moreover, has less power is being taken into account. Examining the plot of (2.19) in Fig. 2.11, it can be seen how the frequency range that maximizes the sensitivity of the system spans around 0.25 · RB.

On comparing it with values proposed in the literature, we see that in [HAR99] a cut-off frequency of 50 MHz is chosen for a 147 Mb/s signal, which agrees with the result obtained by the application of the criterion.

(2.17)

Sout,comp(f ) = Sin(f ) ·[

HCh(jf )]2

·

[

HEq(jf ,A)∣

∣

AOpt

]2

=

(

sin (π · f )

π · f

)2

·

p2Eq

f 2 + p2Eq

(2.18)

∂

∂APacc(f ) =

∂

∂Aacc

[

∞

∫

0

Sout,eq(f ,A)

]

A=AOpt

=

∂

∂Aacc

[

∞

∫

0

Sin(f ) ·[

HCh(jf )]2

·

[

HEq(jf ,A)]2

]

A=AOpt

(2.19)P2

acc(A) ·∂

∂APacc(A)

∣

∣

∣

∣

AOpt



Two BPFs

In this case, the integral limits should be the upper and lower cut-off frequen-cies of the band pass filters (BPFs). The design of BPFs with a very narrow pass-band is challenging and results in power-hungry systems; since the equalizer has to adapt to process, voltage and temperature (PVT) variations, a pass-band of roughly 50 % of the BPF centre frequency is a typical choice [FAY08].

A plot of (2.18), (2.19), and the accumulated power for AOpt is given in Fig. 2.12 for two BPFs. In a similar way to the previous case, the relative variation of the accumulated power increases as the centre frequency of the BPFs increases. This justifies the choice of a center frequency for the BPFs equal to the data bit rate made by [FAY08]. However, Fig. 2.12 shows that the power of the reference signal after filtering has a maximum at a frequency between 0.4 and 0.5 of the bit rate. Looking the plot of (2.19) in Fig. 2.12 it can be argued that, in reality, choosing a central frequency for the BPFs in the vicinity of 0.5 · RB achieves a good trade-off between relative variations and total accumulated power for robustness and good sensitivity. This has been the choice made in [GON07], in which BPFs with a center frequency of 5 GHz have been chosen to equalize a 10 Gb/s bit stream.

No Filters

Finally, in [CHE07, HOO04, YOO06, ZHA05], filters at the adaptation loop are eliminated altogether in an attempt to save power and area, and also to avoid the problems caused by filter mismatch and noise. Looking at Fig. 2.11, this situation

Fig. 2.11 Frequency dependence of the variation of the accumulated power with respect to A (pointed), accumulated power for AOpt (dashed), and their product (line) for CT adaptive equalizers with a slicer and two HPFs

Fig. 2.12 Frequency dependence of the variation of the accumulated power with respect to A (pointed), accumulated power for AOpt (dashed), and its product (line) for CT adaptive equalizers with a slicer and two BPFs

43

corresponds to minimum accumulated power relative variation, which suggests that the overall system sensitivity will be affected negatively; in fact, output rms jitter in [HOO04] is 11.4 % of the bit period, in [CHE07] is 5.3 %, in [ZHA05] is the 4 %, whereas it is only 2.2 % in [GON07], and 2.1 % in [FAY08].

2.3.2 CT Adaptive Equalizer with Spectrum-Balancing Technique

Like the previous case, the operation of CT adaptive equalizers with spectrum-balancing technique relies on the fact that the characteristics of the input to the communications system are known in advance. As the power ratio at different frequency ranges is constant, as shown in Chap. 1, we can control the adap-tation loop using the information of the power spectrum at the output of the equalizer.

Several structures can be used to implement the comparison of the power at different frequency ranges. Some are shown in Fig. 2.13 which are realized by a LPF and a HPF [LEE06], a LPF and an APF [CHE10, HON10, SHI09, SUN05], two BPFs [MAX05], or two LPFs (that were first proposed for the authors of this work) [GIM13b]. Theoretically, any other combination of filters could be used. However, for different reasons they are not practicable. Consider as an example two HPFs. In this case, although they would select different parts of the spectrum and the comparison would be possible, both filters would take into account the high frequency region of the spectrum, and therefore, any change of the fiber char-acteristics would drastically affect both filter outputs; therefore, making the com-parison rather unreliable.

When a LPF and a HPF are used to separate the frequencies for power compari-son, their BWs are usually set at the frequency that separates the PSD of the ideal signal into two parts with equal power, fm; that is

In the case of an NRZ data stream this frequency can be found to be fm = 0.28 · RB [LEE06]. If other modulation format is used, this value changes.

(2.20)fm∫

0

TB

(

sin (π · f · TB)

π · f · TB

)2

df =∞

∫

fm

TB

(

sin (π · f · TB)

π · f · TB

)2

df

Fig. 2.13 Some possible combination of filters for CT adaptive equalizer with spectrum-balancing technique


http://dx.doi.org/10.1007/978-3-319-10563-5_1


Although, in theory, any arbitrary frequency could be set to divide the spectrum of the data stream, the choice of the frequency that splits it into two parts with equal power avoids the need to re-scale the power of each part for proper compari-son, which results in a simpler design.

When a different spectrum separation scheme is used, whether it is the combi-nation of a low-pass and an all-pass filter, two band-pass filters, or two low-pass filters, the choice of the filter bandwidths is not straightforward, and typically a trial and error method is used by the designers. Moreover, in the case of BPFs, a trade-off has to be kept between spectrum requirements and power consumption. In fact, realizing the spectrum-balancing technique with BPFs greatly increases the total power consumption of the system, which has caused them to be relegated against other, preferred architectures [SHI09]. In the following, a general criterion will be extracted for a proper choice of these values.

LPF-HPF

As mentioned, for this architecture, both filters are typically chosen to have a cut-off frequency equal to the frequency that separates the PSD into two parts with the same power. In the case of an NRZ stream, this frequency is 0.28 · RB.

However, the use of the sinc2 function does not completely model the system because the actual PSD of the ideally equalized signal is affected by the equalizer pole (2.17). Figure 2.14 shows the comparison of the PSD of the resulting signal and that of the ideal NRZ stream. It can be seen how, despite being similar, high frequency components are over-attenuated. In this case, a frequency equal to 0.28 · RB does not separate the PSD into two parts with equal power so this value must be recalculated.

Considering normalized frequencies, the expression that determines the proper cut-off frequency fco with optimal gain AOpt is given by

As an example, for the values used in this book, the cut-off frequency must be set at fco = 0.22 · RB. Figure 2.15 shows how fco changes according to A; for a cut-off fre-quency of the filters equal to 0.28 · RB, it is necessary that AOpt = 23, which results in signal over-boost and thus non-optimal equalization and an increased SNR.

(2.21)fco∫

0

Sout,eq(f ,A)

∣

∣

∣

∣

AOpt

df =∞

∫

fco

Sout,eq(f ,A)

∣

∣

∣

∣

∣

AOpt

df

Fig. 2.14 PSD of an ideal and an ideally equalized NRZ data stream

45

LPF-APF

In this case, as well as in all the remaining cases, the outputs of the two filters have different powers, so it is no longer possible to divide the PSD into two halves with equal power for direct comparison and power re-scaling is necessary by using some means of amplification.

To maximize sensitivity, we must use the range of frequencies with greater var-iation of accumulated power against variations of the boosting gain A in a manner similar to that used for the adaptive equalizer with a slicer.

The PSD of the signal after the line equalizer was given in (2.16). If its deriva-tive with respect to the boosting gain A is calculated around the optimal gain AOpt, the resulting expression will indicate which frequency changes in A produce larger changes in the total PSD. So, if the derivative with respect to the frequency f of that expression particularized for the optimal adaptation gain AOpt is obtained and equaling to 0, that yields (2.22); from it, the value of the frequency fmax for maxi-mum sensitivity against changes in A around AOpt can be obtained.

Frequencies around fmax must be used to select the pass-bands of the filters to max-imize the sensitivity to variations in the spectrum of the signal. That is, one of the filters has to give way to frequencies around fmax while the other has to block them.

To illustrate this behavior, let us substitute the numerical values in (2.22). It can be seen in Fig. 2.16 that the maximum variation is achieved for a frequency slightly above 20 % of the bit data rate, a value that will be taken as a reference to establish the filter bandwidth criterion.

As the APF lets all frequencies through, the LPF has to block those in the range of fmax. This way, the criterion is that its cut-off frequency should be placed well below it. This way, only the all-pass filtered signal will have the maximum accu-mulated power variation.

If this result is compared to adaptive equalizer designs reported in the litera-ture, it can be seen that the LPF bandwidth typically lies well below thedata rate. For example, in [HON10] a bandwidth of 100–150 MHz for a 1 Gb/s signal is

(2.22)∂

∂f

[

∂

∂ASout,eq(f ,A)

∣

∣

AOpt

]

= 0 → fmax

Fig. 2.15 Dependency of fco on A for spectrum-balancing technique with LPF and HPF. fco = 0.28 corresponds to A = 23 whereas for AOpt = 9 a value of fco = 0.22 is obtained



proposed to the LPF, in [SUN05] a bandwidth of 15 MHz for a 20 Gb/s signal, in [CHE10] a bandwidth of 527 MHz for a 5 Gb/s signal, in [GIM13a] a band-width of 130 MHz for a 2.5 Gb/s signal, whereas [SHI09] sets the bandwidth at 100 MHz for a 5 Gb/s signal. These results agree with the proposed criterion.

Two BPFs

Similarly, in the case of two BPFs, the choice of their BWs must be carried out so that the frequencies that correspond to maximum ∂

∂ASout,eq(f ,A)

∣

∣

AOpt are blocked by

one of the filters and let through by the other for enhanced comparison. According to this, one of the BPFs must have its pass-band centered on fmax whereas for the other BPF it should be placed either well above fmax or well below it. To facilitate the design of the BPF while saving area and power, it is preferable to choose a pass-band well below fmax.

If this result is compared with adaptive equalizer designs reported in the lit-erature, in [MAX05] values of 200 and 600 MHz for a 3.2 Gb/s signal have been chosen, which corresponds to 0.06 · RB and 0.19 · RB, which is in agreement with the proposed criterion where fmax = 0.2 · RB.

Two LPFs

Following the argument used so far, the bandwidth of the two LPFs must be chosen so that one of them blocks the frequencies that maximize ∂

∂ASout,eq(f ,A)

∣

∣

AOpt while

the other lets them through. That is, one LPF should have a bandwidth well below fmax whereas for the other one, a value roughly above fmax will suffice since the contribution to accumulated power of higher frequencies is small and does not com-pensate for the design challenge and higher power consumption of a LPF with a higher cut-off frequency.

If this result is compared with adaptive equalizer designs reported in the litera-ture, in [GIM13b], the cut-off frequencies of the LPFs are set to 15 and 300 MHz for a system operating at 1.25 Gb/s. These values correspond to 0.01 · RB and 0.24 · RB, which agrees with the proposed criteria.

Fig. 2.16 Variation of the PSD of the equalized signal with respect to A at AOpt. The maximum variation is obtained for f just above 0.2 · RB

47

2.3.3 Summary

Table 2.1 summarizes the theoretical criterion for the filters bandwidth selection in every case and compares them with the values used in literature. The values obtained according to the criteria coincide with the ad hoc values proposed in the literature.

2.4 Loop Filter Selection Criteria

We have explained how to select the BW of the loop filters; but, how can we choose between different filter combinations?

To compare different possibilities, the four adaptation loop configurations pre-viously shown were built using Simulink®. To make the simulations more real-izable, a second pole has been included in the split-path configuration of the equalizer. A tunable zero has also been included. The structure using a slicer has been disregarded as it increases circuit complexity, power dissipation and area consumption since it requires generating sharper rising and falling edges of the signal entering from the line equalizer [CHE10, LEE09].

We use a 1 Gb/s NRZ PRBS with 231 − 1 maximum length. This sequence passes through a block that simulates the behavior of a Mitsubishi GH SI-POF, whose frequency response for different fiber lengths was shown in Fig. 1.21. The signal at the input of the equalizer is shown in Fig. 2.17, where ISI can clearly be observed. At 0.1 µs a change in the fiber length is produced. Note that the ISI is more acute after the length increase.

To verify the proper operation of the adaptive loop we change the length L of the fiber at a certain time and observe how both the output of the equalizer and the control signal used to modify the response of the equalizer change. Figure 2.18

Table 2.1 Comparison between theoretical results and published papers

Adaptation loop structure Theoretical results Published results References

Slicer and two HPFs fHPF ≈ 0.25 · RB fHPF = 0.34 · RB [HAR99]

Slicer and two BPFs fBPF ≈ (0.4− 0.5) · RB fBPF = 0.5 · RB [GON07]

Spectrum-balancing technique with LPF-APF

fLPF ≪ 0.2 · RB fLPF = 0.1 · RB [HON10]

fLPF = 7.5 · 10−4

· RB [SUN05]

fLPF = 0.1 · RB [CHE10]

fLPF = 0.05 · RB [GIM13a]

fLPF = 0.02 · RB [SHI09]

Spectrum-balancing technique with 2 BPFs

fBPF1 ≪ 0.2 · RB

fBPF2 ≈ 0.2 · RB

fBPF1 = 0.06 · RB

fBPF2 ≈ 0.19 · RB

[MAX05]

Spectrum-balancing technique with 2 LPFs

fLPF1 ≪ 0.2 · RB

fLPF2 > 0.2 · RB

fLPF1 = 0.01 · RB

fLPF2 ≈ 0.24 · RB

[GIM13b]


http://dx.doi.org/10.1007/978-3-319-10563-5_1


shows the output of the equalizer and how it evolves when the fiber length increases +30 m or decreases −30 m. Figure 2.19 shows the control signal that is carried to the equalizer to change its response.

To compare the different filter combinations used in the implementation of the spectrum-balancing loop we measure the rise and fall times (TR and TF), defined as the times that the control signal takes to go from 10 to 90 % of the total change. Table 2.2 compares these times in each of the stages when the variance2 in all the configurations is the same. It also shows the constant time of theintegrator TINT used in the adaptation loop to generate a clean dc signal to modify the response of the equalizer, because this is a critical parameter in the implementation of the loop as it is related with the area consumption.

The integrator conditions were forced so that the adaptive equalizers could respond to abrupt changes in the conditions of the fiber. In the practice, we will not have such an abrupt change. Therefore, bigger capacitors could be used to obtain a cleaner control signal. These bigger capacitors can be implemented off-chip.

It can be seen that the worst configuration is to use two BPFs, because it has the worst rise and fall times. Moreover, realizing the spectrum-balancing tech-nique with BPFs severely increases the total power consumption of the system.

2 Variance: Difference between the maximum and minimum value in the stationary state.

Fig. 2.17 Equalizer input signal for two different POF lengths: L = 10 m from 0 to 0.1 µs and L = 40 m from 0.1 to 0.2 µs

Fig. 2.18 Adaptive equalizer output for length changes: L↑ = +30 m and L↓ = −30 m

49

Therefore, it has been relegated against other preferred architectures. The LPF-HPF configuration also has higher rise and fall times than the other two alterna-tives (LPF-APF and LPF-LPF). It would also require a double size capacitor in the integrator as the TINT is double. Implementing a HPF usually requires higher power consumption than a LPF. The LPF-APF and LPF-LPF combinations are good choices as they have similar rise and fall times. So, choosing between them depends on the structures used to implement them as well as other parameters such as the variation of the filters with PVT, the matching between the filters, etc.

2.5 Conclusions

In this chapter, the theoretical fundamentals of a class of adaptive continuous-time equalizers have been explained.

First of all, we have provided a basic analysis of the transfer function of the equalizers and explained how the limited frequency response of the channel is compensated.

Then the spectrum of the incoming data has been studied. NRZ is the simplest and the most widely used code, and is therefore the data stream to be going to be used in the following chapters. The normalized power spectral density and how it is affected by different filtering has been shown.

A detailed analysis of the effect of continuous-time adaptive equalizers on the PSD of the incoming signal has been made to formulate general design criteria for

Fig. 2.19 Example of control signal for length changes: L↑ = +30 m and L↓ = −30 m

Table 2.2 Comparative analysis between the different filters configurations. The rise time TR, fall time TF and constant time of the used integrator TINT are compared

Filter TR (µs) TF (µs) TINT (µs)

LPF-APF 2.43 3.76 500

LPF-HPF 3.26 6.36 1,000

BPF-BPF 6.70 6.42 48

LPF-LPF 3.06 5.02 500

2.4 Loop Filter Selection Criteria


the bandwidth of the filters used to implement the adaptation loop. First, a unified treatment in the frequency domain has been presented which is valid for the two main continuous-time adaptive equalization techniques: with both a slicer and the spectrum-balancing technique. In all cases, with the help of either the PSD of the equalized signal or the accumulated power versus frequency, conditions for maxi-mum sensitivity have been used to derive mathematical expressions to obtain the optimal filter bandwidth.

The results have been obtained using frequencies normalized to the data bit rate, which allows a more general formulation of the design criteria. Moreover, these results have been compared with the values reported in recently published works in the field. The conclusion is that the values obtained according to the criteria coincide with the ad hoc values proposed in the literature. This way, we have provided a methodology that can be applied to any other set of conditions, thus facilitating designers the task of choosing the proper loop filters bandwidth in continuous-time adaptive equalizers.

It is important to mention here that the spectrum-balancing technique is valid as long as the PSD of the incoming data stream is known. Therefore, the performed study can be applied to other modulation formats, such as duo-binary and 4-PAM and to other codifications such as return to zero (RZ).

Finally, a functional simulation of the adaptation loop has been provided to obtain a way to choose between different filter combinations. The structure using a slicer was disregarded because it increases circuit complexity, power dissipation and area consumption. So, the filter combinations in an architecture that uses the spectrum-balancing technique were studied. We found that the LPF-APF and the LPF-LPF are the best configurations. Choosing between them will depend on the structures used to implement them as well as other parameters such as PVT varia-tion of the filters, matching between the filters, etc.

Thus, the contents of this chapter let us deal with the design of a continuous-time adaptive equalizer, which is the focus of this book.

References

[BEY08] W. Beyene, The design of continuous-time linear equalizers using model order reduction techniques, in Proceedings of IEEE Electrical Performance of Electronic Packaging (IEEE-EPEP), pp. 187–190, Oct 2008

[CHE07] W.-Z. Chen, S.-H. Huang, G.-W. Wu, C.-C. Liu, Y.-T. Huang, C.-F. Chiu, W.-H. Chang, Y.-Z. Juang, A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer, in IEEE Asian Solid-State Circuits Conference 2007 (ASSCC’07), pp. 396–399, Nov 2007

[CHE10] K.-H. Cheng, Y.-C. Tsai, Y.-H. Wu, Y.-F. Lin, A 5-Gb/s Inductorless CMOS adap-tive equalizer for pci express generation II applications. IEEE Trans. Circuits Syst. II Express Briefs 57(5), 324–328 (2010)

[FAY08] A.A. Fayed, M. Ismail, A low-voltage low-power CMOS analog adaptive equalizer for UTP-5 cables. IEEE Trans. Circuits Syst. I Regul. Pap. 55(2), 480–495 (2008)

[GIM13a] C. Gimeno, E. Guerrero, C. Aldea, S. Celma, A 2.5 Gb/s low-voltage CMOS fully-differential adaptive equalizer, in Proceedings of 2013 SPIE Microtechnologies Conference (SPIE 2013), pp. 876402-1–876402-8, Apr 2013

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[GIM13b] C. Gimeno, C. Sánchez-Azqueta, E. Guerrero, C. Aldea, S. Celma, A 1-V 1.25-Gbps CMOS analog front-end for short reach optical links, in IEEE European Solid-State Circuits Conference (ESSCIRC2013), pp. 339–342, Sept 2013

[GON07] S. Gondi, B. Razavi, Equalization and clock and data recovery techniques for 10-Gb/s CMOS serial-link receivers. IEEE J. Solid-State Circuits 42(9), 1999–2011 (2007)

[GOO85] J.W. Goodman, Statistical optics (Wiley, New York, 1985) [HAR99] G. Hartman, K. Martin, A. McLaren, Continuous-time adaptive analog coaxial

cable equalizer in 0.5 µm CMOS, in Proceedings of the 1999 IEEE International Symposium on Circuits and Systems (ISCAS99), pp. 97–100, Jul 1999

[HAY01] S. Haykin, Communication Systems, 4th edn (Wiley, New York, 2001) [HOL06] T. Hollis, D. Comer, Mitigating ISI through selfcalibrating continuous-time equali-

zation. IEEE Trans. Circuits Syst. I Regul. Pap. 53(10), 2234–2245 (2006) [HON10] D. Hong, S. Saberi, K.-T. Cheng, C. P. Yue, A two-tone test method for continu-

ous-time adaptive equalizers, in Efficient Test Methodologies for High-Speed Serial Links (Springer, Berlin, 2010), pp. 75–87

[HOO04] L. Hoon, H. Gunhee, A low power and small area analog adaptive line equalizer for 100 Mb/s data rate on UTP cable. IEICE Trans. Electron. 87(4), 634–639 (2004)

[LEE06] J. Lee, A 20-Gb/s adaptive equalizer in 0.13-µm CMOS technology. IEEE J. Solid-State Circuits 41(9), 2058–2066 (2006)

[LEE09] D. Lee, J. Han, G. Han, S.M. Park, 10 Gbit/s 0.0065 mm2 6 mW analogue adaptive equalizer utilising negative capacitance, in IEEE International Solid-State Circuits Conference (ISSCC), pp. 190–191, Feb 2009

[MAX05] Maxim Integrated Products, 3.2 Gbps Equalizer and Cable Driver (2005) [SAN11] C. Sánchez-Azqueta, S. Celma, A phase detection scheme for clock and data recov-

ery applications, in Proceedings of the 20th IEEE European Conference on Circuit Theory and Design (ECCTD2011), pp. 130–133, Aug 2011

[SAN13] C. Sánchez-Azqueta, C. Gimeno, S. Celma, A comparative study of con-tinuous-time analog adaptive equalizers, in Proceedings of the 2013 SPIE Microtechnologies Conference (SPIE 2013), vol. 8764, pp. 876402-8, Apr 2013

[SAN14] C. Sánchez-Azqueta, C. Gimeno, E. Guerrero, C. Aldea, S. Celma, Design consid-erations for loop filters in continuous-time adaptive equalizers, in Proceedings of the International Multi-Conference on Systems, Signals and Devices (SSD 2014), Feb 2014

[SHI09] D.H. Shin, J.E. Jang, F. O’Mahony, C.P. Yue, A 1-mW 12-Gb/s continuous-time adaptive passive equalizer in 90-nm CMOS, in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC09), pp. 117–120, Sept 2009

[SUN05] R. Sun, A low-power 20-Gb/s continuous-time adaptive passive equalizer. Thesis, B.S. Tsinghua University 1999, Dec 2005

[YOO06] K. Yoo, G. Han, H. Yoon, Convergence analysis of the cascade second-order adaptive line equalizer. IEEE Trans. Circuits Syst. II Express Briefs 53(6), 507–511 (2006)

[ZHA05] G.E. Zhang, M.M. Green, A 10 Gb/s BiCMOS adaptive cable equalizer. IEEE J. Solid-State Circuits 40(11), 2132–2140 (2005)

References

53

As presented in the introduction, equalization has been widely used to remove or correct transmission deficiencies in many communication systems. We are focusing our equalizer on compensating the limited frequency response of the step-index plastic optical fibers (SI-POFs). Therefore, it should be specifically designed to compensate their deficiencies: 0.18-dB/m transmission attenuation, 45 MHz · 100 m bandwidth-length product and roll-off slope of 12 dB/dec.

The proposed equalizer should have features such as immunity to parasitic sig-nals, high-frequency range, and moderated linearity. If the signal is processed in a balanced way, the interference of parasitic signals coupled through the substrate from the digital sub-circuits will be minimized. Moreover, linearity is improved because of the elimination of even order harmonic distortion; it also cancels the common-mode noise increasing the signal-to-noise ratio (SNR) and duplicates the maximum variation range of the signals.

As the technologies downscale, the transition frequency of transistors increases and the supply voltage decreases. However, transistor threshold voltages do not decrease proportionally to the supply voltage. To make the design totally compat-ible with nanometer CMOS technologies, a supply voltage of 1 V has been cho-sen as a test bench. However, the 1-V circuit design in a standard 1.8-V 0.18-µm CMOS technology (chosen because it is a cost effective technology) supposes a real challenge as most structures proposed so far in the literature lose their advan-tages when operating with such a low-voltage supply.

In this chapter the description of a new line equalizer architecture will be pro-posed and compared with the most widely used equalizer structure: the degener-ated, differential pair-based equalizer. First, a theoretical analysis of the different structures will be presented. For this analysis, a simple small signal model will be used to study the functionality of the equalizer and the analytical dependences of the gain, position of zero and first poles with the different parameters of the design. This will show us the best way of tuning their positions. Although we are

Chapter 3Continuous-Time Linear Equalizers


54 3 Continuous-Time Linear Equalizers

working with high frequencies, which would bring about the need to use more advanced models of the transistors including distributed components, for a first approach it is enough to use quasi-static models of transistors, characterized by their transconductance and output resistance. Nevertheless, all the simulations will be obtained by using high-level Spectre models provided by the design kit of the foundry. This design methodology has been validated for many continuous-time equalizers [ATE12, DON10, RAD05, TAV06]. As we are working with digital sig-nals, analysis of distortion, linearity, etc. are not relevant.

We shall then summarize the main post-layout performances of the new equal-izer architecture and compare the obtained results with those of the conventional degenerated differential pair-based equalizer.

Finally, experimental verification of the proposed equalizer will be presented and compared with previously proposed structures in literature.

3.1 Degenerated Differential Pair

The continuous-time equalizers proposed so far in literature are based on the con-ventional degenerated differential pair [CHE05, HAO10, RAD05, TAV06], which is shown in Fig. 3.1.

By using ideal transistors characterized by their transconductance gm, the expressions for the differential and the common-mode gain are

(3.1)AD(s) =V+

o − V−

o

V+

S − V−

S

= −

gm · RL

1+ gm · RD

·

1+ s · CD · RD

1+ s · CD·RD1+gm·RD

(a) (b)

Fig. 3.1 Degenerated differential pair-based equalizer with a fixed elements, and b tunable elements

55

The differential gain of the equalizer is gm · RL/(1+ gm · RD) and the first pole and the zero are respectively

The dc common mode rejection ratio (CMRR) is given by

If RD and CD are substituted by transistors working as a variable resistance and capacitance respectively, as shown in Fig. 3.1b, the equalizer has tunable zero and gain. By modifying the control voltage VC, the capacitance of the MOS capacitor structure is variable; so, the high frequency boosting can be adjusted accordantly. The frequency responses for different VC are illustrated in Fig. 3.2a. The gain of the equalizer can be tuned by modifying the gate voltage, VC2, of a transistor oper-ating in triode mode. The frequency responses for different VC2 are illustrated in Fig. 3.2b.

As Fig. 3.2 shows, the gain and zero parameters are strongly coupled, that is, if the gain of the equalizer is tuned, the zero of the circuit also changes causing a setback for the equalizer tuning. Furthermore, the imposed supply voltage (1 V) severely limits the dynamic range of the equalizer setting the degenerated differen-tial pair at a disadvantage for tunable low-voltage systems, as shown below.

Obviously, as the previous figures show, other higher frequency poles affect the frequency responses of the equalizer. These poles come from the parasitic capaci-tances of the transistors. However, we consider it unnecessary to include these par-asitics in our expressions as we are interested only in compensating the response of the fiber.

(3.2)AC(s) =2 · V+

o

V+

S + V−

S

= −2 · gm · RL

(3.3)sP = −

1+ gm · RD

CD · RD

(3.4)sZ = −

1

CD · RD

(3.5)CMRR =

AD(s = 0)

AC(s = 0)=

1

2 · (1+ gm · RD)

Fig. 3.2 Frequency responses of degenerated differential pair for different values of the control voltage a VC and b VC2

3.1 Degenerated Differential Pair


3.2 Split-Path Equalizer

An alternative to the degenerated differential pair is to use a split-path equalizer [BAB98, KUD03, ZHA05]. It divides the signal into two paths, as was shown in Fig. 1.11. One path comprises a high pass filter to amplify the high frequency component and the other path is an all pass filter or a low pass filter to match the time delay of first path. The filters involved in the split-path continuous-time equalizer can be implemented either with operational amplifiers in negative feedback or with Gm-C amplifiers. The latter technique presents the best trade-off of power, dynamic range and operation frequency [ALD03]. Its main characteristic is the exclusive use of transconductors and capacitors.

To implement the high-pass filter, we can use a differentiator (see Fig. 3.3). It is based on the current-mode differentiator proposed by El-Masry and Gates [ELM96] but slightly modified as the input of our circuit is a voltage.

By using ideal transconductors, characterized by their transconductance gmi, the output current of the differentiator is

Using this idea, some architectures have been proposed in literature [GIM11b, GIM12]. Also some modifications of it have been proposed establishing a positive feedback in the design of the differentiator path with the purpose of virtually cancel-ling the dominant pole of (3.6) thereby increasing its operation range [GIM11a, c].

Although the previously proposed equalizers provide some advantages versus the degenerated differential pair-based equalizer, such as independent controls of the gain and the zero and higher input dynamic range, they exhibit a lower com-mon-mode rejection ratio (CMRR).

To increase the CMRR, we need an all-pass filter (APF) with a high CMRR. We can modify the technique proposed by Smith and Sánchez-Sinencio [SMI96], and Zele and Allstot [ZEL96] to reduce the common-mode gain of the all-pass path. Figure 3.4 shows the APF configuration using the mentioned technique. It is a fully balanced split-path topology where the T2 transconductor has two outputs with transconductances gm2 and k · gm2, respectively; this second output is used to establish a partial positive feedback loop with cross configuration to increase the ratio between differential and common-mode gain.

Using the previously mentioned differentiator and the high CMRR all-pass filter, the new equalizer proposed (SPEQ) has the transconductor-level structure shown in Fig. 3.5 [GIM14].

(3.6)Iout(s) = −

s · C ·

gm3gm1·gm2

1+ s · C ·

(

1gm1

+1

gm2

) · Vin

Fig. 3.3 Scheme of the differentiator implemented with transconductors

http://dx.doi.org/10.1007/978-3-319-10563-5_1

57

The output current of the all-pass and the high-pass paths are summed by means of the output resistance R0. Therefore, the equalizer provides an additional zero to compensate for the roll-off frequency caused by the SI-POF.

By using ideal transconductors, characterized by their transconductance gmi and output resistance r0i, the expressions for the differential and common-mode gain are

(3.7)

AD(s) =V+

o − V−

o

V+

S − V−

S

= −

R′

5 · R′

1 · gm1 · gm2

k · R′

1 · gm2 − 1

·

1+ s · C · R′

4 ·

(

1+R′3·gm5·gm3gm1·gm2

·

(

1R′1

− k · gm2

))

1+ s · C · R′

4

(3.8)

AC(s) =2 · V+

o

V+

S + V−

S

=

R′

5 · R′

1 · gm1 · gm2

k · R′

1 · gm2 + 1

·

1+ s · C · R′

4 ·

(


·

(

1R′1

+ k · gm2

))

1+ s · C · R′

4

Fig. 3.4 Scheme of the proposed APF with cross-configuration

Fig. 3.5 Scheme of the proposed SPEQ



where1

Therefore, the gain of the equalizer is R′

5 · R′

1 · gm1 · gm2/(

k · R′

1 · gm2 − 1)

, and the first pole and the zero are, respectively

It is satisfied that

The frequency associated with the first pole is between 9 and 10 times higher than the frequency associated with the zero. This range is independent of the gain and the zero location, so a wide equalizer range can be obtained.

The dc CMRR can be directly obtained from (3.7) and (3.8)

If we assume gm1 = gm2 = gm3 = gm5, to simplify the previous equations, we have that the simplified differential and common-mode gain are

1 The symbol || means a parallel connection.

(3.9)R′

5 = rO5 � rO2 � RO

(3.10)R′

4 = rO4 �1

gm4

(3.11)R′

3 = rO3

(3.12)R′

2 = rO2

(3.13)R′

1 = rO1 � r02k

(3.14)sP = −

1

C · R′

4

(3.15)sZ = −

1

C · R′

4 ·

(


·

(

1R′1

− k · gm2

))

(3.16)sP =

[

1+R′

3 · gm5 · gm3

gm1 · gm2·

(

1

R′

1

− k · gm2

)]

· sZ

(3.17)CMRR =

AD(s = 0)

AC(s = 0)=

1+ R′

1 · k · gm2

1− R′

1 · k · gm2

(3.18)AD(s) = −

R′

5 · R′

1 · g2m2

k · R′

1 · gm2 − 1·

1+ s · C · R′

4 ·

(

1+ R′

3 ·

(

1R′1

− k · gm2

))

1+ s · C · R′

4

(3.19)AC(s) =R′

5 · R′

1 · g2m2

k · R′

1 · gm2 + 1·

1+ s · C · R′

4 ·

(

1+ R′

3 ·

(

1R′1

+ k · gm2

))

1+ s · C · R′

4

59

Therefore, the simplified first pole and zero are respectively

The used simplification is only one possibility for providing a better understanding of the obtained expressions but does not suppose any restriction as we can choose any other relation between the different transconductances.

High operating frequencies and low supply voltage require using the simplest transconductor, i.e., the transistor working in common-source topology. This type of transconductor requires no frequency compensation schemes; therefore, we can approach the maximum operating frequency of the transistors, that is, the transi-tion frequency. Moreover, the dynamic range of the transistor working in com-mon-source is higher than that of the degenerated differential pair as its source is connected to ground whereas the source of the main transistor in the degenerated differential pair is connected to the drain of a transistor in saturation region.

Although both class AB or class A operation are presented a priori as a valid option for the implementation of the transconductor [ALD03], class A version has been cho-sen to achieve bias point controllability and better power supply rejection ratio.

The transistor level topology of the proposed equalizer (SPEQ) is shown in Fig. 3.6 [GIM13].

As this figure shows, transistors biased with resistances have been used to implement the transconductors [CHE07, HAN12, ZHA05]. PMOS transistor-based current sources

(3.20)sP = −

1

C · R′

4

(3.21)sZ = −

1

C · R′

4 ·

(

1+ R′

3 ·

(

1R′1

− k · gm2

))

Fig. 3.6 Transistor level topology of the SPEQ



could also been used to bias the NMOS transistors, as they reduce the area consumption for a certain resistance value. However, they generate higher parasitic capacitances at the output nodes reducing the bandwidth of the transconductors and therefore, the BW of the whole equalizer. The use of resistances avoids the need for common-mode feed-back loops that are incompatible with high-frequency behavior. This technique is very usual in many other high frequency circuits, such as source coupled logic circuits.

The circuit can adjust high-frequency boosting by modifying the gate voltage VC of a transistor, Mb1, added in parallel with resistance R3. Figure 3.7a shows the frequency responses for different VC. Note that the main effect of VC is to change gm3. In this way VC tunes the zero location without unduly affecting the pole location. The gain of the equalizer can also be tunable. As shown in (3.7), the gain of the circuit is a product of transconductances and load resistances. As a result, the gain can be modified by varying one of these parameters. It must be mentioned that it is preferable that the selected gain variation technique does not modify the output common-mode voltage, as this would cause the operating point of the subsequent gain stage to vary. A floating load resistor was chosen to modify the gain without affecting the operating point of the transistors and the common-mode output voltage. The simplest implementation of a variable resistor in CMOS technology is a transistor biased in triode region. Therefore, the gain of the equalizer can be changed by modifying the gate voltage VCG of a transistor working as a variable resistor. The frequency responses for different VCG are given in Fig. 3.7b. It shows that, unlike the degenerated differential pair-based equalizer, the control mechanisms of the gain and zero are completely orthogonal.

The tuning method in the proposed equalizer is limited for an input VC and VCG of 400 mV each one. This is due to the saturation condition of the control PMOS transistors, Mb1 and Mb2, as the supply voltage is 1 V. Beyond this 400 mV input limit, Mb1 and Mb2 will enter in the cut-off region and no more changes will be observed in the frequency response of the equalizer.

The proposed equalizer (SPEQ) not only maintains similar values for the CMRR under the same operation conditions, but also overcomes the limitations of the degenerated differential pair-based equalizer as it presents a higher operation range and decoupled tunability of both the gain and the zero.

Fig. 3.7 Frequency responses of the proposed SPEQ for different values of the voltage a VC, and b VCG

61

3.3 Comparative Analysis

The two analog continuous-time line equalizers have been designed in a standard 0.18-µm CMOS technology with a single supply voltage of 1 V.

Simulations have been carried out using Spectre with a BSIM3v3.2 level 53 transistor model for a 0.18-µm CMOS technology from UMC. This technology has 1 poly and 6 metal layers; the capacitors are fabricated with metal-insulator-metal (MIM) structures which have 1 fF/µm2 and are implemented between metal 5 and metal 6; and the resistors are implemented with high resistivity polysilicon (HRP) layers which have 1,039 Ω/sq.

The layout of the new proposed equalizer is shown in Fig. 3.8. As the layout of an analog integrated circuit directly influences its performance, different layout strategies have been used to minimize effects such as crosstalk, mismatches, coupled noise, etc. Special attention has been paid to asymmetries to avoid large offset. Symmetry sup-presses the effect of common-mode noise and even-order nonlinearity. Therefore, the circuit implementation has been obtained by considering not only matching between transistors but also symmetry between filter sections, to minimize parasitic effects and coupling. Symmetry must be applied to the considered devices but also to their surrounding environment. Layout techniques, such as common-centroid topologies, minimize the first-order effects of mismatch due to gate-oxide thickness gradients, especially when dealing with threshold voltage, and other process variations.

We have also taken special care to outline the signal paths, in an attempt to ensure the best matching between them and obtain the outstanding benefits of bal-anced signals, which greatly depend on the circuit symmetry.

Fig. 3.8 Layout of the proposed equalizer SPEQ (6,050 µm2)



Transistor layout was carried out using different design rules to achieve adequate matching. In cases where matching between components was critical, common-centroid structures were employed. Multi-finger transistors were used and the number of fingers were chosen achieving a trade-off between gate resistance reduction and minimizing the source/drain perimeter capacitance contribution. These active elements requiring symmetry must be laid out with the same orientation, leading to gate-aligned transistors. Likewise, dummy transistors were introduced in the stack borders to guarantee obtaining identical surrounding conditions for all the active elements. These dummies were connected to the adequate power supply, to keep them in the cut-off region.

The proposed equalizer has floating capacitors in their design that were imple-mented by metal-insulator-metal (MIM) structures. Parasitic capacitances must be considered when implementing capacitors, especially the capacitance between the lower electrode and the substrate. A technique, very used in poly capacitors for maintaining an adequate symmetry while minimizing this parasitic effect, consists of splitting the desired capacitor C into two equal capacitive elements C/2 in an anti-parallel connection. Comparing the results with and without the implementation of this technique, we checked that its effect is not very significant in MIM capacitors.

For the layout of resistors, polysilicon resistors were used. When matching was necessary, they were interdigitated with dummy structures on both sides.

Guard rings have been included in the circuit layouts in order to isolate the sen-sitive sections from the substrate noise produced by other sections. A guard ring may be simply a continuous ring made of substrate ties that surround the circuit, providing a low-impedance path to ground for the charge carriers produced in the substrate. Good substrate isolation also reduces sources of distortion arising from adjacent circuit crosstalk.

The equalizer has to compensate the limited bandwidth of a Mitsubishi GH SI-POF, whose bandwidth depends greatly on its length. Reliable electrical models with passive devices are employed to model the frequency response of the fiber for different lengths. For details of the fiber and the used model see Appendix A.

The frequency response after equalization for 50-m length (fiber BW of 100 MHz) is shown in Fig. 3.9 for the degenerated differential pair-based equalizer (DDP) and the new proposed equalizer (SPEQ). The CMRR is shown in Fig. 3.10.

Fig. 3.9 Output frequency responses of the different equalizers using a 50-m POF

63

The main performances of the equalizers are compared in Table 3.1 for a 50-m SI-POF. The bandwidth of the received signal can be enhanced from 100 MHz to 1.30 GHz with the proposed SPEQ. However, with the equalizer based on degenerated differential pair, the bandwidth of the receiver signal only reaches 1 GHz. Furthermore, the proposed equalizer exhibits an input range three times higher than that of the degenerated differential pair, i.e., the signal-noise ratio is higher and the integrity of the signal improves. As a drawback, it presents a relatively higher input noise and higher power consumption.

Now, we shall show the dependence of the frequency responses of the two structures on common-mode dc input voltage (Fig. 3.11), supply voltage (Fig. 3.12) and temperature (Fig. 3.13). It can be seen that the variation of both the common-mode dc input voltage and the temperature have a worse effect on the degenerated differential pair-based equalizer. Both parameters affect changing the gain of the circuits. However, whereas the zero frequency of the proposed equal-izer stays relatively constant, the zero of the degenerated differential pair-based equalizer changes substantially.

Figure 3.14 shows the dependence of the bandwidth of the system after equaliza-tion of a 50-m POF with different parameters. Figure 3.14a shows the impact of the dc input voltage on the equalizer bandwidth. While the bandwidth of the proposed equal-izer does not vary too much with the input voltage, the bandwidth of the degenerated differential pair however is considerably affected. Therefore, any variation on the dc

Fig. 3.10 CMRR versus frequency of the different equalizers

Table 3.1 Performance summary

Parameter DDP SPEQ

Gain (dB) −5.1 −4.93

BW (50-m) (GHz) 1.05 1.30

GBW (50-m) (GHz) 0.58 0.74

Power (mW) 0.90 9.1

Supply voltage (V) 1 1

dc CMRR (dB) 9 9.8

Input range (mV) −100 to 100 −300 to 300

Input noise (mV) 0.81 0.99



voltage at the input of the equalizer would make the degenerated differential pair not to work properly, since it would be really difficult to implement an adaptation loop that would be able to correct these variations. The SPEQ presents smaller variation with the dc input voltage for two main reasons: it has a higher CMRR, and when the dc input voltage changes, both the gain and the zero change in the same way. In Fig. 3.14b, it can be seen that the effect of changes of supply voltage in the bandwidth is very similar in the degenerated differential pair-based equalizer, and SPEQ. Figure 3.14c shows that whereas the bandwidth of the new proposed equalizer does not vary too

Fig. 3.11 Variation of the response of the equalizer with the input common-mode dc voltage (VCM) for a degenerated differential pair-based equalizer, and b proposed equalizer

Fig. 3.12 Variation of the response of the equalizer with the supply voltage (VDD) for a degenerated differential pair-based equalizer, and b SPEQ

Fig. 3.13 Variation of the response of the equalizer with the temperature (T) for a degenerated differential pair-based equalizer, and b SPEQ

65

much with the temperature, the variation of the bandwidth of the degenerated differ-ential pair-based equalizer is very pronounced and it can cause it not to work properly. This is because in the degenerated differential pair-based equalizer, the change in the temperature affects the value of the resistances what make the gain of the equalizer to change substantially; the zero, however, does not seem to be so affected.

Fig. 3.14 Bandwidth of equalized 50-m POF versus a dc input voltage, b supply voltage, and c temperature



Monte Carlo simulations have been carried out for process and mismatch. The simulations for bandwidth and gain are shown in Fig. 3.15 for the two equalizers. Input noise and output voltage dispersions are shown in Fig. 3.16. It can be seen that the standard deviation (sd) in the degenerated differential pair is higher than the proposed equalizer in all the cases. Moreover, the bandwidth of the degenerated differential pair is much lower than the mean value (mu) in the 18 % of the cases.

Corner analysis has also been performed to compare the two structures and the results of the minimum, typical, and maximum values are presented in Table 3.2. It can be seen that the degenerated differential pair has a maximum variation of 89 % for the BW, 78 % for the gain and 18 % for the output dc voltage; and SPEQ has a maximum variation of 23 % for the BW, 34 % for the gain and 4 % for the output dc voltage. Therefore, the proposed structure presents better results than the degenerated differential pair-based equalizer in terms of corner analysis.

So, the proposed equalizer overcomes the gain-bandwidth product (GBW) and input range limitations suffered by the conventional degenerated differential pair-based equalizer without significantly affecting the rest of the parameters.

Moreover, it is more robust as the main characteristics of the proposed equalizer are less affected by the PVT variations and by the common-mode input voltage.

We define inter-symbol interference (ISI) as [AZN13]

where d is defined in Fig. 3.17, and VH and VL are the high and low levels.

(3.22)ISI =2 · d

VH − VL

Fig. 3.15 Monte Carlo simulations for a bandwidth, and b gain. The parameter mu is the mean value, sd is the standard deviation, and N is the total number of samples

67

Figure 3.18 shows the eye diagram of the output of a 50-m Mitsubishi GH POF for a PRBS of (231-1) NRZ data stream at 1.25 and 2 Gb/s. From the outcome of the test, we can see that the eye opening is closed because of the limited bandwidth of the POF.

Figure 3.19 shows the eye diagrams after the equalization based on the two equal-izers previously presented for 1.25 and 2 Gb/s. As the simulator does not allow perform-ing a transient simulation including the effect of noise, root mean square (rms) output noise obtained with a noise analysis (see Table 3.1) has been added to each point of the time analysis based on a normal distribution. To make this, first, using the Frequency Analysis Utility provided by Cadence Virtuoso Analog Design Environment, we can obtain the noise power spectrum in each node of the circuit. Then a noise value based

Fig. 3.16 Monte Carlo simulations for a input noise, and b dc output voltage. The parameter mu is the mean value, sd is the standard deviation, and N is the total number of samples


Table 3.2 Corner analysis for equalization of 50-m SI-POF


on a normal distribution where the standard deviation is the rms output noise has been added to each simulated transient point.

Examining the eye diagrams of Fig. 3.19 we can see that the degenerated dif-ferential pair-based equalizer presents worse results in terms of rms deterministic jitter (9.97 and 11.96 % for 1.25- and 2-Gb/s signals). The proposed equalizer pre-sents a jitter of 2.58 and 3.80 % for 1.25 and 2 Gb/s signals, respectively.

The degenerated differential pair-based equalizer also presents worse results in terms of ISI (1.49 and 1.24 for 1.25- and 2-Gb/s signals, respectively). The pro-posed equalizer presents similar results in terms of ISI: 0.62 and 0.55 for 1.25- and 2-Gb/s signals, respectively.

3.4 Experimental Verification

In this section, the experimental set-up and results of the proposed equalizer are described.

To test the proposed equalizer, the implemented prototype includes the pro-posed continuous-time equalizer, which boosts the high-frequency component of

Fig. 3.17 Eye diagram degraded by inter-symbol interference

Fig. 3.18 Eye diagrams before equalization with a NRZ PRBS 231-1 of data rate a 1.25 Gb/s, and b 2 Gb/s

69

the signal, and a 50-Ω output driver to perform experimental measurements (see Fig. 3.20).

Figure 3.21 shows the output driver that is necessary for performing experi-mental measurements [AZN11]. Its main task is to drive 50-Ω loads with high out-put swing. Furthermore, a differential output is highly desirable to increase supply rejection and improve noise immunity. A higher supply voltage (1.8 V) is used to increase the output signal levels to a value suitable for experimental measurements and to facilitate the design of the driver. The first stages are used to increase the voltage level to one that can handle the differential pair. The bias current of the

Fig. 3.19 Eye diagrams after equalization with a NRZ PRBS 231-1 for 1.25 and 2 Gb/s for a the degenerated differential pair-based equalizer, and b the SPEQ

Fig. 3.20 Block diagram of the fabricated line equalizer



first stages is 1.2 mA, for the first differential pair is 15.2 mA, and for the last dif-ferential pair 11.9 mA. The output driver shows a 20-dB gain.

3.4.1 Layout Strategies

In addition to the layout strategies previously mentioned to design the layout of the proposed equalizers (symmetry, matching, dummies, guard rings, etc.), addi-tional strategies have been used in the design of the final chips.

To connect the bond wires to the die, large pads are placed on the perimeter of the chips and connected to the corresponding nodes in the circuit. But the interface between an IC and the external world entails the problem of electrostatic discharge (ESD). This effect occurs when an external object having a high potential touches on the connections to the circuit and can cause permanent damage on the chip.

To overcome the ESD a structure based on two diodes becoming forward biased and providing a low-impedance path to pull the excessive charge away has been imple-mented. Such elements clamp the external discharge to ground or VDD, thereby limit-ing the potential applied to the circuit. Although more sophisticated techniques such as those proposed in [NIK02] can be used, the used protection diodes are sufficient for our purposes. However, for high frequency applications, these ESD devices are considered to be bad capacitors as they introduce substantial capacitances. Therefore, ESD protec-tion devices have been included in all the supply and control paths but never in the input and output signal paths so that do not degrade the frequency response of the circuits, where simple custom pads formed with only top metal were used.

To implement the full system layout, differences in the paths of balanced signals were carefully avoided as it is absolutely necessary to obtain the benefits inherent to these signals. In addition to this, we must endeavor to obtain an adequate distri-bution of the bond-pads, placing the input and output pads as far as possible from each other to avoid undesirable coupling. As previously mentioned, balanced signal paths were drawn symmetrically and the same was done with bond pads.

Fig. 3.21 Output driver

71

3.4.2 Electrical Set-Up

This section summarizes the electrical measurement strategies used for the IC pro-totype characterization.

Besides all the conventional equipment existing in a typical electronic labora-tory, a Rohde & Schwarz ZVL6 vector network analyzer (9 kHz–6 GHz) has been used to properly characterize the proposed design.

The first thing to take into account in the measurement of an IC is the design of PCB required to support the chip and connect it to the measurement devices and auxiliary circuitry.

One of the most restrictive problems encountered when dealing with a very high frequency experimental set-up is the influence of parasitic capacitances, asso-ciated either to the input/output pads, the IC package or to the PCB where the pro-totype to be characterized is mounted. These parasitic effects limit the expected circuit bandwidth. To minimize the parasitic capacitance, the prototype includes the bare die without package to easily perform the experimental measurements. It is fitted with silver epoxy and aluminum wire-bonding on the PCB, as shown in Fig. 3.22.

The most important requirement of a PCB in this work is to avoid as much as possible parasitic capacitances along the signal path from the generator to the chip input pads and from the output pads to the measurement devices. To do so, SMA connectors up to 18-GHz root signal lines. The output signal lines include 100-nF decoupling ceramic capacitors. The supply lines are noise- filtered by using grounded 100-nF and 10-µF ceramic capacitors. Input and output resistors of 50 Ω have also been used where necessary to maximize power transfer.

To electrically test the prototypes, we usually need a balanced input signal. However, this is not a common choice regarding conventional measurement

Fig. 3.22 Bare die with wire bonding to the PCB



equipment. To generate balanced signals, Prodyn Baluns (BIB-100G) with a bandwidth from 250 kHz to 10 GHz have been used both at the input and output paths.

For frequency-domain characterization, a complete calibration process for a 2-port system should be performed. It consists of four measurements: short, open, load and through (SOLT). Network analyzer is calibrated with a SOLT kit (Rohde & Schwartz ZV-Z132 Calibration Kit). After calibration, the reference plane is defined to measure the device under test (DUT).

In addition to the calibration, if parasitic effects of the rest of necessary com-ponents degrade significantly the frequency response of the DUT, compensation can be achieved thanks to de-embedding techniques. For that, a de-embedding cir-cuitry is included in the chip design. This de-embedding circuitry is composed of a second path between inputs and outputs which includes the output driver. It is employed to cancel pad parasitic capacitances, so that it is possible to obtain the ratio between the two measurements represented in Fig. 3.23 leading to the real frequency performance of the DUT.

Moreover, a dc input voltage is needed to the correct operation of the equalizer. For that, a Bias-TEE circuit from Mini-Circuits (ZFBT-4R2G+, 10–4,200 MHz) has been used. It adds to the RF input a dc voltage.

One goal of the electrical measurements is to obtain the bandwidth improvement for different POF lengths. Thus, to simulate the response of the fiber so that the frequency response of the fiber-equalizer combination can be obtained, we have designed a PCB with different passive circuits that simulates the response of the POF for different lengths. This PCB is shown in Fig. 3.24. It has been included in the signal path when necessary.

The complete schematics for the test set-up is shown in Fig. 3.25 and a photo-graph of the laboratory electrical test bench is shown in Fig. 3.26.

3.4.3 Electrical Characterization

To test the proposed equalizer, it has been included in a front-end like the previously described model. The correct operation of the proposed design has been confirmed by transistor level and post-layout simulations. The equalizer is fed with 1 V and the output driver with 1.8 V.

Fig. 3.23 Electrical test set-up that makes possible the compensation for the off-chip parasitic elements during measurements

73

Fig. 3.24 POF electrical emulator on PCB

Fig. 3.25 Schematics of the complete electrical test set-up for the integrated prototype



Figure 3.27 shows the layout and microphotograph of the design and Fig. 3.28 a microphotograph of its active area, over which the location of its main blocks has been superimposed. The dimensions of the full chip are 0.747 · 0.640 mm2, whereas the active area is 0.012 mm2, where 0.006 mm2 correspond to the line equalizer, and 0.006 mm2 to the driver.

Figure 3.29 shows the fabricated PCB with the bare die without package for electrical measurements of the SPEQ chip.

The whole circuit maximum power consumption is 118.6 mW with maximum peaking, where 8.6 mW corresponds to the line equalizer, and 110 mW to the out-put driver.

Fig. 3.26 Electrical test bench

Fig. 3.27 a Layout and b microphotograph of the chip for testing the SPEQ

75

Fig. 3.28 Microphotograph of the active area of the SPEQ chip (0.012 mm2)

Fig. 3.29 PCB for electrical measurements of the SPEQ chip

Fig. 3.30 Measured S21 parameter



Figures 3.30 and 3.31 show measured S-parameters for VC = 0.5V.To show the correct operation of the prototype, Fig. 3.32 shows the dependency

of the frequency response of the proposed equalizer with the boosting control voltage, VC, and with the gain control voltage, VCG. We can also test how the variation of the supply voltage or the input common mode dc voltage changes the response of the equalizer. Figure 3.33 shows these dependencies.

Fig. 3.31 Measured a S11, and b S22 parameters

Fig. 3.32 Measured S21 for different values of a VC, and b VCG

Fig. 3.33 Measured S21 for different values of a VDD, and b VCM

77

To demonstrate the bandwidth improvement for different POF lengths, Fig. 3.34 shows the frequency responses at the output of the POF electrical emu-lator without including the IC and at the output of the whole system after data treatment. The bandwidth of the received signal can be enhanced from 100 MHz to 1.35 GHz and from 300 MHz to 1.35 GHz for 50- and 10-m POF, respectively.

This important result validates the effectiveness of the proposed architecture.

3.5 Conclusions

This chapter has covered an in-depth analysis and an experimental characteriza-tion of the line equalizer block. This section is dedicated to summarizing the main results and to performing a comparison with similar recent reported equalizers in order to underline the advantages of the new line equalizer.

The required performances are: high speed, quantified by the bandwidth of the fiber-equalizer combination for the same gain; high input dynamic range, which is important because the line equalizer will be placed after the transimpedance amplifier; and low power consumption.

First, a new low-voltage low-power high-frequency line equalizer targeted for multi-gigabit short-haul transmission has been proposed. It has been designed in a standard 0.18-µm CMOS technology without the gain-bandwidth product and input range limitations undergone by the conventional degenerated differential pair-based equalizer. Furthermore, it has shown to be more robust against PVT variations. The prototype is designed for targeting 1.25 Gb/s over 50-m long of 1-mm SI-POF with only a 1-V supply voltage. However, the proposed equalizer could be used for higher data rates, reaching 2-Gb/s transmission over 50-m long POF.

The proposed continuous-time equalizer is intended to compensate the low bandwidth of a plastic optical fiber, and it can be used in an adaptive equalizer scheme in response to the possible variations of the characteristics of the fiber. Unlike the degenerated differential pair-based equalizer, in the proposed equalizer (SPEQ), the controls of the gain and the zero are completely decoupled, the fre-quency sensitivity to the common-mode dc voltage is drastically reduced, and the

Fig. 3.34 Measured bandwidth improvement for 10- and 50-m POF



input range is three times higher. Furthermore, the degenerated differential pair-based equalizer is more sensible to process, mismatch, and temperature. The price is a slightly greater input noise, which can be considered irrelevant in this receiver stage, and a higher power consumption, which can be assumed in typical wireline systems, such as home area networks.

It is worth noting that, although continuous-time equalizers, like all continuous-time filters, undergo a strong dependency on the process, voltage and temperature variations, some on-chip tuning schemes can be implemented to automatically correct the deviation of the frequency response of such filters. In our case, the line equalizer will be integrated in an adaptation loop which, although it will be designed to compensate the variations of the characteristics of the fiber, will also serve to correct those deviations.

The main experimental performances as well as the comparison with other reported works are now described and summarized in Table 3.3.

To the knowledge of the authors, there is not much available in the literature to make comparisons. This is because the concrete application for which the equalizer is designed determines its characteristics. It would be unfair to com-pare equalizers designed for different applications so therefore we shall compare the proposed equalizer with others designed to compensate the response of the SI-POF.

A possible figure-of-merit (FOM) would be the following

(3.23)FOM = log

(

BW50m POF(MHz) · Peak (dB) · Technology (µm)

Power (mW) · VoltageSupply (mW)

)

Table 3.3 Summary and comparison with other continuous-time equalizers

aEstimated value; bThe power consumption includes the adaptation loop

[ATE12] [AZN12] [SUN09] Proposed Equalizer

Technology 0.6 μm BiCMOS

0.18 μm CMOS

0.35 μm CMOS

0.18 μm CMOS

Rate (Gb/s) 1.25 1.25 1.0 1.25

Fiber length (m) 50 50 50 50

PD diameter (mm)

0.4 0.8 0.8 0.8

Power (mW) 12a 2a 165b 8.0

Voltage supply (V)

3.3 1.8 3.3 1

Peaking (dB) 9 10 10 16.5

Equalizer BW 750 MHz (20-m POF)

1.1 GHz (10-m POF)

Peaking centered in 500 MHz

1.35 GHz (10-m POF)

700 MHz (50-m POF)

900 MHz (50-m POF)

1.35 GHz (50-m POF)

FOM 1.98 2.65 0.62 2.70

79

In this way, the proposed equalizer provides a FOM of 2.70. So, it provides the best FOMs although [ATE12] uses a smaller PD and a more expensive BiCMOS technology and [AZN12] uses a higher supply voltage. It is important to mention that the adaptation loop is also included in the power consumption of [SUN09]. However, although the same power supply voltage than our equalizer were used, it would still present a lower FOM of 2.29.

Other continuous-time equalizers can be found in Refs. [DON13, TAV10] for short-reach high-speed application through POF, but they have not been included in the comparative analysis as they are designed to compensate the limited fre-quency response of the integrated PD, not the response of the fiber itself either because they use more expensive GI-POF, or because they are used for very short distances so that the response of the POF need not be compensated.

References

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[ATE12] M. Atef, R. Swoboda, H. Zimmermann, 1.25 Gbit/s over 50 m step-index plastic optical fiber using a fully integrated optical receiver with an integrated equalizer. IEEE J. Lightwave Technol. 30(1), 118–122 (2012)

[AZN11] F. Aznar, W. Gaberl, H. Zimmermann, A 0.18 um CMOS transimpedance amplifier with 26 dB dynamic range at 2.5 Gb/s. Microelectron. J. 42(10), 1136–1142 (2011)

[AZN12] F. Aznar, C. Sánchez-Azqueta, S. Celma, B. Calvo, Gigabit receiver over 1-mm SI-POF for home area networks. IEEE J. Lightwave Technol. 30(16), 2668–2674 (2012)

[AZN13] F. Aznar, S. Celma, B. Calvo, CMOS receiver front-ends for gigabit short-range optical communications (Springer, New York, 2013)

[BAB98] J.N. Babanezhad, A 3.3 V analog adaptive line-equalizer for fast ethernet data communication, in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), May 1998, pp. 343–346

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[DON10] Y. Dong, K. Martin, Analog front-end for a 3 Gb/s POF receiver, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), Aug 2010, pp. 197–200

[DON13] Y. Dong, K.W. Martin, A 4-Gbps POF receiver using linear equalizer with multi-shunt-shunt feedbacks in 65-nm CMOS. IEEE Trans. Circ. Syst. II Express Briefs 60(10), 617–621 (2013)

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3.5 Conclusions


[GIM11b] C. Gimeno, C. Aldea, S. Celma, F. Aznar, High-speed CMOS front-end architecture for SI-POF, in Proceedings of 20th International Conference on Plastic Optical Fibers (POF2011), Sept 2011, pp. 437–442

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[HAO10] J. Hao, Z. Yumei, J. Yishu, A low power 3.125 Gbps CMOS analog equalizer for serial links. J. Semiconductors 31(11), 115003 (2010)

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[SUN09] J. Sundermeyer, J. Tan, C. Zerna, Integrated analogue adaptive equalizer for gigabit transmission over standard step index plastic optical fibre (SI-POF), in Proceedings of 22nd LEOS Annual Meeting Conference, Oct 2009, pp. 195–196

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81

The equalization must be robust to channel variations because in a practical trans-mission system, the exact characteristics of the channel are not known a priori and can vary significantly. This is especially important in high-speed communications because changes in temperature, material properties, length, bends, etc. can pro-duce the bandwidth of the channel to change substantially. Therefore, the equalizer must automatically detect and critically compensate for the high frequency chan-nel losses; otherwise, the resulting bit error rate would increase.

This implies the need for implementing an adaptation scheme along with the continuous-time linear equalizer which should be capable of providing an error signal, based on the ideal frequency response, to drive the response of the equal-izer to the required one.

In this chapter, we deal with the design of a low-voltage, low-power, fully bal-anced continuous-time adaptive equalizer that compensates for the limited band-width of SI-POF channels and uses the spectrum-balancing technique to adapt its response to both the possible variations of the characteristics of the fiber, and also to the possible deviations of the response of the line equalizer itself due to pro-cess, voltage and temperature (PVT) variations. However, the presented structures can be extended to other applications where continuous-time adaptive equaliza-tion is needed.

First we will present the proposed adaptation loop and will then focus our atten-tion on the main blocks that make it up. As with Chap. 3, a simple theoretical analy-sis based on a small signal model will be used to study the functionality of the main building blocks. The same approximations used in that chapter will be assumed: transistors characterized by their transconductance and output resistance, no para-sitic components included in the analysis and lumped models for the devices.

An adaptation loop based on two LPFs (proposed by the authors) will be stud-ied in parallel with the one based on a LPF/APF, and compared by simulations in terms of response, power consumption and robustness. We will then choose one

Chapter 4Adaptation Loop


http://dx.doi.org/10.1007/978-3-319-10563-5_3

82 4 Adaptation Loop

filter combination to implement the power comparison on the adaptation loop and will present the experimental verification of the proposed device. Measurement results will be compared with structures previously proposed in literature.

4.1 Design of the Adaptation Loop

Several continuous-time adaptive equalizer topologies for compensating the chan-nel variations have been proposed in the literature. Some require a slicer or a high-gain amplifier to generate sharper rising and falling edges of the signal incoming from the line equalizer which increase the circuit complexity and, mainly, power consumption [CHE10, JOO10, LEE09, LIU09]. To overcome these drawbacks, the adaptation loop of the proposed equalizer is implemented based on the spectrum-balancing technique, which consists of comparing two different frequency ranges of the signal spectrum [LEE06, SUN05]. This solution obviates the need for a high-speed slicer, significantly reducing the complexity of the circuit, power dis-sipation and area consumption.

The block diagram of the proposed continuous-time adaptive equalizer is shown in Fig. 4.1 [GIM13, GIM14a]. The adaptability is obtained by a feedback loop formed by two filters and a power comparator, where the error signal needed to adjust the frequency behavior of the line equalizer is generated. This error sig-nal is integrated to generate a clean dc control voltage, VC, which is feed back to the line equalizer. Because fast slicers are not used, this structure significantly reduces the complexity of the design, and, hence, the area consumption of the sys-tem [LIU04]. In this design a single adaptive loop approach is employed keeping the gain of the equalizer constant.

As shown in Chap. 2, the normalized power spectrum of a random binary sequence is represented by a sinc2 function. For it, the ratio of signal power for any two frequency ranges, P1 and P2, is constant, c, and can be expressed as

(4.1)P2

P1

= c

Fig. 4.1 Block diagram of the proposed adaptive equalizer

http://dx.doi.org/10.1007/978-3-319-10563-5_2

83

By examining the power spectrum derived from the equalizer output, it can be determined whether the data stream is under- or over-compensated and adjust the boost accordingly.

To obtain the powers P1 and P2 the equalized signal is passed through two fil-ters that select the frequency ranges. Both filters drive the filtered equalized signal to the error comparator, as shown in Fig. 4.1. Different filter combinations have been used in literature to implement the power comparison, but Chap. 2 shows that the best alternatives are two LPFs or a LPF and an APF. So, these are going to be the combinations used in this chapter.

To determine the cut-off frequencies of the filters, f1 & f2, the power ratio can be expressed as

where Hi(f ) is the transfer function of each filter.If we have two LPFs (LPF1 and LPF2) with gains Ai and cut-off frequencies fi:

It should be noted that this approximation is valid for cut-off frequencies much lower than the bit rate.

A low power ratio makes the power comparison more inaccurate and a high ratio causes greater power consumption. Using a procedure like the one pre-sented in Chap. 2, a power ratio of c = 6.8 is found suitable to be used in (4.3). Gains A1 = 2.3 and A2 = 1.3 for the LPF1 and LPF2, respectively, provide the power ratio required. Values of f1 = 23.6 MHz and f2 = 471 MHz are obtained for a period of the data bit stream of 800 ps (bit rate of 1.25 Gb/s). Note also that these cut-off frequencies are valid for ideal brick-wall filters. The term brick-wall implies that frequencies smaller than fi pass with a gain Ai, whereas all other fre-quencies are entirely eliminated. Practical filters can only approach a brick-wall response as their complexity, i.e. filter order, is increased. However, in this appli-cation, high order filters are not necessary; in fact they can compromise the sta-bility of the adaptation loop due to the associated phase shift. So, as first order filters are used, their cut-off frequencies are π/2 times lower [CHE10], that is, f1 = 15 MHz and f2 = 300 MHz.

If an LPF and an APF are used, the previous approximation is not longer valid for the APF, but it is still valid for the LPF. In the case of the APF, we use the fact that half of the power spectrum is equal to one half [LEE06]. Therefore

(4.2)P2

P1

=

∫ f20S(f )df

∫ f10S(f )df

=

∫ f20sinc2(f ) · H2

2 (f ) · df∫ f10sinc2(f ) · H2

1 (f ) · df= c

(4.3)P2

P1

=

A22 ·

∫ f20S(f )df

A21 ·

∫ f10S(f )df

≈

A22 · f2 · Tb

A21 · f1 · Tb

=

A22 · f2

A21 · f1

= c

(4.4)P2

P1

=

A22 · ∫

∞

0 S(f )df

A21 · ∫

f10 S(f )df

≈

A22 · 0.5

A21 · f1 · Tb

= c


http://dx.doi.org/10.1007/978-3-319-10563-5_2

http://dx.doi.org/10.1007/978-3-319-10563-5_2


As explained before, a suitable value of c should be chosen to get a good trade-off between accuracy and power consumption. Using a procedure like the one pre-sented in Chap. 2, a power ratio of c = 6.3 is found suitable to be used in (4.4). Therefore, a dc gain of 0 and 8 dB is determined for the APF and LPF, respec-tively, with a cut-off frequency of 130 MHz for the latter for a period of the data bit stream of 800 ps (bit rate of 1.25 Gb/s).

Obviously, real filters have additional poles, but their effects will not be signifi-cant if they are located at frequencies much higher than their cut-off frequencies.

The control signal can be then obtained with the following equation

In this way, when a change in the power of the signal is produced, the feedback loop attempts to maintain (4.5) valid by modifying the control signal, VC, which increases or decreases boosting in the equalizer. Thus, the control signal variation, �VC, for the equalizer is generated by

We have explained the general behavior of the adaptation loop. Our attention now focuses on the specific implementation of each block that makes up the adaptation loop.

4.1.1 Line Equalizer

For the implementation of the continuous-time adaptive equalizer we have chosen to use the architecture proposed in the previous chapter as a line equalizer: the SPEQ, see Figs. 3.5 and 3.6. The reason is that it presents not only a good trade-off between gain-bandwidth product, noise and input dynamic range but also a high common-mode rejection ration (CMRR), which will facilitate the comparison between powers, and is robust to PVT variations.

4.1.2 Loop Filters

As justified in Sect. 2.4, to obtain the different ranges of the spectrum of the sig-nal, LPF/LPF or LPF/APF combinations are used.

To implement the filters, simple Gm-C topologies could be used. However, a partial positive feedback topology, similar to that of the line equalizer (with k = 0.5), is chosen to implement both filters to reduce the variations in the com-mon-mode of the signal and perform the comparison properly [GIM14a]. Block diagrams of both filters are shown in Fig. 4.2. By using the same topology for the filters as was used for the equalizer, the design will have great modularity, mak-ing the matching of the different stages easier, without significantly increasing the

(4.5)VC ∝ P1 · c− P2

(4.6)�VC ∝ �P1 · c−�P2

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complexity of the circuits. We used an APF instead of a direct connection for two reasons: the APF provides the same phase delay between the output signal of the equalizer and the input signal of the comparator as the LPF branch, and also works as a buffer to minimize the effect on the output signal of the gate capacitances of the comparator input transistors.

As we did with the line equalizer, a transistor working in common-source topology and biased with a resistance is used to implement the transconductors to maintain the low-voltage and high-frequency operation of the system; metal-insu-lator-metal (MIM) integrated capacitors are used to implement the required capac-itors. The transistor level topologies of the proposed filters are shown in Fig. 4.3. Assuming ideal transistors, characterized by their transconductances, gmiLP/AP, and being RiLP/AP the equivalent resistance at their drain nodes, the expressions for the differential and common-mode gain for the LPF are

For the all-pass filter

(4.7)

ADLPF (s) =V+

OLP− V−

OLP

V+

O − V−

O

=

R1LP · R2LP · gm1LP · gm2LP

1− R1LP · k · gm2LP·

1

1+ s CLP ·R1LP1−R1LP ·k·gm2LP

(4.8)

ACLPF (s) =2 · V+

OLP

V+

O + V−

O

=

R1LP · R2LP · gm1LP · gm2LP

1+ R1LP · k · gm2LP·

1

1+ s CLP ·R1LP1+R1LP ·k·gm2LP

(4.9)ADAPF(s) =

V+

OAP− V−

OAP

V+

O − V−

O

=

R1AP · R2AP · gm1AP · gm2AP

1− R1AP · k · gm2AP

(4.10)ACLPF (s) =

2 · V+

OAP

V+

O + V−

O

=

R1AP · R2AP · gm1AP · gm2AP

1+ R1AP · k · gm2AP

Fig. 4.2 Block diagram of the a LPF and b APF



In all the cases, the effect of the parasitic elements has been disregard.It can be directly obtained from (4.7), (4.8), (4.9) and (4.10) that the dc CMRR

for the filters is

According to (4.11), by correctly designing the filters, a high CMRR can be achieved so as to ensure the same common-mode for both signals to perform the comparison of powers properly. Note that the CMRR expression for both filters is the same as that shown in (3.36) for the SPEQ.

Figure 4.4 shows the frequency responses of the filters in the LPF/LPF con-figuration. LPF1 and LPF2 have differential gains of 7.2 and 2.3 dB and cut-off

(4.11)CMRR =

ADLPF/APF(s = 0)

ACLPF/APF(s = 0)

=

1+ R1LP/AP · k · gm2LP/AP

1− R1LP/AP · k · gm2LP/AP

Fig. 4.3 Transistor level topology of the a LPF and b APF

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frequencies of 15 and 300 MHz, respectively. The common mode gain is −8.9 dB for both filters. Capacitances of C1LP = 6.2 pF and C2LP = 0.26 pF have been used in the LPF1 and LPF2, respectively.

Figure 4.5 shows the frequency responses of the filters in the LPF/APF configu-ration. LPF and APF have differential gains of 7.4 and 0.5 dB and cut-off frequen-cies of 130 MHz and 1.7 GHz, respectively. The common-mode gains are −5.5 and −6 dB, respectively. A capacitance of CLP = 1.5 pF has been used in the LPF.

4.1.3 Power Comparator

It is widely known that the power or root mean square (rms) value of a signal can be obtained by squaring either its voltage or current component. For example, in [YIN05] a bipolar junction transistor (BJT) translinear loop as the core cell for an rms detector has been proposed, whereas in [LI10] the quadratic characteristics of MOS transistors are exploited instead. Higher complexity, area consumption

Fig. 4.4 Frequency responses of the loop filers for the LPF/LPF configuration: a differential, b common mode

Fig. 4.5 Frequency responses of the loop filers for the LPF/APF configuration: a differential, b common mode



and voltage supply requirements of the full power detectors, make them diffi-cult to implement along with the adaptive equalizers. Nevertheless, the quadratic approach to obtain an expression proportional to the signal power is still valid for the power comparator design.

In literature, two filters followed by two rectifiers and an error amplifier are reported to obtain the power comparison. Rectifiers are usually based on differen-tial pairs with their output voltage at the common-source node [LEE06, SUN05]. This configuration is not a true power detector and also suffers from a small output swing at high frequency, mainly due to the parasitic capacitance of the common-source node. Therefore, these rectifiers need to use an error amplifier with high gain and low offset which makes the design difficult and increases the power con-sumption around a few mW [SUN05].

As an alternative to the use of error amplifiers, a voltage-current converter (V/I) has also been used. This facilitates the integration of the error signal by a simple grounded capacitor; however, proposed V/I converters need at least 1.6-V supply for 0.18-µm CMOS technology [CHE10].

We propose a new compact design of a power comparator suitable for 1-V sup-ply voltage. It is based on the use of the quadratic voltage-current MOS transistor characteristics of the strong inversion saturation region [GUE14]. The conceptual scheme of the adaptive equalizer with the proposed power comparator is shown in Fig. 4.6. The slicer has been represented dashed in the figure as the proposed com-parator can be used for both adaptation loop alternatives (with and without slicer). The use of squarers instead of rectifiers has the advantage of providing an output proportional to the power of the input signal. Furthermore, the V/I converter can be eliminated since the squarer itself is a V/I converter. This way, the power con-sumption is reduced below 1 mW.

The current-steering technique used to implement the power comparator reported in [HOO07, LEE06], provides a wide output swing of the error signal, which relaxes

Fig. 4.6 Conceptual scheme of the adaptive equalizers: a conventional and b squarer-based adaptation loop

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the gain specification for the error amplifier to adjust the control signal, VC, to a level required by the line equalizer. However, as the following shows, in the common dif-ferential pair, an overdrive voltage is needed for each stacked transistor to operate in saturation, so, the input voltage headroom reduces to VDD − 3 · VDsat, which, for low-voltage applications, severely limits the input voltage swing.

The proposed power comparator is based on the flipped-voltage follower differ-ential pair (FVFDP) squarer [CAR05] shown in the dashed box in Fig. 4.7, where transistors M1 and M2 utilize the exclusive characteristics of the coupled differen-tial pair to detect the signal power thanks to the quadratic current-voltage response of MOS transistors working in the saturation region. Unlike the structures based on the conventional differential pair [SUN05], the FVFDP can be biased with a supply voltage of only 1 V, without severely degrading the input range available.

Since a current source fixes a constant drain-source current through M4, which is Ib, the total current of the differential pair can be obtained by means of M3 as

with

where VTHn is the threshold voltage of the NMOS transistor, and the rest of the parameters have their usual meaning.

The gate voltages, V+

in and V−

in, at each input transistor in the differential pairs correspond to the sum of the common-mode voltage level, VCM, and the differ-ential part of the input signal, +Vin/2 and −Vin/2, respectively. If the channel dimension ratios, W/L, for M1 and M2 in the differential pairs are set equal, then Eq. (4.12) can be expressed as

(4.12)I3 = I1 + I2 + Ib

(4.13)I1,2 =1

2· µn · COX ·

W

L·

(

VGS1,2 − VTHn

)2

(4.14)I3 = µn · COX ·

W

L·

[

(VCM − VTHn − VS)2+

V2in

4

]

+ Ib

Fig. 4.7 Schematics of the flipped-voltage follower differential pair (FVFDP) based power comparator



Clearly from (4.14) the total current of each differential pair contains the signal power through the term V2

in. As each FVFDP detects the powers P1 and P2 of the signals Vin1 and Vin2, respectively, the comparison between them can be performed by means of their difference, that is

where Iout denotes the error current. Since the power is obtained in the current domain, Eq. (4.15) can be implemented straightforward using a simple current mirror technique formed by transistors M5–M6 as shown in Fig. 4.7. The output current Iout can be expressed as

where Vin1 = V+

in1 − V−

in1 and Vin2 = V+

in2 − V−

in2 correspond to the differential out-put voltage of the filters.

To generate the error voltage, Vout, the current Iout is integrated by a grounded capacitor, Cint, to obtain a clean dc output voltage,

The voltage Vout is amplified and level shifted with a two-stage common-source amplifier shown in Fig. 4.8 to achieve the voltage level required by the loop con-trol. The output control voltage, VC, is carried to the line equalizer.

To make the circuit immune to common-mode level variations, both FVFDP power detectors must be biased with the same voltage level Vb. We have chosen to set it to a common-level between V+

in1 and V−

in2, so

This sets an equal common-source node voltage, VS, in both blocks, which allows for subsequent elimination along with the common-mode term, VCM. The simplest way to generate this voltage is by means of a resistive divider.

The input voltage swing is determined by the saturation condition of the tran-sistors M1–M2. Since the drain of M1 is connected to VDD, saturation is always sat-isfied for the maximum differential input voltage. On the other hand, the minimum differential input voltage is restricted to

(4.15)Iout ∼ P1 − P2

(4.16)Iout = Io1 − Io2 =1

4· µn · COX ·

W

L·

[

V2in1 − V2

in2

]

(4.17)Vout =1

4· µn · COX ·

W

L·

1

Cint

∫

[

V2in1(t)− V2

in2(t)

]

dt

(4.18)Vb =V+

in1 + V−

in2

2

(4.19)Vin,DM

∣

∣

min= VTH1,2 + VDSat3

Fig. 4.8 Level-shifter amplifier schematics

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where VTH1,2 is the threshold voltage of transistors M1 – M2 and VDSat3

= VGS3 − VTH3 is the saturation drain-source voltage of M3.Therefore, the input voltage swing for each flipped-voltage differential pair in

Fig. 4.7 is

The input swing for an ordinary differential pair is described by

where VDsatP is the overdrive voltage for the PMOS transistors connected to the

drain of the input pair.The input voltage swing for the FVFDP is therefore bigger than the standard

power comparator based on the current-steering technique, thereby overcoming the low-voltage limitation. Additionally, as the FVFDP structure can operate with very low bias currents, we have set Ib to 10 μA; so, the power dissipation of the comparator is greatly reduced.

The proposed power comparator has been implemented in a standard 0.18-μm CMOS technology with a single supply voltage of 1 V. The capacitance used for the integrator is Cint = 7 pF. To test it, Vin2 with different powers, −13.9 and −9.5 dBm, is switched at the input terminal of the power comparator, while the power of Vin1 is kept constant to −9.5 dBm (Fig. 4.9). Therefore, P1 > P2 from 0 to 1 μs and P1 = P2 from 1 to 2 μs, which generates the output voltage shown in Fig. 4.10. Figure 4.11 shows the output voltage, Vout, versus the power difference of the input signals for different frequencies. Only 1.82 % variation is obtained between the minimum (10 MHz) and maximum frequencies (5 GHz) of the NRZ bit streams.

The simulation results are summarized and compared with the differential pair-based power comparator [SUN05] in Table 4.1, where the performance parameters of the latter have been simulated in the same technology as the proposed struc-ture and fed with 1.8 V, since it was unable to operate at 1 V. It can be seen that the proposed power comparator greatly reduces the errors in the output signal due to the input common-mode variations to 1.28 % in the worst case, with a lower power consumption and lower input noise.

(4.20)VTH1,2 + VDSat3≤ Vin ≤ VDD

(4.21)VTH + VDSat≤ Vin ≤ VDD − VDsatP

Fig. 4.9 Simulated eye diagrams for bitstream at 1.25 Gb/s of a −13.9 dBm and b −9.5 dBm



4.1.4 Complete Continuous-Time Adaptive Equalizer

The proposed continuous-time adaptive equalizers have been designed in a stand-ard 0.18-µm CMOS technology from UMC with a single supply voltage of 1 V. Simulations have been carried out using Spectre with a BSIM3v3.2 level 53 tran-sistor model. The technology has 1 poly and 6 metal layers; the capacitors have been fabricated with metal-insulator-metal (MIM) structures which have a capaci-tance per area of 1 fF/µm2 and are implemented between metal 5 and metal 6; and the resistors have been implemented with high resistivity polysilicon (HRP)

Fig. 4.10 Time response of the power comparator

Fig. 4.11 Output voltage versus input power difference for different frequencies of a NRZ bitstream

Table 4.1 Performance comparison with the power comparator based on the conventional dif-ferential pair

Parameter Differential pair Proposed power comparator

Supply voltage (V) 1.8 1

Comparison error (%) 2.78 1.28

Power consumption 1.1 mW 650 µW

CMRR (dB) 48.3 44.2

Input noise (µV/Hz1/2) 43.26 41.56

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layers which have 1,039 Ω/sq. In the same way than in Chap. 3, reliable electri-cal models with passive devices are employed to model the frequency response of a Mitsubishi GH SI-POF for different lengths. See Appendix A for more information.

To better illustrate the behaviour of the proposed adaptive equalizers, Fig. 4.12 shows an example of the time response at the different stages of the adaptive equalizer. A PRBS of 231 − 1 maximum length NRZ data stream at 1.25 Gb/s is used. The simulation shows the behavior of the adaptive equalizer for a variation from short (10 m) to long length (50 m) at 1.5 µs and from long to short at 3 µs. Obviously, in practice it is unlikely that these sudden length changes occur in the fiber, but this simulation allows us to check the rapid response of the equalizer.

Both proposed adaptive equalizers present the same results in terms of band-width (1.35 GHz for fiber lengths between 10- and 50-m POF) and rms input noise (0.99 mV). Furthermore, they present very similar results in terms of power con-sumption (13.7 mW the LPF/LPF adaptive equalizer versus 14.3 mW the LPF/APF adaptive equalizer). Some considerations regarding process, voltage and temperature (PVT) variations must be made. The zero and gain boosting of the line equalizer may suffer PVT variations; however, the control loop, that adapts the equalization to any cable length, in the same way performs the compensation against PVT variations. But these variations can also affect the adaptation loop blocks. First, corner analysis is going to be performed. Figures 4.13 and 4.14 show the eye diagram at stationary conditions after equalization of 50- and 10-m POF,

Fig. 4.12 Example of the transient response at the different building blocks of the adaptive equalizer implemented with a LPF/APF combination


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Fig. 4.13 Eye diagrams after 50-m POF equalization with a 1.25 Gb/s NRZ PRBS 231-1 for the adaptation loop including LPF/LPF and LPF/APF for a typical behavior, b slow n and slow p (ss), c fast n and fast p (ff), d slow n and fast p (snfp), and e fast n and slow p (fnsp)

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Fig. 4.14 Eye diagrams after 10-m POF equalization with a 1.25 Gb/s NRZ PRBS 231-1 for the adaptation loop including LPF/LPF and LPF/APF for a typical behavior, b slow n and slow p (ss), c fast n and fast p (ff), d slow n and fast p (snfp), and e fast n and slow p (fnsp)



respectively, at the different corners. Table 4.2 shows the results of the minimum, typical, and maximum values of ISI and rms deterministic jitter for stationary con-ditions for 50- and 10-m POF (see Sect. 3.3 for a definition of the parameters). So, it can be seen that, although for 10 m both adaptation loops present similar results in terms of ISI and rms deterministic jitter, for 50-m POF the LPF/APF configura-tion presents poorer results.

Figures 4.15 and 4.16 show the eye diagrams at stationary conditions after equalization of 50- and 10-m POF, respectively, for two extreme temperatures.

Figures 4.17 and 4.18 show how the eye diagram at stationary conditions after equalization of 50- and 10-m POF changes when the supply voltage experi-ences ±10 % of variation.

Table 4.3 shows the results of the minimum, typical, and maximum values of ISI and rms deterministic jitter for stationary conditions for 50- and 10-m POF. It can be seen that, although for 10-m POF both adaptation loops present similar results in terms of ISI and jitter, for 50-m POF the LPF/APF configuration presents worse results.

Table 4.2 Corner analysis of the two proposed adaptive equalizers

LPF/LPF adaptive equalizer LPF/APF adaptive equalizerParameter Min Typ Max Min Typ Max

Jitter for 50-m POF (%) 0.8 2.4 3.7 1.4 3.7 13.9

Jitter for 10-m POF (%) 1.2 2.9 3.5 1.5 3.2 3.7

ISI for 50-m POF 0.22 0.67 0.93 0.21 1.10 2.09

ISI for 10-m POF 0.32 0.62 0.75 0.28 0.74 0.74

Fig. 4.15 Eye diagrams with a 1.25 Gb/s NRZ PRBS 231-1 for the adaptation loop including LPF/LPF and LPF/APF for a −40 ºC, b 120 ºC after 50-m POF equalization

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Worth noting is that by using two LPF in the control loop it becomes less sen-sitive to PVT variations. However, the performed simulations do not take into account a good matching layout design between the filter transistors. Therefore, as the matching in the LPF/LPF adaptive equalizer is simpler, the results will even improve.

Fig. 4.16 Eye diagrams with a 1.25 Gb/s NRZ PRBS 231-1 for the adaptation loop including LPF/LPF and LPF/APF for a −40 ºC, b 120 ºC after 10-m POF equalization

Fig. 4.17 Eye diagrams with a 1.25 Gb/s NRZ PRBS 231-1 for the LPF/LPF and LPF/APF con-figuration for a supply voltage of a 1.1 V, b 0.9 V after 50-m POF equalization



4.2 Experimental Measurements

In this section, the experimental set-up and results of the proposed continuous-time adaptive equalizer implemented with two LPFs to obtain the power compari-son is described.

To test the proposed adaptive equalizer, the implemented prototype includes the adaptive equalizer with a 50-Ω input resistance, and a 50-Ω output driver (see Fig. 3.21). The main assignment of the output driver is to drive 50-Ω loads with high output swing. Some external controls for the adaptive equalizer have been included in the test bench (Fig. 4.19).

Fig. 4.18 Eye diagrams with a 1.25 Gb/s NRZ PRBS 231-1 for the LPF/LPF and LPF/APF con-figuration for a supply voltage of a 1.1 V, b 0.9 V after 10-m POF equalization

Table 4.3 Jitter and ISI summary for different temperatures and supply voltages

Parameter LPF/LPF adaptive equalizer

LPF/APF adaptive equalizer

Min Typ Max Min Typ Max

Temperature variation

Jitter for 50-m POF (%) 1.4 2.4 18.6 2.1 3.7 45.9

Jitter for 10-m POF (%) 0.5 2.9 4.4 0.6 3.2 4.5

ISI for 50-m POF 0.22 0.67 1.8 0.52 1.10 2.28

ISI for 10-m POF 0.16 0.62 0.93 0.19 0.74 0.97

Supply voltage variation

Jitter for 50-m POF (%) 1.4 2.4 2.4 2.6 3.7 4.32

Jitter for 10-m POF (%) 2.9 2.9 4.4 2.27 3.2 4.6

ISI for 50-m POF 0.35 0.67 0.67 0.91 1.10 1.10

ISI for 10-m POF 0.62 0.62 0.91 0.37 0.74 1.39

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The same output driver that was used in the previous chapter for performing experimental measurements [AZN11] has been used. A higher supply voltage (1.8 V) is used to increase the output signal levels to a value suitable for experi-mental measurements and to facilitate the design of the driver.

4.2.1 Layout

The correct operation of the proposed design has been confirmed by transistor level and post-layout simulations.

The same layout strategies described in Chap. 3 (symmetrical paths, ESD pro-tection, adequate PADs distribution, guard rings, etc.) have been used to design the layout of the proposed adaptive equalizer to ensure the correct operation of the circuits in high-frequency and low-voltage conditions.

Figure 4.20 shows the layout and microphotograph of the design, and Fig. 4.21a microphotograph of its active area, over which the location of its main blocks has been superimposed. The dimensions of the full chip are 1.182 · 0.808 mm2, whereas the active area is 0.015 mm2, where 0.006 mm2 corre-spond to the line equalizer, 0.005 mm2 to the loop filters, 0.005 mm2 to the power comparator, and 0.004 mm2 to the output driver.

4.2.2 Electrical Characterization

To perform some electrical characterization, the prototype was included in a set-up like the one used in Chap. 3, shown in Fig. 3.25. A Rohde and Schwarz ZVL6 vector network analyzer (9 kHz–6 GHz) has been used to properly characterize

Fig. 4.19 Block diagram of the fabricated adaptive equalizer


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Fig. 4.21 Microphotograph of the active area of the chip (0.015 mm2)

Fig. 4.20 a Layout and b microphotograph of the chip for testing the adaptive equalizer

the proposed design. To minimize parasitic capacitances of the package, the pro-totype includes the bare die directly fitted on the PCB (see Fig. 4.22). 18-GHz SMA connectors were also used in the signal lines. The output signal lines include 100-nF decoupling ceramic capacitors and the supply lines are noise-filtered by using grounded ceramic capacitors. To generate balanced signals, Prodyn Baluns (BIB-100G) with a bandwidth from 250 kHz to 10 GHz have been used both at the input and output paths. A Bias-TEE circuit from Mini-Circuits (ZFBT-4R2G+, 10-4 200 MHz) has been used to add a dc voltage to the RF input.

To make the adaptation loop work correctly, the POF behavior should be included. Thus, the POF electrical emulator presented in Chap. 3 (Fig. 3.24) has been included in the signal path. A complete calibration process for a 2-port sys-tem was also performed using a SOLT kit to define the reference plane to measure the DUT. A de-embedding circuit is also included in the chip to obtain the real fre-quency performance of the DUT.

The maximum whole circuit power consumption is 82.3 mW, where 13.7 mW corresponds to the adaptive equalizer, and 68.7 mW to the output driver.

To show the correct operation of the prototype for different POF lengths, Fig. 4.23 shows the frequency response at the output of the POF electrical

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emulator and at the output of the IC after data treatment. It is noteworthy that the spectral bandwidth of the received signal can be enhanced from 100 MHz to 1.35 GHz and from 300 to 1.35 GHz for 50- and 10-m POF, respectively. This important result validates the effectiveness of the proposed architecture.

4.2.3 Time-Domain Characterization

Time-domain characterization is also needed. The POF electrical emulator (Fig. 3.24) is also used.

The set-up is shown in Fig. 4.24. A serial bit error rate tester (BERT) N4096A generates the electrical bit pattern that passes through the POF emulator to the prototype. Eye diagrams are obtained by using an Agilent 86100C digital commu-nications analyzer (DCA).

Fig. 4.22 Printed circuit board (PCB) of the adaptive equalizer chip

Fig. 4.23 Measured bandwidth improvement for 10- and 50-m POF


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A bit rate of 1.25 Gb/s with an NRZ PRBS (231-1) pattern is used for the char-acterization. Figure 4.25a and c show the eye diagrams for 50-m and 10-m POF, respectively without equalization, that is, the results including the POF electrical emulator with the 50-Ω input resistor of the measurement equipment. From the outcome of the test, we can see that the eye diagrams are almost closed due to the limited bandwidth available (~100 MHz for 50-m and 300 MHz for 10-m POF). In Fig. 4.25b and d, the obtained equalized eye diagrams during stationary conditions

Fig. 4.24 Block diagram of the time-domain measurement set-up

Fig. 4.25 Eye diagrams for 1.25 Gb/s NRZ PRBS 231-1: a unequalized and b equalized through 50-m POF; c unequalized and d equalized through 10-m POF

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are shown for 50- and 10-m POF, respectively. So, the proposed adaptive equalizer is able to adapt its response to that of the fiber generating a good quality eye dia-gram for any POF length between 10 and 50 m.

The measured rms deterministic jitter at the output of the system is 5.2 % for 10-m POF and 4.4 % for 50-m POF. The measured ISI is 1.28 for 10-m POF and 1.37 for 50-m POF. So, it can be seen that the output signal is very independent from the frequency characteristics of the input.

4.3 Conclusions

This chapter has covered an in-depth design analysis and experimental charac-terization of the adaptive equalizer that compensates for the limited bandwidth of SI-POF channels and uses the spectrum-balancing technique not only to adapt its response to the possible variations of the characteristics of the fiber, but also to the possible variations of the response of the line equalizer itself due to process, volt-age and temperature. We will dedicate this section to summarize the main results and to perform a comparison with similar recently reported adaptive equalizers in order to underline the advantages of the one proposed.

The required performances are: high speed, quantified by the bandwidth of the fiber-equalizer combination, low-voltage operation, and low-power consumption.

First, the main blocks that constitute the adaptation loop have been presented. They have been designed in a standard 0.18-µm CMOS technology with only 1 V of supply voltage.

Some filters have been proposed to implement the power spectrum compari-son. They use a cross configuration to obtain high CMRR without sacrificing input dynamic range or gain-bandwidth product. Moreover, as they have the same struc-ture as the line equalizer, the layout can have good matching and modularity.

A CMOS differential power comparator has also been presented in this chapter. It is a modification of the current-steering technique based on the flipped voltage follower as the main power detector cell, which makes it suitable for low-voltage, low-power, high-frequency applications. Its main advantages are higher input range, lower power dissipation (650 µW), and that the errors in the output signal due to the input common-mode variations are greatly reduced since only 1.28 % error is obtained for the worst case.

With the previously mentioned blocks, the whole adaptive equalizer has been implemented. Two filter combinations have been studied in parallel to implement the power comparison: LPF/LPF (proposed by the authors) and LPF/APF. They provide similar results in terms of power, bandwidth, and noise. However, the pro-posed two LPF combination is more robust in terms of PVT variations.

So, an adaptive equalizer with the spectrum-balancing technique as the decision mechanism using two LPFs to provide the power comparison has been integrated and tested. The main experimental performances as well as the comparison with other reported works are now described and summarized in Table 4.4.



As mentioned in Chap. 3, to the knowledge of the authors, there is little available in the literature to compare with, as the concrete application determines the required characteristics of the equalizer. If we want to include the adaptation loop in the com-parison, the number of papers we can compare our work with is even less. On the other hand, they do not provide too many data we can include in the FOM.

To compare with other solutions, a possible figure-of-merit (FOM) would be the following:

The proposed adaptive equalizer provides the best FOM, 2.4, while [AZN12] and [SUN09] provide a FOM of 2.2 and 0.8, respectively. Moreover, we use the lowest supply voltage which seriously complicates the design. Although it can-not be directly compared, according to the results presented in Sect. 4.1.4, the use of LPF/LPF instead of a LPF/APF to implement the adaptation loop, makes our design more robust against PVT variations.

The proposed equalizer automatically detects and compensates the losses and variations from the ideality from the signal at the output of the equalizer that affects its frequency behavior. The proposed architecture has been studied in depth.

References

[AZN11] F. Aznar, W. Gaberl, H. Zimmermann, A 0.18 um CMOS transimpedance amplifier with 26 dB dynamic range at 2.5 Gb/s. Microelectron. J. 42(10), 1136–1142 (2011)

[AZN12] F. Aznar, C. Sánchez-Azqueta, S. Celma, B. Calvo, Gigabit receiver over 1-mm SI-POF for home area networks. IEEE J. Lightwave Technol. 30(16), 2668–2674 (2012)

[CAR05] R.G. Carvajal, J. Ramírez-Angulo, A.J. López-Martín, A. Torralba, J.A.G. Galán, A. Carlosena, F.M. Chavero, The flipped voltage follower: a useful cell for low-volt-age low-power circuit design. IEEE Trans. Circuits Syst. I Regul. Pap. 52(7), 1276–1291 (2005)

(4.22)FOM = log

(

Bit Rate (Mb/s) · Peaking (dB) · Technology (µm)

Power (mW) · Voltage Supply (V)

)

Table 4.4 Summary and comparison with other works

*Estimated value

[AZN12] [SUN09] Proposed adaptive equalizer

Technology (μm CMOS) 0.18 0.35 0.18

Rate (Gb/s) 1.25 1.0 1.25

Maximum fiber length (m) 50 50 50

Power (mW) 7.5* 165 13.7

Voltage supply (V) 1.8 3.3 1

Peaking (dB) 10 10 16.5

FOM 2.2 0.8 2.4

http://dx.doi.org/10.1007/978-3-319-10563-5_3

105

[CHE10] K.-H. Cheng, Y.-C. Tsai, Y.-H. Wu, Y.-F. Lin, A 5-Gb/s inductorless CMOS adaptive equalizer for PCI express generation II applications. IEEE Trans. Circuits Syst. II Express Briefs 57(5), 324–328 (2010)

[GIM13] C. Gimeno, E. Guerrero, C. Aldea, S. Celma, A 2.5 Gb/s low-voltage CMOS fully-differential adaptive equalizer, in Proceedings of 2013 SPIE Microtechnologies Conference (SPIE 2013), (April 2013), pp. 876402-1–876402-8

[GIM14a] C. Gimeno, E. Guerrero, S. Celma, C. Aldea, Reliable CMOS adaptive equalizer for short-haul optical networks. Microelectron. Reliab. 54(1), 110–118 (2014)

[GUE14] E. Guerrero, C. Gimeno, C. Sánchez-Azqueta, S. Celma, Power comparator for continuous-time adaptive equalization in ethernet-based instrumentation. Meas. Sci. Technol. 25(8), 087002 (1–4) (2014)

[HOO07] D. Hong, S. Saberi, K.-T. Cheng, C.P. Yue, A two-tone test method for continuous-time adaptive equalizers, in Proceedings in Europe Conference and Exhibition of Design, Automation and Test (DATE07), (April 2007), pp. 1–6

[JOO10] H.-Y. Joo, L.-S. Kim, A data-pattern-tolerant adaptive equalizer using the spectrum balancing method. IEEE Trans. Circuits Syst. II Express Briefs 57(3), 228–232 (2010)

[LEE06] J. Lee, A 20 Gb/s adaptive equalizer in 0.13 µm CMOS technology, in IEEE International Solid-State Circuits Conference (ISSCC), (February 2006), pp. 273–282

[LEE09] D. Lee, J. Han, G. Han, S.M. Park, 10 Gbit/s 0.0065 mm2 6 mW analogue adaptive equalizer utilising negative capacitance, in IEEE International Solid-State Circuits Conference (ISSCC), (February 2009), p. 190

[LI10] C. Li, F. Gong, P. Wang, A low-power ultra wideband CMOS power detector with an embedded amplifier. IEEE Trans. Instrum. Meas. 59(12), 3270–3278 (2010)

[LIU04] J. Liu, X. Lin, Equalization in high-speed communication systems. IEEE Circuits Syst. Mag. 4(2), 4–17 (2004)

[LIU09] H. Liu, I. Mohammed, Y. Fan, M. Morgan, J. Liu, L. Hao, An HDMI cable equal-izer with self-generated energy ratio adaptation scheme. IEEE Trans. Circuits Syst. II Express Briefs 56(7), 595–599 (2009)

[SUN05] R. Sun, A low-power 20-Gb/s continuous-time adaptive passive equalizer. Thesis, B.S. Tsinghua University 1999, December 2005

[SUN09] J. Sundermeyer, C. Zerna, J. Tan, Integrated analogue adaptive equalizer for gigabit transmission over standard step index plastic optical fibre (SI-POF), in Proceedings of 22nd LEOS Annual Meeting Conference (December 2009)

[YIN05] Q. Yin, W.R. Eisenstadt, R.M. Fox, T. Zhang, A translinear RMS detector for embed-ded test of RF ICs. IEEE Trans. Instrum. Meas. 54(5), 1708–1714 (2005)

References

107

Short-range optical communications is the most promising solution to achieve gigabit transmission in single-user applications. Step-index polymer optical fiber (SI-POF) is an attractive transmission medium because of its high mechanical resilience, low cost, and ease of installation and maintenance, among other advan-tages [GIM11].

Standard 1-mm core SI-POF and CMOS technology has been proposed as a cost-effective combination against other wireless and wireline solutions. It is already used in industries [KAM01, KAM02], the automotive sector, or low-cost home area networks (HANs) at speeds up to 100 Mb/s. In fact, the goal set by some operators is to outperform copper-based and all-radio-based solutions in the future [KOO11].

In particular, this approach is very attractive for in-home networks due to an overall ease of installation and maintenance, which can be carried out even by do-it-yourself installers. However, manipulation requires eye-safety operation that limits the highest optical power given out by the laser depending on several factors, such as protective case, exposure time or numerical aperture [IEC07]. Thus, the sensitivity of the receiver becomes a very stringent parameter due to the losses of standard POF and other penalty sources. However, the design of the POF receiver targeting a sensitivity compatible with eye-safe laser power is a real challenge.

Receivers with adaptive gain and equalization are needed to compensate the band-limited frequency response caused by fiber losses (0.14 dB/m at 650 nm). The bandwidth of the fiber depends on its length (∼40 MHz · 100 m) and other parameters such as temperature, connectors, bends, etc. [SÄC05]. Moreover, to efficiently detect the light transmitted along a cost-effective SI-POF, characterized by a large core diameter, the designed CMOS receiver must deal with a large-area photodiode, which results in a high photodiode capacitance.

Chapter 5Receiver Front-End for 1.25-Gb/s SI-POF


108 5 Receiver Front-End for 1.25-Gb/s SI-POF

Following these motivations, a novel CMOS receiver front-end has been designed, fabricated and verified for short-range optical communications over 1-mm SI-POF channels. First we will present the proposed receiver front-end and we will focus our attention on the main blocks that make it up. Then, we will present the experimental verification of the fabricated prototype. Measurement results will be compared with previously proposed structures in literature. Finally, main conclusions will be drawn.

5.1 Receiver Front-End Architecture

In this chapter, a fully integrated low-voltage low-power receiver front-end suita-ble for home and factory networks at 1.25 Gb/s through 50-m long 1-mm diameter SI-POF is presented [SAN14]. Figure 5.1 shows the block diagram.

The photodiode is a large (0.8-mm diameter) off-chip silicon PIN photodiode (PD). A dummy PD has also been used, where the light has been blocked out. In this way, the influence of the dark current can be cancelled. Thus, the signal is pro-cessed in a balanced way improving immunity against power supply, dc offset and common-mode noise.

A transimpedance amplifier (TIA) converts the output current of the PD into a voltage. The design of this stage of the receiver is crucial to achieve good per-formance in sensitivity and speed as the noise generated in this block will be amplified in subsequent stages and its input resistance must deal with the large photodiode capacitance, CPD. An automatic gain control provides a control voltage that adjusts the input-output response of the transimpedance amplifier in function of the amplitude of the signal.

A continuous-time adaptive equalizer is used because its operation is independ-ent of the clock and data recovery circuit (CDR) and it is suitable for low-power, high-speed applications, as it has already been shown in previous chapters. An adaptation loop at the adaptive equalizer modifies the position of the zero to adjust its response to the fiber, achieving a flat output over the bandwidth of interest.

Fig. 5.1 Optical receiver block diagram

109

A PLL-based CDR is included whose phase detector eliminates the need of sampling the data close to their transitions at the locked state, minimizing the per-nicious effect that metastability has on the performance of the system.

5.1.1 Transimpedance Amplifier

The transimpedance amplifier is the link between the PD and the rest of the receiver. It converts the photogenerated current by the PD into an output voltage. The design conditions for a good preamplifier are high transresistance (TR), wide bandwidth (BW), low input referred noise (I2N ,IN), and reduced power consumption [AZN13].

First, as the target of the TIA is to convert the input current into a voltage, let us introduce the simplest current-to-voltage (I-V) converter circuit: a passive resis-tive load (RF) as shown in Fig. 5.2. Its small signal model is shown in Fig. 5.2b, where the thermal noise generated by RF is included. The main performances of such a circuit can be directly derived

where K is the Boltzmann’s constant, T is the temperature and CPD is the photodi-ode capacitance.

Thus, supposing that thermal noise from the resistor IN ,RF is dominant over noise from the PD, IN ,PD, the transimpedance and the noise are governed by the resistor RF, while the bandwidth is limited by the pole associated to photodiode capacitance CPD and resistor RF [RAZ03]. Hence, there is an inherent trade-off between the bandwidth and noise that is independent of RF, as shown by the fol-lowing equation

(5.1)TR = RF

(5.2)BW =

1

CPD · RF

(5.3)I2N ,IN = I2N ,PD + I2N ,RF ≈ I2N ,RF =

4 · K · T

RF

(5.4)BW

I2N ,IN

=

1

4 · K · T · CPD

Fig. 5.2 Simple I-V conversion by using a resistor RF: a circuit and b equivalent model



This means that poor noise performance is expected to attain high BW and this dependence can only be minimized by reducing the capacitance of the photodiode. However, this is one of the critical parameters in our circuit: it has an enormous value, about 3 pF.

Therefore, this suggests the use of other improved approaches to perform the I-V conversion, such as shunt feedback or current mode TIAs [AZN13], which relax this trade-off.

The shunt feedback TIA, which is the most popular structure of TIA, is formed by an inverting amplifier and a feedback resistor, as illustrated in Fig. 5.3.

Let us analyze the same performances for such a TIA

where the new parameters introduced by the voltage amplifier are the dc gain A0 and the input referred noise of the amplifier IN ,Amp. If the dc gain A0 of the invert-ing amplifier is high enough, the bandwidth of the TIA is enhanced A0 times due to a reduction of the resistance seen from the input node, while the transimpedance does not change from the aforementioned converter. Thus, the feedback resistor RF can be higher for the same data rate, optimizing the input referred noise in spite of a new noise source, the inverting amplifier. This improvement is reflected in the bandwidth-noise trade-off

(5.5)TR =

−A0

1+ A0

· RF ≈ −RF if A0 ≫ 1

(5.6)BW =

1+ A0

CPD · RF

≈

A0

CPD · RF

if A0 ≫ 1

(5.7)I2N ,IN = I2N ,PD + I2N ,RF + I2N ,Amp ≈ I2N ,RF + I2N ,Amp =4 · K · T

RF

+ I2N ,Amp

(5.8)

BW

I2N ,IN

=

A0(

4 · K · T + I2N ,Amp · RF

)

· CPD

Fig. 5.3 Basic structure of a shunt feedback TIA: a circuit and b equivalent noise model

111

Although the denominator increases, the trade-off is relaxed by the increase in the numerator by A0. However, when the CPD is very big, as is our case, the dc gain of the inverter amplifier must also be very big, which can be difficult to design and would consume a lot of power. Therefore, another kind of TIAs, referred to as current-mode TIAs, are preferred if the load capacitance is lower than the input capacitance [SÄC10] as is our case. In contrast to the shunt-feedback TIA, the replacement of the voltage amplifier for a current amplifier modifies the critical node to determine the bandwidth. Ideal current amplifiers show zero input imped-ance and infinite output impedance and so the dominant pole is formed by the out-put resistance and load capacitance.

The proposed transimpedance amplifier, represented in Fig. 5.4, is formed by four stages: a negative feedback voltage follower and a three-stages voltage ampli-fier [GIM13]. The first stage has very low input impedance for high-speed opera-tion despite the large parasitic capacitance of the photodiodes (CPD), which can be up to 3 pF, whereas the amplifier increases the gain-bandwidth product. Moreover, the last voltage amplifier stage is implemented with a differential amplifier to bal-ance the signal. A low-pass filter is added in the dummy path to minimize the noise that comes from the dummy PD.

To increase the input dynamic range, an automatic gain control (AGC) loop is used to adjusts the gain of the TIA by means of a control voltage VCT. The AGC is formed by an integrator, implemented with an RC network with large time con-stant, and a comparator formed by a differential amplifier. Figure 5.5 shows the transistor level topology of the transimpedance amplifier.

The first stage is based on a negative-feedback voltage follower stage [PEL98, RIJ93] and provides a very low input resistance to handle the large PD capaci-tance. Transistors M1–M2 form a two-pole shunt negative-feedback loop that reduces the equivalent M2 source resistance Ri down to 3.2 Ω given by

Fig. 5.4 Block diagram of the whole transimpedance amplifier and the AGC



where gmi is the transconductance and roi is the source-drain resistance of the tran-sistor Mi.

Although in (5.9) it was not explicitly included, using a small signal model for high frequency, the input resistance of the TIA has a frequency-dependent behav-ior (Fig. 5.6). For frequencies below 500 MHz its value is constant and equal to 3.2 Ω whereas for higher frequencies the value increases, always remaining below 30 Ω. However, the peak takes place at around 5 GHz, which suffices to reach a 0.9 GHz bandwidth.

To implement the amplifiers, two simple common-source stages have been used (M3, M4 biased with their corresponding resistors R3, R4). For the last amplifier stage, a simple differential pair has been used.

The whole TIA provides a transimpedance of 60 dBΩ with a bandwidth of 0.9 GHz. The value of the transimpedance can be adapted to the amplitude of the input signal modifying the bias current of the first stage, yielding a −15-dBm sen-sitivity with 10−12 BER for the whole receiver.

(5.9)Ri =1

gm1 · gm2 · r02

Fig. 5.5 Transistor level topology of the transimpedance amplifier

113

5.1.2 Adaptive Equalizer

As mentioned before, 1-mm SI-POF shows a limited bandwidth that furthermore depends on several external effects; besides, transmitters have bandwidth limita-tions that degrade the properties of the transmitted signal [XI13]. For these rea-sons, adaptive equalization is mandatory for the selected application.

To implement the adaptive equalizer, the structure explained in Chap. 4 is used. Figure 5.7 shows the main blocks. This architecture is formed by the line equalizer SPEQ, which boosts the high-frequency component of the signal and the adaptation loop, which provides an error signal to control the line equalizer. The adaptation

Fig. 5.6 Dependence of the input impedance on the frequency

Fig. 5.7 Continuous-time adaptive equalizer


http://dx.doi.org/10.1007/978-3-319-10563-5_4


loop, based on the spectrum-balancing technique, uses two LPFs with different cut-off frequencies and a power error detector to perform the comparison. The same parameters for the filters that were described in Chap. 4 have been used: a dc gain of 2.3 and a cut-off frequency of 15 MHz for the first LPF and a gain of 1.3 and a cut-off frequency of 300 MHz for the second LPF. Obviously, both filters have additional poles given by the parasitic elements, but their effects are not significant because they are located at frequencies higher than 1 GHz.

Figure 5.8 shows the functionality of the adaptive loop after changes in the fiber length.

5.1.3 Limiting Amplifier

Once the signal is processed by the preamplifier and the equalizer, a postamplifier should be included to provide compatible digital signal levels for the following processing, typically source coupled logical (SCL) levels. The requirements of this stage are lower than that of the preamplifier because the noise contribution of the whole receiver is almost entirely determined by previous blocks. So, special atten-tion to bandwidth, gain and power must be taken into account.

There are two main approaches to implement postamplifiers: limiting amplifiers (LA) and variable gain amplifiers (VGA). LAs are usually open-loop non-linear systems which provide gain, ideally increasing the signal amplitude between sup-ply rails. On the other hand, VGAs are close-loop linear systems which provide gain and allow for constant output signal levels [RAZ03]. LAs offer several advan-tages in the design of post amplifiers for high-speed optical links [SÄC05, TAO06] that make them more suitable to be included in our design: higher operation speed, lower voltage supply and lower power consumption, easier design and smaller area, simpler monolithic implementation and slightly higher input sensitivity.

When designing LAs, the simplest topology consists of a cascade of N identical amplifiers having the same gain-bandwidth product (Fig. 5.9). The optimal value of N depends on the topology of each amplifier. Conventionally, each amplifier consists of a differential pair either passively or actively loaded [CRA06].

Fig. 5.8 Response of the equalizer adaptive loop. Generated error voltage VC for 10-m (0–1.5 and 3–4.5 µs) and 50-m (1.5–3 µs) POF

http://dx.doi.org/10.1007/978-3-319-10563-5_4

115

Nevertheless, this simple implementation has a serious drawback: a strong bandwidth dependence on the technology due to the load effect between stages. A possible solution is to select a more advanced and more expensive CMOS process. Other solutions without resorting to more sophisticated technologies have been reported to alleviate this setback. The first one is based on the down-scaling technique [MUL05]: the structure also consists of N amplifiers but in this case each amplifier is scaled with respect to its predecessor. Figure 5.9b shows this technique. It slightly reduces the load effect, but the problem remains. Other compensation techniques like the passive shunt-peaking [RAZ02a], where passive inductors are used to create a peak that increases the bandwidth, or the multi-feed-back technique [HUA07, WU06], which uses feedback to neutralize capacitances and effectively enhance the BW, have also been reported.

The limiting amplifier used in this design is based on the limiting amplifier reported in [GAR10]. It uses compensation stages to increase the bandwidth. As we are looking for a low-voltage and low-power structure with large bandwidth, simple common-source stages are used instead of differential pairs. As Fig. 5.10 shows, the proposed LA is composed of four consecutive amplifying stages plus two compensation stages between the first two and the last two gain stages, to achieve a higher gain and a larger output swing. These stages minimize the load effect between gain stages, which results in an overall reduction of the bandwidth of the amplifier. They are based on two NMOS transistors, being the upper one biased by a resistor connected between the supply and gate terminals. This resistor is needless in the dc operating point because there is no current flow across, so the gate voltage of the upper transistor equals VDD. However, it plays a very impor-tant role in the proposed frequency compensation. The compensation stages can be modeled by a second order transfer function with one zero and two poles [GAR10]

Fig. 5.9 Core of a limiting amplifier: a without downscaling, b with downscaling and c conventional passively loaded differential pair implementing each amplifier



where ro denotes the parallel equivalent resistance between ro1 and ro2, and Cgs2 is the gate-source parasitic capacitance of M2. Moreover, the contribution of the bias PMOS transistor has been neglected. This approximation may seem tough, but it is justified because the most important frequency contribution is made by the para-sitic Cgs of the NMOS transistors.

Therefore, the zero allows pole-zero cancellation of the pole of the first gain stage while at the same time, the second order nature of the transfer function provides a shunt-peaking effect which compensates the drop in the frequency response due to the second common source stage, both resulting in frequency compensation of the limiting amplifier.

Note that no extra passive devices such as inductors are needed. This makes the design more compact and robust than other previous structures based on passive inductors [RAZ02a]. The topology maintains the minimum voltage supply condition. The use of only two compensation stages barely increases the power consumption. And finally, the structure presents no physical feedback loop, thus ensuring stability.

The limiting amplifier used in this design is fed at 1 V, and it achieves a band-width of 1.25 GHz, which is sufficient for our application since noise does not imply stringent limitations at this stage.

5.1.4 Clock and Data Recovery Circuit

Although most of the nonidealities of the channel have been compensated with the previous circuits, the data still have no recovery. To prevent an excessive deg-radation that completely ruins the information, the received data stream has to be

(5.10)H(s)Comp ≈

−g1·rog2·ro+1

·

(

1+ s · Cgs2 · Ri

)

s2 ·CO·Cgs2·ro·Ri

g2·ro+1+ s ·

CO·ro+Cgs2·(ro+Ri)

g2·ro+1+ 1

Fig. 5.10 Half-circuit of the balanced limiting amplifier

117

regenerated periodically, in a process called data recovery, before being deserial-ized. Furthermore, since data are transmitted as a single signal through the chan-nel, there is no information about their timing reference, which appears to be somehow embedded in the data stream itself. To avoid misinterpretation of the message encoded in the data, it is necessary to have a time reference indicating how long the transmission of every bit takes. The extraction of the synchronization clock from the data stream is referred to as clock recovery.

Strictly speaking, data and clock recovery are not separate processes that can be carried out independently. Rather than that, the extraction of the synchronizing clock signal from the data stream has to be done prior to its regeneration. Because of this, the two processes are treated as a whole, in what is referred to as clock and data recovery. The specific circuitry that carries out this function is the clock and data recovery circuit (CDR). Its operation involves the extraction of the reference clock embedded in that data stream and the retiming and regeneration of the data, using the extracted clock as a time reference [RAZ96].

Modern CDRs for multigigabit applications use a wide variety of structures to carry out the task of clock recovery and data regeneration. Each of them has certain advantages and disadvantages and are therefore chosen for specific appli-cations [HSI08]. Some of the examples are among others: CDR based on delay-locked-loop [DAL05], which does not have jitter accumulation and is easy to guarantee its stability but has a limited capture range, making it unsuitable when the frequency off-set between transceiver and receiver is large; CDR based on phase interpolator, which can withstand a larger frequency off-set between the transceiver and the receiver but requires tight resolution for the DAC and the deliv-ery of quadrature clocks in multigigabit can be troublesome [HSI08].

The designed CDR is based on a phase-locked-loop (PLL) architecture, which shows good performance in continuous-mode high-speed serial links [HSI08]. A PLL is a system capable of generating a periodic signal locked in phase to a given reference. It is a closed loop system that tracks the phase difference between the reference and the generated signal, evolving in the direction of making it constant with time. Because frequency is obtained as the derivative of phase with respect to time, an immediate consequence of both signals having a constant phase shift is that their frequencies must be identical.

The structure of the CDR is shown in Fig. 5.11. It is formed by a voltage-con-trolled oscillator (VCO), a binary phase detector (BPD), and a voltage to current converter (V-I) that drives a second order loop filter (LF).

Voltage Controlled Oscillator (VCO)

A VCO is necessary as the CDR has to incorporate a block capable of generat-ing an oscillating signal that will be adjusted in phase to realize the sampling and regeneration of the data. Also, its frequency of oscillation has to be tunable: it must be variable around a given frequency, usually referred to as centre frequency, according to the changes produced on another magnitude, in this case a voltage. This is due to the fact that, as well as the variation of the centre frequency due to



PVT variations, in the particular case of a clock and data recovery circuit, lock acquisition is carried out dynamically because the adjustment of phase is achieved by a modification of the rate at which the system accumulates it, which is the oscillation frequency.

There are mainly two kinds of architectures being used in the literature for the implementation of VCOs: ring and LC oscillators. LC VCO achieves a very sta-ble oscillation thanks to the resonant nature of the LC tank present in its structure [AND02]. From a quantitative perspective, this translates into their having a lower phase noise figure than their ring counterparts, and also into being able to reach higher oscillation frequencies. Nevertheless, an LC VCO outperforms a ring VCO in terms of frequency and phase noise at the cost of occupying a relatively larger area. The reason for this is that an LC VCO requires the implementation of a high quality inductor for its correct operation, whereas a ring VCO does not, allow-ing a much more compact design. Besides area considerations, it is important to point out another significant advantage of the use of a ring structure for the VCO: it inherently generates several phases of the clock; this property is of great use for several applications, and in particular for a CDR circuit employing a multi-level binary phase detector (BPD) [SAN12].

Therefore, ring oscillator-based VCOs are the preferred choice for frequencies under 10 GHz where phase noise is not a determining factor [RAZ02b].

Generally speaking, a ring oscillator consists of a certain number of gain stages that are placed one after another and then fed back forming a closed loop. A dif-ferential ring oscillator can be built having an even number of delay stages, just by making one of them non-inverting by swapping its outputs, which allows creating a system that provides in-phase as well as quadrature outputs, very useful for the design of clock and data recovery circuits [RAZ03].

The VCO used for our design is a differential four-stage ring VCO. To design a differential delay stage for a ring VCO, the differential pair inverter structure with either active or passive loads is almost omnipresent in the literature, as reported, for example, in [CHE06, GER08, IER07, KOK07, REN08, ZHA06].

Fig. 5.11 Detailed differential CDR block diagram

119

The whole structure is biased by a tail current Itail. When this changes, the propagation delay of the stage also varies, which in turn results in a change of the oscillation frequency of the VCO. However, a mere variation of the tail current of the differential pair causes also a variation of its output dc voltage. This is an effect that has to be avoided because it complicates the connection of the VCO to subsequent stages.

The strategy to be followed when building the delay stage is keeping the delay stage structure as simple as possible, and leaving the output dc level stabilization to be carried out outside the ring, at the output buffer. The delay stage configura-tion used to build the ring VCO is represented in Fig. 5.12. Following the consid-erations discussed above, it is formed by a differential pair loaded by resistors; the tail current will be mirrored from the bias and control circuit.

The control circuitry has to be able, on the one hand, to provide the cor-rect biasing points to both the delay stages and the output buffer of the VCO; on the other hand, it has to produce a variation of the tail current of the delay stages according to the changes of an external voltage applied to the VCO, its control voltage Vcont. The schematic design of the control circuit is shown in Fig. 5.13.

So, changes in the frequency of the VCO are achieved via Vcont_1, generated in the VCO control voltage generator stage from the output of the V-to-I converter and loop filter. Current steering in a replica of the delay stages outside the ring has been used to achieve a constant dc level of oscillation to minimize the effect of jitter sources on the generation of the signal [SAN11b]. The action of Vtune cre-ates a current I2 whose changes balance those of the bias current of the VCO delay stage replicas, thus achieving a constant dc level of oscillation at the output. The designed dc level shift stage is shown in Fig. 5.12.

The VCO provides four differential output signals evenly spaced with a π/4 delay between them. This allows taking eight data samples per bit period, which in turn results in the possibility of designing a multi-level binary or bang-bang phase detector (BBPD).

Fig. 5.12 VCO delay stage schematics



Multi-level Bang-Bang Phase Detector

The synchronization process that takes place in a CDR is fulfilled when both sig-nals acquire phase at the same rate. Therefore, a phase detector is included in the CDR to extract the phase difference between the oscillating signal generated by the VCO and the input data stream; it uses this information to generate a signal that drives the VCO, modifying its frequency, until there is a constant phase differ-ence between these signals.

There are two main groups of phase detectors in terms of how they encode the information about the phase difference between the two signals that acts as their inputs. On the one hand, linear phase detectors give an output proportional to the phase difference between their input signals (Fig. 5.14a). They are characterized by their gain KPD, which is the slope of the straight line of its response. On the other hand, bang-bang phase detectors give information about the sign of the delay but not about its magnitude. The output they produce is a digital signal that only helps to state whether one of the inputs leads or lags behind the other as shown in Fig. 5.14b.

Finally, there is another group of phase detectors whose characteristics lie between those of linear and bang-bang phase detectors, referred to as improved or multi-level bang-bang. Multi-level BBPDs are used in CDRs to minimize the large jitter caused by binary. They operate digitally, contributing to the robustness of the system, but instead of stating only the sign of the phase difference, they provide quantized information about its magnitude. In all cases, the operation of a BBPD is based on taking samples of the data to discover between which samples a data tran-sition occurs. In the case of a two-level BBPD, only three samples per bit period are needed; as the number of quantization levels increases more samples are required.

Another issue that hinders the performance of BBPDs is metastability. It happens if samples are taken so close to the data transitions that the set-up and clock-to-Q times at the sampling flip-flops are violated [REN07]. BBPDs sample the data at the transitions at the locked state leading to metastability, which results in increased jitter.

Fig. 5.13 VCO control voltage circuit schematics

121

To overcome the drawbacks mentioned above, a seven-level BBPD is presented in which the clock transition that takes place with the data transitions at the locked state is disregarded [SAN11a]. To achieve this, the inverse of the main clock phase (which corresponds to clk−

1) is not used to take data samples to compute the phase

shift. All the remaining seven clock phases trigger a first set of D flip-flops (DFFs) that sample the data. These samples are re-clocked by a second set of DFFs that keep them at the same value for a whole clock period. The samples are subse-quently fed to a logic stage (formed by XOR gates) that computes that phase shift and encodes it in a thermometer code.

This information is fed to a V-I converter, which generates a proportional cur-rent that drives the loop filter. The block diagram of the proposed multi-level BBPD is shown in Fig. 5.15 whereas a plot of its output as a function of the phase difference between its inputs in shown in Fig. 5.16. It can be seen how the infor-mation about the phase difference is quantized into seven levels.

Some realizations of CDRs use a charge pump (CP) instead of a V-I. However, a CP [EMI13], creates undesired peaks in the control signal due to its internal behavior, based on turning switches on and off; for this reason, a V-I converter is a more suitable choice for this application.

The DFF, as well as the XOR gate, have to be designed so that they can operate at Gb/s. The CMOS logic family is not suitable for gigahertz frequencies, how-ever, current-mode logic (CML) is a good choice for high-speed environments [JIA01, SAN12]. Besides, the use of CML brings other advantages such as a higher immunity to supply noise and a reduced switching noise [ROD09, YAN10]; the minimization of the effects of noise has been strengthened by the use of differ-ential operation. The price to pay is a nonzero static power consumption.

The structure chosen for the DFF is based on a master-slave operation in which the two CML latches used follow a class A-B current switching topology (Fig. 5.17), suitable for multigigabit operation [LIA08, YAN10]. Finally, the DFFs are preceded by tapered buffers to achieve a high input swing.

As in the case of the DFFs, the structure of the XOR gates has to be oriented towards a reliable operation at a bit rate in the range of the Gb/s; therefore, CML and a differential operation have been chosen for its design. Besides, it is conveni-ent for the XOR gates to be symmetric with respect to their inputs, to avoid pos-sible differences in their propagation delays that could result in an incorrect output

Fig. 5.14 Phase detector output characteristics: a linear, and b bang-bang



for a certain time [SAV01, YAN10]. The symmetric and differential XOR gate implemented in CML is shown in Fig. 5.18.

Loop Filter

Finally, as Fig. 5.11 shows, the loop filter is an off-chip second order low-pass filter formed by two capacitors (CP and CS) and one resistor (RS) that is loaded or unloaded by the voltage-to-current converter and whose output is used to generate the control voltages (Vcont1 and Vcont2) of the VCO by its control voltage generator. Capacitor CP is placed for stability issues, just to achieve a new pole filtering the high frequency components to minimize the ripple at the control voltage of the VCO. The addition of this capacitor turns the filter into a second order one and

Fig. 5.15 Multi-level bang-bang phase detector block diagram

123

thus the CDR circuit becomes of third order. To minimize its effect, the value of CP is typically chosen to be much smaller than that of CS so that its effect on the CDR circuit is just the filtering of the jitter on the control voltage of the VCO, allowing in this way the use of a dominant pole approximation.


In this section, the experimental verification of the receiver front-end is described.The implemented prototype [SAN14], shown in Fig. 5.19, includes two 50-Ω

output drivers: one at the data output and other at the clock output. The main assignment of the output drivers is to drive 50-Ω loads with high output swing. Some external controls and test outputs have been included in the test bench.

Fig. 5.16 Output of the proposed multi-level BBPD as a function of the phase difference between its inputs

Fig. 5.17 CML DFF schematics



Figure 5.20 shows the output driver that is necessary for performing experi-mental measurements [AZN11]. A higher supply voltage (1.8 V) is used to increase the output signal levels to a value suitable for experimental measurements and to facilitate the design of the driver.

Before fabrication, the correct operation of the proposed design has been con-firmed by transistor level and post-layout simulations. The same layout strategies that were described in Chap. 3 (symmetrical paths, ESD protection, adequate PADs dis-tribution, guard rings, etc.) have been used to lay out the proposed receiver to ensure the correct operation of the circuits in high-frequency and low-voltage conditions. Figure 5.21 shows the microphotograph of the design, and Fig. 5.22 the layout of its active area, over which the location of its main blocks has been superimposed. The dimensions of the full chip are 1.45 · 0.9 mm2, whereas the active area is 0.24 mm2.

Fig. 5.18 CML XOR gate schematics

Fig. 5.19 Block diagram of the fabricated POF receiver

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5.2.1 Optical Characterization

To perform the optical characterization, the prototype was included in the set-up shown in Fig. 5.23.

The optical devices involved are a Mitsubishi GH SI-POF (ESKA Premier GH 4001, ~0.17 dB/m at 645 nm and NA = 0.5), and a S5972 silicon PD from Hamamatsu (0.8-mm diameter, 0.44-A/W responsivity at 660 nm). The test set-up

Fig. 5.20 Output driver

Fig. 5.21 Microphotograph of the chip for testing the POF receiver

Fig. 5.22 Layout of the active area. Its size is about 800 µm × 300 µm



includes an 650 nm RCLED-based GDL1000T-228 Firecomms evaluation board which converts to an optical signal the electrical bit pattern from a bit error ratio tester (BERT) Agilent N4096A. This board is supplied with 3.3 V, supports bit rates from 100 Mb/s to 1.25 Gb/s and is 50-Ω matched. Eye diagrams are obtained by using an Agilent 86100C digital communications analyzer (DCA). To minimize parasitic capacitances of the package, the prototype includes both the PD and the bare die directly fitted on the PCB. They are fixed to the PCB with silver epoxy, and adhesive electric conductor in a process at 50 °C during 6 h periods. The wire-bonding has been performed with a HYBOND 572A Wedge Bonder that operates through ultrasounds. It allows bonding in minimum surfaces of 25 µm × 25 µm. The wire-bonding material is high purity aluminum with 25-µm diameter that allows an optimum adhesion to the different surfaces.

A microphotograph of the PD-receiver combination is shown in Fig. 5.24.SMA up to 18 GHz connectors were also used in the signal lines. The output

signal lines include 100-nF decoupling ceramic capacitors and the supply lines are noise-filtered by using grounded ceramic capacitors. A plastic cap has been

Fig. 5.23 Experimental optical test set-up for the integrated prototype a block diagram, and b photograph of the test bench

127

used to focus the light beam directly to the PD. The photo of the designed PCB is shown in Fig. 5.25.

The whole power consumption is 107 mW without taking into account the out-put driver; 39 mW corresponds to the TIA-adaptive equalizer-limiting amplifier combination, and 68 mW to the CDR.

The design has been tested for a 1.25-Gb/s NRZ 2-1 PRBS pattern. The CDR circuit is able to regenerate the data with a BER lower than 10−12 with 8-ps rms jitter for the recovered clock. The CDR bandwidth is 2 MHz and its jitter peaking lies below 0.1 dB (Fig. 5.26), a threshold commonly used by standards such as SONET/SDH.

Figure 5.27a shows the eye diagram of the recovered clock obtained for the 231-1 input pseudo-random bit sequence. The peak-to-peak amplitude is about 200 mV. The jitter affecting the clock has been further amplified and its rms mag-nitude has been obtained (Fig. 5.27b) yielding a value of 8 ps.

Table 5.1 shows a summary of the CDR performances compared to other CMOS implementations in the range of the Gb/s.

Fig. 5.24 Microphotograph of the PD-receiver combination

Fig. 5.25 PCB of the receiver front-end



The eye diagrams of the signal after the POF and the PD loaded with the 50-Ω input resistance of the measurement equipment for 10, 30 and 50-m POF are shown in Fig. 5.28a–c, respectively. The eyes are quite close due to the limited bandwidth of the POF. Figure 5.28d shows the eye diagram at the receiver front-end output that is independent of the length of the fiber. These measurements dem-onstrate the proper operation of the whole receiver and, in particular, the adequate compensation of the limited frequency response of the POF.

The sensitivity is degraded due to the higher boosting of the preamplifier noise caused by the equalizer, as an increase of the POF length demands higher boosting of the equalizer frequency response to compensate the roll-off frequency limitation

Fig. 5.26 a Jitter transfer plot and b jitter peaking for the proposed CDR

Fig. 5.27 a Eye diagram of recovered clock signal, and b recovered clock jitter

Table 5.1 Summary of CDR performances and comparison with other works

Design [BEG03] [DJA00] [SCA02] Proposed CDR

Bit rate (Gb/s) 1 0.933 1 1.25

Technology (nm CMOS) 180 350 250 180

Jitter (UIrms) (%) 3 16 1.1 1

Power (mW) 300 200 100 68

129

of the POF. As derived from the measured bit error rate for the 10-m POF length shown in Fig. 5.29, an error-free (BER = 10−12) sensitivity of −17 dBm is achieved for 1.25 Gb/s. For 50-m POF, the sensitivity is slightly degraded to −15 dBm.

The main experimental performances as well as the comparison with other reported works are now described and summarized in Table 5.2.

To compare with other solutions, the used figure-of-merit (FOM) is

Because none of the systems listed in Table 5.2 incorporates a CDR, its contribution to the total power (68 mW) and FOM is disregarded for fair comparison. The proposed front-end achieves a FOM of 24.04, which is the highest in Table 5.2. In comparison, [SUN09] reports neither the TIA power consumption nor its sensitivity, so the values in this paper are assumed; [DON11] takes advantage of a superior and more expensive 65-nm CMOS technology and optimized graded-index POF channel; [GIM12, ATE12] only include the TIA and the line equalizer without any adaptation loop; besides, [ATE12] uses BiCMOS technology, which is more expensive than a CMOS technology of the same minimum feature length.

(5.1)FOM =Bit Rate (Mb/s) · Fiber Length (m) · Sensitivity (dBm)

Power (mW)

Fig. 5.28 Eye diagrams for 1.25-Gb/s NRZ PRBS 231-1 at the input for a 10-m POF, b 30-m POF, c 50-m POF and d at the output of the equalization/data recovery



5.3 Conclusions

In this chapter, an optical receiver front-end aimed for multi-gigabit short-range applications, achieving 1.25 Gb/s through up to 50-m POF and integrated in 0.18-µm CMOS technology with a supply voltage of 1 V, is presented. It is designed for low-cost applications; thus, a plastic optical fiber and a large area photodiode are used. Adaptive amplification and equalization are mandatory to achieve high performance because of the large capacitance of the photodiode and the frequency response of the plastic optical fiber, which strongly depends on its length.

The receiver includes a transimpedance amplifier, which provides a very low input impedance to handle the large parasitic capacitance of the outsized

Fig. 5.29 Measured BER versus input optical power for 10- and 50-m POF for 1.25 Gb/s

Table 5.2 Performance comparison of receivers (does not include the CDR)

Design [SUN09] [DON11] [GIM12] [ATE12] Proposed front-end

Channel SI-POF GI-POF SI-POF SI-POF SI-POF

Technology 0.35 μm CMOS

65 nm CMOS

0.18 μm CMOS

0.6 μm BiCMOS

0.18 μm CMOS

Wavelength (nm) 650 670 645 655 645

PD diameter (µm) 800 250 800 400 800

PD responsivity (A/W) 0.46 – 0.44 0.52 0.44

Bit rate (Gb/s) 1 3.125 1.25 1.25 1.25

Error-free sensitivity (dBm)

– −3.8 −8.2 −15.5 −15

POF length (m) 50 30 50 50 50

Power dissipation (mW)

165 (without TIA)

50 23 100 (with driver)

39

Area (mm2) 1.62 0.27 0.015 1.31 0.24

FOM 4.54 7.125 22.28 9.68 24.04

131

photodiode. Additionally, the adaptive equalizer boosts the high-frequency part of the signal to compensate the limited frequency response of the fiber. The limiting amplifier generates the required output levels. Finally, the CDR synchronizes and regenerates the data.

To implement the transimpedance amplifier a four-stage approach, that includes a negative feedback voltage follower and a three-stage voltage amplifier, was used. It provides the required low input impedance with a good sensitivity. A gain con-trol loop was included to improve the input dynamic range.

The adaptive equalizer is based on the building blocks detailed in Chaps. 3 and 4: the SPEQ is used to implement the line equalizer, and squarers and LPF/LPF filter combination is used to implement the adaptation loop.

A limiting amplifier has been included to provide compatible digital signal levels for the following processing. An open-loop non-linear LA has been used, which has four consecutive amplifier stages implemented with simple common-source stages actively loaded; the load effect between stages is minimized with the inclusion of compensation stages.

Finally, a clock and data recovery circuit has been included to regenerate and synchronize the data with a BER lower than 10−12 and a 1 % UIrms jitter for the recovered clock with a settling time shorter than 0.5 s. The designed CDR is based on a PLL architecture and is formed by a differential four-stage ring voltage-con-trolled oscillator, a multi-level bang-bang phase detector, and a voltage-to-current converter that drives an off-chip second order loop filter.

The results make this approach attractive to implement gigabit transmission demanded by in-house networks. It operates with a supply voltage of only 1 V and consumes 107 mW. These values are compatible with most modern low-cost standard digital nano-CMOS technologies, which impose 1-V operation in mixed analog-digital front-ends.

In the literature, there are a few examples of high speed transmission over POF, although the comparison among them is not easy. The proposed front-end provides the best results. Nevertheless, a strong effort is currently being made to develop POF-compliant receivers targeting multi-gigabit data rate.

The cost can be further reduced if the photodiode is integrated; however, the drawback worsens. In addition to the large capacitance, the responsivity is lower compared with an external photodiode and is further degraded by a slope of −4 dB/dec due to slowly diffusing carriers [RAD03]. All these fre-quency limitations must be compensated either by the designed equalizer, by optimized layout techniques for photodiode design or by both [CHE07]. An 800-Mb/s speed over SI-POF for a prototype integrated in 0.18-µm CMOS technology including an integrated photodiode is reported in [TAV10]. This result is encouraging in order to achieve multi-gigabit speed with a CMOS fully integrated receiver. However, the length of the POF channel is not men-tioned in the paper.

5.3 Conclusions

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Throughout this book, the most relevant results and main conclusions have been summarized in the final discussion of each chapter. In this final chapter, the most significant scientific contributions will be reported to give a general overview of the entire work.

In Chap. 1, the goals that were set before the start of the work leading to this book were presented; the first task that will be undertaken in this general conclu-sions section is the verification of the degree of agreement between the goals set and the results achieved.

Finally, further research directions will be point out. Among these are some issues not considered in this book as well as the more in-depth development of some of those already accomplished. These proposed investigations could well be used in future works as an extension to complement the work presented here.

6.1 General Conclusions

First of all, the theoretical fundamentals and mathematical analysis of continuous-time equalizers have been performed. The main contributions in this area are:

• An in-depth analysis of the power spectral density of non-return-to-zero data encoding and pseudo-random bit sequence has been presented.

• This analysis has allowed providing a thorough and unified model for contin-uous-time equalizers in the frequency domain. We demonstrated that the two most widely used approaches are equivalent and can be understood in the fre-quency domain.

• Behavioral models implemented in Matlab® have made it possible to provide a procedure to establish a filter design criteria based on the characteristics of the channel and the equalizer filter.

Chapter 6Conclusions


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136 6 Conclusions

• This procedure has led to the design criteria to select the most appropriate adap-tation loop filters and their corresponding bandwidths instead of the ad-hoc cri-teria used up to now.

• A functional simulation in Simulink® has been provided to determine which fil-ters are preferred in the adaptation loop.

The proposed criteria constitute a complete set of mathematical tools of easy application and they have disclosed to be very useful in the analysis and design of continuous-time adaptive equalizers.

Once the theoretical analysis has been performed, we proceeded with the syn-thesis of continuous-time line equalizers. A new continuous-time structure has been proposed. First, it has been compared with the conventional degenerated differential pair-based equalizer, which is the most widely-used continuous-time equalizer in literature. The most relevant results can be resumed as:

• The proposed equalizer provides a gain-bandwidth product more than a 25 % higher, with an input range three times higher. As a drawback, it presents a rel-atively higher input noise, which can be considered irrelevant in this receiver stage, and higher power consumption, which can be assumed in typical wireline systems, such as home area networks.

• The proposed equalizer is less sensible to common-mode input voltage and tem-perature variations.

• The proposed equalizer is also more robust against process variations.• Moreover, contrary to the degenerated differential pair-based equalizer, the pro-

posed equalizer controls of the gain and the zero are orthogonal which facili-tates tuning of the equalizer.

• The proposed equalizer reduces the rms deterministic jitter and intersymbol interference, more than 60 % up to 2 Gb/s.

So, the proposed equalizer overcomes the gain-bandwidth product and input range limitations suffered by the conventional degenerated differential pair-based equal-izer without significantly affecting the rest of parameters. Additionally, it is more robust as the main characteristics of the proposed equalizer are less affected by the PVT variations and by the common-mode input voltage.

Some other general conclusions of this equalizer include the following:

• The prototype has been designed for targeting 1.25 Gb/s over 50-m length of 1-mm SI-POF with only 1 V of supply voltage. However, the proposed equal-izer could be used for higher data rates, reaching 2 Gb/s.

• When comparing the experimental performances with other continuous-time equalizers presented in literature for the same application, the proposed equal-izer provides the best FOMs although other authors use a smaller PD, a more expensive technology or a higher supply voltage. This is thanks to the better fre-quency behavior with lower power consumption.

The equalizer must automatically adapt its response to the variations of the char-acteristics of the fiber, as well as process, voltage and temperature variations.

137

Therefore, an adaptation scheme along with the line equalizer has been imple-mented using the spectrum-balancing technique as the decision mechanism. The main results are highlighted as follow:

• High common-mode rejection ratio filters have been used, which makes the comparison more immune to offset variations.

• A new compact design of a power comparator based on a flipped-voltage fol-lower differential pair squarer has been proposed. Unlike the structures based on the conventional differential pair, it can be biased with 1-V supply voltage without severely degrading the input range available. Compared with the con-ventional differential pair-based power comparator, the proposed one exhibits half error with half power consumption.

• Two filter combinations have been studied in parallel to implement the power comparison: the already proposed APF/LPF and the new proposed LPF/LPF combination. Both provide similar results in terms of power, bandwidth, and noise but the double LPF combination is more robust in terms of PVT varia-tions: the maximum rms deterministic jitter for 50-m POF is a 73 % better under a corner analysis, a 59 % better under temperature variations, and a 44 % better under supply voltage variations; the intersymbol interference is a 55 % better under a corner analysis, a 21 % better under temperature variations, and a 39 % better under supply voltage variations.

• The proposed full adaptive equalizer has been designed for targeting 1.25 Gb/s through 1-mm SI-POF between 10- and 50-m long with only 1-V supply volt-age. When comparing experimental results with previously presented works in literature, it provides the best FOM although the lowest supply voltage seriously complicates the design.

The aforementioned adaptive equalizer has been integrated together with other specifically designed analog cells (transimpedance amplifier, limiting ampli-fier) and digital circuits (clock and data recovery circuit), comprising an opti-cal receiver for step-index plastic optical fiber. The most important results are summarized:

• The prototype, integrated in 0.18-µm CMOS technology, is aimed for multi-gigabit short-range applications, achieving 1.25 Gb/s through up to 50-m POF.

• It operates with a supply voltage of only 1 V, consumes 107 mW, and has a sensitivity of −15 dBm for error-free transmission with a commercial large area external photodiode.

• When comparing the experimental performances with other front-ends pre-sented in literature for the same application, the prototype presents better results thanks to the good sensitivity, low consumption and compatibility with higher area photodiodes. Moreover, the CDR used provides lower jitter (1 % UIrms) and power consumption (68 mW) than previously presented works in literature.

As a final conclusion, it must be noted that, although in this book we have focus our attention on SI-POF applications, due to the potential of the systems based on POF and submicron CMOS technology to provide the final user with a

6.1 General Conclusions

138 6 Conclusions

considerable speed increase compared to electric systems as well as to the com-plete confidentiality of the information thanks to the immunity to electromagnetic interference, the proposed structures can be adapted to many other applications where adaptive equalization is needed. Moreover, we have demonstrated the suit-ability of the proposed cells to operate with supply voltages of 1 V; therefore they can be downscaled to the most modern nano-CMOS technologies.

6.2 Further Research Directions

Recent research, including this book, has demonstrated that silicon CMOS has matured to a technology that is capable of competing with bipolar or even GaAs technologies in the field of gigabit optical communications. However, there are several challenges relating the design that will be of great interest to study in future projects.

There are new adaptive equalizers that offer new research lines to improve the behavior of the continuous-time adaptive equalizers proposed in this book, as well as propose some new equalizer architectures to reduce power consumption and area when integrating it in the whole front-end.

One future research direction includes the study of different modulation for-mats, such as duo-binary, PAM-4, etc., that can improve the equalized results in terms of data rate and signal-to-noise ratio.

Another interesting research direction faces with the integration of photodiodes in the same substrate as the whole front-end. In addition to the benefits in cost of a complete integrated receiver, it must be remarked the increase of reliability and the optimization of the connection between the photodiode and the front-end thanks to avoiding bound wires.

Moreover, when the transmission length increases, more effort is needed in designed a receiver front-end with very good sensitivity values to provide robust systems with eye-safety operation. Although the receiver proposed in Chap. 5 pre-sents better values of sensitivity than other works in literature, a transimpedance amplifier with an even better sensitivity is mandatory. Therefore, some techniques to reduce noise should be studied. This opens a very interesting research line.

The full integration of the analog front-end with digital circuitry may entail a non-considered issue. The noise caused by a huge number of transitions during digital processing could affect the sensitivity of the receiver. Although a basic iso-lation was employed, more research on isolation techniques could be necessary.

Maximum flexibility in emerging telecommunications applications requires the receivers to operate over a broad range of frequencies. For example, wavelength division multiplex (WDM) fiber-optic system where various clients are each assigned a wavelength. A key problem is that each client may wish to use a dif-ferent data rate signal, ranging from standard SONET rates to Ethernet to digital video. So, multi data rate equalizer architectures must be explored.

http://dx.doi.org/10.1007/978-3-319-10563-5_5

139

Finally, other issue that deserves to be studied is the test method for these equalizers. The most popular means of testing equalizers is to measure the eye-diagram using either an external scope or on-chip measurement circuitry. These methods test the equalizer by simply comparing the eye-openings before and after the equalizer. However, measuring the eye-diagram in the multi-gigahertz range requires either expensive equipment for external measurement or a significant amount of internal circuitry for on-chip measurement. Then, a cost-effective pro-duction test method for adaptive equalizers must be studied.

6.2 Further Research Directions

141

The response of plastic optical fibers depends, between others factors, on the type of fiber, the length and the coupling between the fiber with the emitter and the receiver. In this work, a Mitsubishi GH SI-POF has been used with lengths between 10 and 50 m. However, as the designed equalizer is adaptive, it can be used to compensate the response of other SI-POFs in the market.

A.1 Characteristics of Plastic Optical Fibers

Plastic optical fibers (POFs) are constituted by the core, the cladding and the jacket. The core is the central part of the fiber where the light is confined due to the higher refraction index than the cladding material; the jacket protects the core and the cladding. The core diameter in POFs is up to 1 mm, see Fig. A.1.

POFs are generally made with polymethyl methacrylate, an organic compound based on a polymer channel [ZIE08]. They are multimode fibers with large core diameter and high numerical aperture to facilitate the coupling of the light at the input and output. This is one of the most important advantages of POFs, as the connection technology that can be used is cheaper than with glass optical fibers (GOFs). Moreover, they are commonly manufacture with step-index profile; there-fore the cost is even reduced compared with grade-index POF.

The main problems when transmitting through POF are the dispersion and the attenuation that limit the bandwidth of the system and the transmission speed of the POF.

The attenuation of POF usually increases depending on the wavelength from visible range. Thus, transmission with a short wavelength as low as 650 nm is prefer-able [AZN13]. This wavelength is compatible with Si photodiodes and vertical-cavity surface-emitting laser (VCSEL) or light-emitting diode (LED). A plot of typical atten-uation is shown in Fig. A.2. It can be seen that the attenuation of a POF is typically 0.2 dB/m at 650 nm, so its use is limited to short-range applications.

Appendix A Plastic Optical Fibers

© Springer International Publishing Switzerland 2015 C. Gimeno Gasca et al., CMOS Continuous-Time Adaptive Equalizers for High-Speed Serial Links, Analog Circuits and Signal Processing, DOI 10.1007/978-3-319-10563-5

142 Appendix A: Plastic Optical Fibers

Dispersion refers to all processes that result in a difference in the transit times of various modes [SÄC05]. It produces a pulse to be broadened as it is transmit-ted through the POF. The main dispersion types are modal, chromatic and polar-ization-mode; however, in POF, the main effect is caused by modal dispersion. Different delays in the light components produce a reduction of the amplitude at high frequencies; that produce the fiber to behave like an LPF. Therefore, POF have a limited bandwidth length product of approximately 45 MHz · 100 m.

The response of the fiber changes depending on the temperature, the material properties, length, and other kind of effects such as connector, bends, etc. This causes the bandwidth of the fiber to change substantially. Figure A.3 shows the dependence of the frequency response of a Mitsubishi GH SI-POF only on its length [MAT09].

It can be seen that the BW changes substantially: from 400 MHz for 10-m POF to 100 MHz for 50-m POF. However, the slope of the frequency response stays relatively constant.

Fig. A.1 Step-index plastic optical fiber

Fig. A.2 Attenuation along a typical PMMA plastic optical fiber

Fig. A.3 Frequency response of a Mitsubishi GH SI-POF for different fiber lengths

143Appendix A: Plastic Optical Fibers

A.2 Simulation Model

Reliable electrical models with passive devices are employed to model the frequency response of the fiber for different length. Figure A.4 shows the circuit used to simulate the frequency response of the fiber, and Table A.1 shows the values used for the components for 10 and 50-m POF.

The voltage V1 is then

where

Figure A.5 shows a comparison for 10-m and 50-m POF between experimental and simulated results.

(A.1)V1 = I ·R · Zeq

R+ Zeq

(A.2)1

Zeq=

C1 · s

1+ R1 · C1 · s+

C2 · s

1+ R2 · C2 · s+ C3 · s

Fig. A.4 Equivalent circuit model that simulates the frequency response of the fiber

Table A.1 Summary of values of main parameters for the model of the POF

Parameter 10-m POF 50-m POF

R 100 Ω 100 Ω

R1 1.33 kΩ 80 Ω

C1 440 fF 7.4 pF

R2 50 Ω 46 Ω

C2 2.1 pF 3 pF

C3 1 pF 2 pF

Fig. A.5 Comparison between the experimental and simulated results for 10-m and 50-m fiber lengths

144 Appendix A: Plastic Optical Fibers

References

[AZN13] F. Aznar, S. Celma, B. Calvo, CMOS Receiver Front-Ends for Gigabit Short-Range Optical Communications. (Springer, New York, 2013).

[MAT09] J. Mateo, M.A. Losada, J. Zubia, Frequency Response in Step Index Plastic Optical Fibers Obtained from the Generalized Power Flow Equation. Optics Express 17(4), 2850–2860 (2009)

[SÄC05] E. Säckinger, Broadband Circuits for Optical Fiber Communication (Wiley Interscience, NJ, 2005)

[ZIE08] O. Ziemann, J. Kranser, P. E. Zamzow, W. Daum, POF Handbook Optical Short Range Transmission Systems. (Springer, Berlin, 2008).

145145© Springer International Publishing Switzerland 2015 C. Gimeno Gasca et al., CMOS Continuous-Time Adaptive Equalizers for High-Speed Serial Links, Analog Circuits and Signal Processing, DOI 10.1007/978-3-319-10563-5

Boost, 10, 16, 32, 34, 45, 83Boosting, 7, 10, 35, 36, 41, 55, 60, 76, 84, 93,

128

CCMOS, 1, 4, 8, 11, 19, 22, 23, 53, 60, 61, 77,

78, 88, 91, 92, 103, 104, 107, 115, 121, 128–131, 137, 138

Capacitance, 4, 19, 55, 60, 62, 71, 72, 85, 87, 88, 91, 92, 100, 110, 111, 115, 116, 126, 130, 131

Channel, 1–8, 10, 12, 13, 17, 18, 20, 22, 31–34, 36–40, 50, 81, 82, 89, 103, 108, 116, 129, 130, 135

Charge pump (CP), 121Clock, 3, 9, 14, 19, 21, 33, 118, 121, 123, 128,

131Clock and data recovery circuit (CDR), 22, 31,

108, 116–118, 128, 130, 131, 137Common-mode, 53, 54, 57, 58, 60, 61, 63, 64,

66, 77, 84–86, 89–91, 103, 108, 136Common-mode rejection ratio (CMRR), 56,

58, 60, 62–64, 84, 86, 92, 103, 137Common-source, 59, 85, 88, 90, 112, 115, 131Communication, 1, 3, 4, 13, 16, 18–20, 22, 23,

31, 33, 34, 37, 38, 43, 53, 81, 101, 107, 126, 138

Comparator, 22, 37, 82, 83, 85, 87, 88, 92, 99, 103, 111, 137

Compensation stage, 115, 116, 131Continuous-time (CT), 9, 11, 12, 14, 21–23,

31, 35, 37, 49, 50, 54, 56, 61, 68, 77–79, 81, 82, 84, 92, 98, 108, 113, 135, 136, 138

AAccumulated power, 37, 38, 41, 42, 45–47, 50Active, 10, 11, 62, 74, 75, 99, 100, 114, 118,

124, 131Adaptation loop, 14, 21–23, 31, 37, 40–43,

47, 48, 50, 64, 78, 79, 82–84, 88, 93, 94, 96, 100, 103, 104, 108, 113, 129, 131, 136

Adaptive, 6, 8, 13, 18–23, 31, 37–39, 42, 43, 46–50, 77, 81, 82, 88, 92, 93, 97, 99, 100, 103, 104, 107, 108, 113, 114, 127, 130, 136, 137, 139

All-pass filter (APF), 11, 35, 44–47, 49, 50, 56, 81, 83–88, 93–98, 103, 104, 137

Analog, 5, 8, 9, 11, 14, 16, 19, 21, 23, 61, 131, 137, 138

Analog to digital converter (ADC), 5, 8Attenuation, 2, 3, 6, 9, 12, 31, 53Automatic gain control (AGC), 19, 111

BBalanced, 53, 56, 61, 70, 71, 81, 100, 108, 116Band pass filters (BPF), 16, 42–44, 46, 47, 49Bandwidth (BW), 1, 2, 4, 7, 9, 11, 12, 17,

18, 22, 23, 31–33, 35, 37, 38, 41, 43, 44, 46, 47, 50, 53, 60, 62, 63, 65–67, 71, 72, 77, 78, 81, 84, 100–103, 107, 109–116, 127, 128, 136, 137

Bang-bang phase detector (BBPD), 119, 120, 122

Binary phase detector (BPD), 117, 118Bit error rate (BER), 3, 12, 13, 18, 20, 31, 81,

101, 112, 127, 130, 131Bit rate, 10, 32, 33, 37, 41, 42, 50, 83, 84, 102,

121, 126, 128, 130

Index

Index146146

Feedback, 10, 11, 56, 82, 84, 110, 111, 115, 116, 131

Feedforward (FFE), 12, 21Fiber, 53, 62, 72, 77, 79, 93, 103, 107, 114,

128, 130, 131, 136, 138, 141, 142Figure-of-merit (FOM), 78, 104, 129, 136, 137Finite impulse response (FIR), 5–11, 21Flip-flop, 120, 121Flipped-voltage follower, 89, 137Fourier, 33, 39Frequency-domain, 72, 135Front-end, 72, 107, 108, 123, 127–131, 137,

138

GGain, 7, 10, 11, 19, 21, 35, 36, 38, 44, 45, 53,

55, 58, 60, 64, 66, 76, 77, 82–84, 86, 88, 93, 103, 107, 110, 111, 114–116, 120, 131, 136

Glass optical fiber (GOF), 17, 18, 141Gm-C, 10, 16, 37, 56Graded index plastic optical fiber (GI-POF),

18, 130

HHigh-pass filter (HPF), 11, 16, 34, 35, 41, 43,

45, 49, 56

IIntegrator, 14, 48, 49, 91, 111Intersymbol interference (ISI), 2–4, 6, 7,

11–13, 21, 31, 38, 66, 68, 96, 103, 136, 137

JJitter, 9, 31, 39, 68, 96, 103, 117, 119, 120,

123, 127, 128, 131, 136, 137

LLaser, 19LC oscillator, 118Least mean square (LMS), 13, 21Light-emitting diode (LED), 17, 19Limiting amplifier, 19, 114–116, 127, 130, 131Line equalizer, 11, 13, 22, 23, 31, 32, 36, 37,

45, 47, 53, 54, 61, 74, 77, 78, 81, 82, 84, 89, 90, 93, 99, 103, 113, 129, 131

Loop filter (LF), 47, 50, 84, 99Loss, 3, 4, 7, 21, 81, 104, 107

Control, 14, 16, 19, 37, 43, 48, 49, 55, 56, 59, 60, 70, 76, 77, 82, 84, 89, 90, 93, 97, 98, 108, 111, 113, 117, 119, 121–123, 131, 136

Crosstalk, 2, 5, 6, 61, 62Current-mode, 111Current-steering, 88, 91, 103, 119Cut-off, 41, 42, 44, 46, 47, 60, 62, 83, 84, 86,

114

DDark current, 108Data rate, 2, 3, 9, 11, 17, 18, 37, 46, 68, 77,

110, 131, 136, 138De-embedding, 72, 100De-emphasis, 5, 6Decision feedback equalizer (DFE), 11, 12, 21Degenerated differential pair (DDP), 22, 23,

53–56, 59, 63, 136Delay, 5, 8, 9, 11, 85, 117, 119–121, 142Demultiplexer (DEMUX), 19Deserializer, 19Differential, 5, 10, 22, 23, 53–56, 60, 62–66,

68, 69, 77, 85, 87–92, 111, 112, 114, 115, 118, 119, 121, 122, 131, 136, 137

Differential amplifier, 5, 111Digital, 1, 3, 5, 8, 10, 18, 19, 53, 54, 101, 114,

120, 126, 131, 137, 138Digital to analog converter (DAC), 5, 6, 117Discrete time, 8Dispersion, 4, 18, 66, 141Driver, 18, 69, 70, 72, 74, 98–100, 123, 124,

127, 130Dynamic range, 21, 22, 55, 56, 59, 77, 84,

103, 111, 131

EElectromagnetic interference (EMI), 4, 5, 17,

138Equalization, 1–7, 9, 10, 12–14, 18, 21–23,

31, 32, 36–38, 40, 45, 50, 53, 62, 63, 67–69, 81, 93, 94, 96, 97, 102, 107, 113, 129, 130

Equalizer, 1, 2, 4–6, 8–14, 18–23, 53–56, 58–69, 72, 76–79, 81, 82, 108, 113, 127–129, 131, 135, 136, 138, 139

Error amplifier, 88Error comparator, 22, 37

FFall time, 48, 49

Index 147147

Process, voltage and temperature (PVT) varia-tions, 42, 66, 77, 81, 84, 93, 97, 103, 104, 118

Pseudo-random bit sequence (PRBS), 31, 33, 34, 48, 67–69, 93–98, 102, 129

RReceiver, 2–7, 9, 10, 12, 19–21, 23, 63, 78,

107, 109, 117, 123, 124, 126, 128, 130, 131, 136

Rectifier, 14, 37, 88Resonant-cavity light emitting diode

(RCLED), 17, 126Responsivity, 125, 130, 131Retimer, 19Ring oscillator, 118, 131Rise time, 49

SSensitivity, 10, 23, 40–43, 45, 46, 77, 107,

108, 112, 114, 128–130Serializer, 18Set-up, 68, 71–73, 98, 99, 102, 120, 125, 126Settling time, 9, 131Shunt feedback, 110Signal-to-noise ratio (SNR), 2, 6, 8, 10, 31,

45, 53Slicer, 14–16, 21, 37–42, 82, 88Spectrum, 7, 10, 14–18, 21–23, 31, 34, 35, 37,

41, 43, 67, 81–84, 103Spectrum-balancing technique, 15, 17, 21, 22,

37, 43–45, 49, 50, 81, 82, 103, 114, 137Split-path, 10, 11, 35, 47, 56Squarer, 14, 37, 88Step-index plastic optical fiber (SI-POF),

17–21, 23, 35, 48, 53, 57, 62, 63, 77, 78, 81, 93, 103, 107, 108, 113, 125, 130, 131, 137

Supply, 22, 53, 55, 59–65, 69, 70, 76, 77, 79, 88, 89, 91, 92, 97–100, 103, 104, 108, 114, 116, 121, 124, 126, 130, 131

TTemperature, 12, 18, 42, 63, 65, 78, 81, 93,

103, 107, 109, 137Time-domain, 14, 101, 102Transconductance, 54, 56, 59, 60, 81, 85Transconductor, 56, 59, 85Transimpedance amplifier (TIA), 19, 21, 23,

77, 108–112Transition time, 14, 38–40

Low-pass filter (LPF), 2, 11, 16, 34, 40, 43–46, 49, 56, 81, 83, 84, 86, 87, 93–97, 103, 104, 111, 114, 122, 131

MMean-square error (MSE), 13Mismatch, 11, 42, 61, 66, 78Multiplexer (MUX), 19

NNon return-to-zero (NRZ), 2, 17, 18, 23, 31,

33–37, 39, 43, 44, 50, 67, 68, 91, 92, 94, 95, 97, 98, 102, 127, 129

Negative feedback voltage follower, 111, 131Noise, 2, 7, 11, 13, 21, 31, 38, 42, 53, 61–63,

66, 67, 69, 78, 84, 92, 93, 100, 103, 108–111, 114, 116, 121, 126

OOffset, 33, 61, 88, 108Over-compensation, 83

PPassive, 10, 62, 72, 93, 109, 114–116, 118,

143Pattern, 33, 34, 101, 126, 127Period, 5, 6, 9, 16, 33, 34, 83, 84, 119–121Phase, 2, 9, 11, 14, 83, 85, 117–121Phase detector, 109, 117–120Phase-locked loop (PLL), 19, 109, 117, 131Photodiode (PD), 4, 19, 22, 23, 78, 79, 107,

109–111, 125, 127, 129, 130, 136Plastic optical fiber (POF), 4, 17–19, 21, 22,

24, 53, 57, 62, 63, 65, 67, 72, 77, 78, 81, 93–98, 100–102, 107, 108, 113, 124, 125, 128–130, 136, 137

Pole, 53, 55, 56, 58, 60, 84, 109, 111, 114, 116, 122

Postamplifier, 21, 114Power comparator, 82, 88, 91, 92, 99, 103Power consumption, 8, 10, 21, 44, 47, 49, 63,

74, 77–79, 81, 82, 84, 88, 93, 100, 103, 109, 114, 116, 121, 127, 129

Power detector, 88, 90, 103Power ratio, 43, 83, 84Power spectral density (PSD), 17, 33–38, 40,

43, 50, 135Pre-emphasis, 5–7Printed circuit board (PCB), 3, 5, 71, 72, 74,

75, 100, 101, 126, 127

Index148148

Transmitter, 2, 3, 5, 6, 18, 20, 21, 113

UUnder-compensation, 13, 18

VVariable gain amplifier (VGA), 114Variance, 48Vertical-cavity surface emitting laser

(VCSEL), 17, 141Voltage-controlled oscillator (VCO), 117–119,

122, 131Voltage-to-current converter (V–I), 88, 109,

117, 119, 122, 131Variations, 81

WWaveform monitor, 13

XXOR gate, 121

ZZero, 14, 32, 33, 36, 38, 47, 50, 53, 55, 56, 58,

60, 63, 65, 77, 93, 108, 111, 115, 116Zero forcing (ZF), 13

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