ST Sitronix ST7565 - HP InfoTech · 2019-10-21 · ST Sitronix ST7565 65 x 132 Dot Matrix LCD...

STSitronix ST7565 65 x 132 Dot Matrix LCD Controller/Driver

Ver 1.0a 1/56 2002/06/24

FFEEAATTUURREESS Direct display of RAM data through the display data

RAM. RAM capacity : 65 x 132 = 8580 bits Application Display driver circuits

1/65 duty : 65 common x 132 segment 1/49 duty : 49 common x 132 segment 1/33 duty : 33 common x 132 segment 1/55 duty : 55 common x 132 segment 1/53 duty : 53 common x 132 segment

High-speed 8-bit MPU interface (The chip can be connected directly to the both the 80x86 series MPUs and the 68000 series MPUs) /Serial interfaces are supported.

Abundant command functions Display data Read/Write, display ON/OFF, Normal/ Reverse display mode, page address set, display start line set, column address set, status read, display all points ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, common output status select, V5 voltage regulation internal resistor ratio set.

Static drive circuit equipped internally for indicators. (1 system, with variable flashing speed.)

Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratios of Double/Triple/ Quad, where the step-up voltage reference power

supply can be input externally). High-accuracy voltage adjustment circuit (Thermal gradient –0.15%/°C or external input) V5 voltage regulator resistors equipped internally, V1 to V4 voltage divider resistors equipped internally, electronic volume function equipped internally, voltage follower.

CR oscillator circuit equipped internally (external clock can also be input)

Extremely low power consumption Operating power when the built-in power supply is used (an example) 95uA (VDD – VSS = VDD – VSS2 =5.0 V, Quad voltage, V5 – VDD = – 11.0 V). Conditions: When displays pattern OFF and the normal mode is selected.

Power supply Operable on the low 2.0 voltage Logic power supply VDD – VSS = 4.0V to 5.5 V Boost reference voltage: VDD – VSS2 = 2.0V to 5.5V Booster maximum voltage limited VOUT= -18V Liquid crystal drive power supply: VDD – V5 = 4.0V to 13.0 V

Wide range of operating temperatures: –40 to 85°C CMOS process Shipping forms include bare chip and TCP. Not support master/slave mode These chips not designed for resistance to light or

resistance to radiation.

GGEENNEERRAALL DDEESSCCRRIIPPTTIIOONN The ST7565 is a single-chip dot matrix LCD drivers that can be connected directly to a microprocessor bus. 8-bit parallel or serial display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a LCD drive signal independent of the microprocessor. Because the chips in the ST7565 contain 65x132 bits of display data RAM and there is a 1-to-1 correspondence between the LCD panel pixels and the internal RAM bits, these chips enable displays with a high degree of freedom. The ST7565chips contain 65 common output circuits and 132 segment output circuits, so that a single chip can drive a 65x132 dot display (capable of displaying 8 columnsx4 rows

of a 16x16 dot kanji font). Moreover, the capacity of the display can be extended through the use of master/slave structures between chips. The chips are able to minimize power consumption because no external operating clock is necessary for the display data RAM read/write operation. Furthermore, because each chip is equipped internally with a low-power LCD driver power supply, resistors for LCD driver power voltage adjustment and a display clock CR oscillator circuit, the ST7565 can be used to create the lowest power display system with the fewest components for high-performance portable devices.

PART NO. VRS temperature gradient VRS range ST7565-0A -0.15%/°C -2.1V ±0.06V ST7565-0B External input ---

ST7565

Ver 1.0a 2/56 2002/06/24

PPIINN DDIIMMEENNSSIIOONNSS

Chip Size 9760 μm X 2440 μm Bump Pitch 65 μm (Min.) Bump Size PAD No. 1~24 85 μm X 85 μm

PAD No. 25~82 64 μm X 85 μm PAD No. 83~99 85 μm X 85 μm PAD No. 100 85 μm X 73 μm PAD No. 101~133 85 μm X 47 μm PAD No. 134 85 μm X 73 μm PAD No. 135 73 μm X 85 μm PAD No. 136~273 47 μm X 85 μm PAD No. 274 73 μm X 85 μm PAD No. 275 85 μm X 73 μm PAD No. 276~308 85 μm X 47 μm PAD No. 309 85 μm X 73 μm

Bump Height 18 μm (Typ.) Chip Thickness 457 μm

Master/slave mode cancel. VOUT maximum -18V ST7565-0A Temperature gradient = -0.15%/°C Logic power supply VDD – VSS = 4.0V to 5.5 V Booster 4 times cancel , 3 times , 2 times worked In display reverse mode , used display off command : display pixels all on In display reverse mode , used display all point on command : display pixels all off

(0,0) ST7565Die No.

1

309

275

274135

134

100

99

ST7565

Ver 1.0a 3/56 2002/06/24

PPaadd CCeenntteerr CCoooorrddiinnaatteess Units: μm

PAD No. PIN Name X Y

001 (NC) 4536 1117 002 FRS 4431 1117 003 FR 4326 1117 004 CL 4221 1117 005 /DOF 4116 1117 006 (NC) 4011 1117 007 VSS 3906 1117 008 /CS1 3801 1117 009 CS2 3696 1117 010 VDD 3591 1117 011 /RES 3486 1117 012 A0 3381 1117 013 VSS 3276 1117 014 WR(R/W) 3171 1117 015 RD(E) 3066 1117 016 VDD 2961 1117 017 D0 2856 1117 018 D1 2751 1117 019 D2 2646 1117 020 D3 2541 1117 021 D4 2436 1117 022 D5 2331 1117 023 D6(SCL) 2226 1117 024 D7(SI) 2121 1117 025 (NC) 2026.5 1117 026 VDD 1942.5 1117 027 VDD 1858.5 1117 028 VDD 1774.5 1117 029 VDD 1690.5 1117 030 VSS 1606.5 1117 031 VSS 1522.5 1117 032 VSS 1438.5 1117 033 VSS2 1354.5 1117 034 VSS2 1270.5 1117 035 VSS2 1186.5 1117 036 VSS2 1102.5 1117 037 (NC) 1018.5 1117 038 VOUT 934.5 1117 039 VOUT 850.5 1117 040 CAP3- 766.5 1117 041 CAP3- 682.5 1117 042 (NC) 598.5 1117 043 CAP1+ 514.5 1117 044 CAP1+ 430.5 1117 045 CAP1- 346.5 1117 046 CAP1- 262.5 1117 047 CAP2- 178.5 1117


048 CAP2- 94.5 1117 049 CAP2+ 10.5 1117 050 CAP2+ -73.5 1117 051 VSS -157.5 1117 052 VSS -241.5 1117 053 VRS -325.5 1117 054 VRS -409.5 1117 055 VDD -493.5 1117 056 VDD -577.5 1117 057 V1 -661.5 1117 058 V1 -745.5 1117 059 V2 -829.5 1117 060 V2 -913.5 1117 061 (NC) -997.5 1117 062 V3 -1081.5 1117 063 V3 -1165.5 1117 064 V4 -1249.5 1117 065 V4 -1333.5 1117 066 V5 -1417.5 1117 067 V5 -1501.5 1117 068 (NC) -1585.5 1117 069 VR -1669.5 1117 070 VR -1753.5 1117 071 VDD -1837.5 1117 072 VDD -1921.5 1117 073 TEST1 -2005.5 1117 074 TEST2 -2089.5 1117 075 TEST3 -2173.5 1117 076 TEST4 -2257.5 1117 077 TEST5 -2341.5 1117 078 TEST6 -2425.5 1117 079 TEST7 -2509.5 1117 080 TEST8 -2593.5 1117 081 TEST9 -2677.5 1117 082 TEST10 -2761.5 1117 083 VDD -2856 1117 084 M/S -2961 1117 085 CLS -3066 1117 086 VSS -3171 1117 087 C86 -3276 1117 088 P/S -3381 1117 089 VDD -3486 1117 090 /HPM -3591 1117 091 VSS -3696 1117 092 IRS -3801 1117 093 VDD -3906 1117 094 SEL1 -4011 1117

ST7565

Ver 1.0a 4/56 2002/06/24


095 VSS -4116 1117 096 SEL2 -4221 1117 097 VDD -4326 1117 098 SEL3 -4431 1117 099 VSS -4536 1117 100 (NC) -4777.5 1119 101 COM[31] -4777.5 1040 102 COM[30] -4777.5 975 103 COM[29] -4777.5 910 104 COM[28] -4777.5 845 105 COM[27] -4777.5 780 106 COM[26] -4777.5 715 107 COM[25] -4777.5 650 108 COM[24] -4777.5 585 109 COM[23] -4777.5 520 110 COM[22] -4777.5 455 111 COM[21] -4777.5 390 112 COM[20] -4777.5 325 113 COM[19] -4777.5 260 114 COM[18] -4777.5 195 115 COM[17] -4777.5 130 116 COM[16] -4777.5 65 117 COM[15] -4777.5 0 118 COM[14] -4777.5 -65 119 COM[13] -4777.5 -130 120 COM[12] -4777.5 -195 121 COM[11] -4777.5 -260 122 COM[10] -4777.5 -325 123 COM[9] -4777.5 -390 124 COM[8] -4777.5 -455 125 COM[7] -4777.5 -520 126 COM[6] -4777.5 -585 127 COM[5] -4777.5 -650 128 COM[4] -4777.5 -715 129 COM[3] -4777.5 -780 130 COM[2] -4777.5 -845 131 COM[1] -4777.5 -910 132 COM[0] -4777.5 -975 133 COMS -4777.5 -1040 134 (NC) -4777.5 -1119 135 (NC) -4531.5 -1117 136 (NC) -4452.5 -1117 137 (NC) -4387.5 -1117 138 (NC) -4322.5 -1117 139 SEG[0] -4257.5 -1117 140 SEG[1] -4192.5 -1117 141 SEG[2] -4127.5 -1117 142 SEG[3] -4062.5 -1117 143 SEG[4] -3997.5 -1117 144 SEG[5] -3932.5 -1117 145 SEG[6] -3867.5 -1117 146 SEG[7] -3802.5 -1117


147 SEG[8] -3737.5 -1117 148 SEG[9] -3672.5 -1117 149 SEG[10] -3607.5 -1117 150 SEG[11] -3542.5 -1117 151 SEG[12] -3477.5 -1117 152 SEG[13] -3412.5 -1117 153 SEG[14] -3347.5 -1117 154 SEG[15] -3282.5 -1117 155 SEG[16] -3217.5 -1117 156 SEG[17] -3152.5 -1117 157 SEG[18] -3087.5 -1117 158 SEG[19] -3022.5 -1117 159 SEG[20] -2957.5 -1117 160 SEG[21] -2892.5 -1117 161 SEG[22] -2827.5 -1117 162 SEG[23] -2762.5 -1117 163 SEG[24] -2697.5 -1117 164 SEG[25] -2632.5 -1117 165 SEG[26] -2567.5 -1117 166 SEG[27] -2502.5 -1117 167 SEG[28] -2437.5 -1117 168 SEG[29] -2372.5 -1117 169 SEG[30] -2307.5 -1117 170 SEG[31] -2242.5 -1117 171 SEG[32] -2177.5 -1117 172 SEG[33] -2112.5 -1117 173 SEG[34] -2047.5 -1117 174 SEG[35] -1982.5 -1117 175 SEG[36] -1917.5 -1117 176 SEG[37] -1852.5 -1117 177 SEG[38] -1787.5 -1117 178 SEG[39] -1722.5 -1117 179 SEG[40] -1657.5 -1117 180 SEG[41] -1592.5 -1117 181 SEG[42] -1527.5 -1117 182 SEG[43] -1462.5 -1117 183 SEG[44] -1397.5 -1117 184 SEG[45] -1332.5 -1117 185 SEG[46] -1267.5 -1117 186 SEG[47] -1202.5 -1117 187 SEG[48] -1137.5 -1117 188 SEG[49] -1072.5 -1117 189 SEG[50] -1007.5 -1117 190 SEG[51] -942.5 -1117 191 SEG[52] -877.5 -1117 192 SEG[53] -812.5 -1117 193 SEG[54] -747.5 -1117 194 SEG[55] -682.5 -1117 195 SEG[56] -617.5 -1117 196 SEG[57] -552.5 -1117 197 SEG[58] -487.5 -1117 198 SEG[59] -422.5 -1117

ST7565

Ver 1.0a 5/56 2002/06/24


199 SEG[60] -357.5 -1117 200 SEG[61] -292.5 -1117 201 SEG[62] -227.5 -1117 202 SEG[63] -162.5 -1117 203 SEG[64] -97.5 -1117 204 SEG[65] -32.5 -1117 205 SEG[66] 32.5 -1117 206 SEG[67] 97.5 -1117 207 SEG[68] 162.5 -1117 208 SEG[69] 227.5 -1117 209 SEG[70] 292.5 -1117 210 SEG[71] 357.5 -1117 211 SEG[72] 422.5 -1117 212 SEG[73] 487.5 -1117 213 SEG[74] 552.5 -1117 214 SEG[75] 617.5 -1117 215 SEG[76] 682.5 -1117 216 SEG[77] 747.5 -1117 217 SEG[78] 812.5 -1117 218 SEG[79] 877.5 -1117 219 SEG[80] 942.5 -1117 220 SEG[81] 1007.5 -1117 221 SEG[82] 1072.5 -1117 222 SEG[83] 1137.5 -1117 223 SEG[84] 1202.5 -1117 224 SEG[85] 1267.5 -1117 225 SEG[86] 1332.5 -1117 226 SEG[87] 1397.5 -1117 227 SEG[88] 1462.5 -1117 228 SEG[89] 1527.5 -1117 229 SEG[90] 1592.5 -1117 230 SEG[91] 1657.5 -1117 231 SEG[92] 1722.5 -1117 232 SEG[93] 1787.5 -1117 233 SEG[94] 1852.5 -1117 234 SEG[95] 1917.5 -1117 235 SEG[96] 1982.5 -1117 236 SEG[97] 2047.5 -1117 237 SEG[98] 2112.5 -1117 238 SEG[99] 2177.5 -1117 239 SEG[100] 2242.5 -1117 240 SEG[101] 2307.5 -1117 241 SEG[102] 2372.5 -1117 242 SEG[103] 2437.5 -1117 243 SEG[104] 2502.5 -1117 244 SEG[105] 2567.5 -1117 245 SEG[106] 2632.5 -1117 246 SEG[107] 2697.5 -1117 247 SEG[108] 2762.5 -1117 248 SEG[109] 2827.5 -1117 249 SEG[110] 2892.5 -1117 250 SEG[111] 2957.5 -1117


251 SEG[112] 3022.5 -1117 252 SEG[113] 3087.5 -1117 253 SEG[114] 3152.5 -1117 254 SEG[115] 3217.5 -1117 255 SEG[116] 3282.5 -1117 256 SEG[117] 3347.5 -1117 257 SEG[118] 3412.5 -1117 258 SEG[119] 3477.5 -1117 259 SEG[120] 3542.5 -1117 260 SEG[121] 3607.5 -1117 261 SEG[122] 3672.5 -1117 262 SEG[123] 3737.5 -1117 263 SEG[124] 3802.5 -1117 264 SEG[125] 3867.5 -1117 265 SEG[126] 3932.5 -1117 266 SEG[127] 3997.5 -1117 267 SEG[128] 4062.5 -1117 268 SEG[129] 4127.5 -1117 269 SEG[130] 4192.5 -1117 270 SEG[131] 4257.5 -1117 271 (NC) 4322.5 -1117 272 (NC) 4387.5 -1117 273 (NC) 4452.5 -1117 274 (NC) 4531.5 -1117 275 (NC) 4777.5 -1119 276 COM[32] 4777.5 -1040 277 COM[33] 4777.5 -975 278 COM[34] 4777.5 -910 279 COM[35] 4777.5 -845 280 COM[36] 4777.5 -780 281 COM[37] 4777.5 -715 282 COM[38] 4777.5 -650 283 COM[39] 4777.5 -585 284 COM[40] 4777.5 -520 285 COM[41] 4777.5 -455 286 COM[42] 4777.5 -390 287 COM[43] 4777.5 -325 288 COM[44] 4777.5 -260 289 COM[45] 4777.5 -195 290 COM[46] 4777.5 -130 291 COM[47] 4777.5 -65 292 COM[48] 4777.5 0 293 COM[49] 4777.5 65 294 COM[50] 4777.5 130 295 COM[51] 4777.5 195 296 COM[52] 4777.5 260 297 COM[53] 4777.5 325 298 COM[54] 4777.5 390 299 COM[55] 4777.5 455 300 COM[56] 4777.5 520 301 COM[57] 4777.5 585 302 COM[58] 4777.5 650

ST7565

Ver 1.0a 6/56 2002/06/24

PAD No. PIN Name X.5 Y

303 COM[59] 4777.5 715 304 COM[60] 4777.5 780 305 COM[61] 4777.5 845 306 COM[62] 4777.5 910 307 COM[63] 4777.5 975 308 COMS 4777.5 1040 309 (NC) 4777.5 1119

ST7565

Ver 1.0a 7/56 2002/06/24

BBLLOOCCKK DDIIAAGGRRAAMM

CO

MS

CO

M63

CO

M0

SEG131

SEG0

MPU INTERFACE ( Parallel and Serial )

Command decoder

Voltage Regulator circuit

Voltage follower circuit

Voltage booster circuit

Status Bus holder

DISPLAY DATA RAM

65 X 132 = 8580 Bits

Column address circuit

I/O buffer

Page address circuit

Line address circuit

Display data latch circuit

Oscillator circuit

Display tim

ing generator circuit

132 SEGMENT

DRIVERS

64 COMMON

DRIVERS

COM output control circuit

CO

MS

VDD V1V2V3V4V5

HPM

V5

VR

VRS

VOUT

IRS

CS1

CS2

A0

E(RD

)

RW

(WR

)

P/S

C86

/RES

SEL1

SEL2

SEL3

D6(SC

L)

D7(SI)

D5

D3

D4

D0

D1

D2

FRS

M/S

CL

FR

DOF

CLS Power Supply Circuit

CAP1+CAP1-

CAP2-CAP2+

CAP3+

VSS

VSS2

ST7565

Ver 1.0a 8/56 2002/06/24

PPIINN DDEESSCCRRIIPPTTIIOONNSS Power Supply Pins

Pin Name I/O Function No. of Pins

VDD Power Supply Shared with the MPU power supply terminal Vcc. 13

VSS Power Supply This is a 0V terminal connected to the system GND. 9

VSS2 Power Supply

This is the reference power supply for the step-up voltage circuit for the liquid crystal drive. 4

VRS Power Supply

This is the externally-input VREG power supply for the LCD power supply voltage regulator. These are only enabled for the models with the VREG external input option.

2

V1, V2, V3, V4,

V5 Power Supply

Power This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through changing the impedance using an op. amp. Voltage levels are determined based on VDD, and must maintain the relative magnitudes shown below. VDD (= V0) ≧V1 ≧V2 ≧V3 ≧V4 ≧V5 When the power supply turns ON, the internal power supply circuits produce the V1 to V4 voltages shown below. The voltage settings are selected using the LCD bias set command.

1/65 DUTY 1/49 DUTY 1/33 DUTY 1/55 DUTY 1/53 DUTY V1V2V3V4

1/9*V5,1/7*V5 2/9*V5,2/7*V5 7/9*V5,5/7*V5 8/9*V5,6/7*V5

1/8*V5,1/6*V52/8*V5,2/6*V56/8*V5,4/6*V57/8*V5,5/6*V5

1/6*V5,1/5*V52/6*V5,2/5*V54/6*V5,3/5*V55/6*V5,4/5*V5

1/8*V5,1/6*V52/8*V5,2/6*V56/8*V5,4/6*V57/8*V5,5/6*V5

1/8*V5,1/6*V5 2/8*V5,2/6*V5 6/8*V5,4/6*V5 7/8*V5,5/6*V5

10

LCD Power Supply Pins


CAP1+ O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. 2

CAP1– O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. 2

CAP2+ O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. 2



VOUT O DC/DC voltage converter. Connect a capacitor between this terminal and VSS. 2

VR I Output voltage regulator terminal. Provides the voltage between VDD and V5 through a resistive voltage divider. IRS = “L” : the V5 voltage regulator internal resistors are not used . IRS = “H” : the V5 voltage regulator internal resistors are used .

2

ST7565

Ver 1.0a 9/56 2002/06/24

System Bus Connection Pins


D5 to D0 D6 (SCL) D7 (SI)

I/O

This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus. When the serial interface is selected (P/S = “L”) : D7 : serial data input (SI) ; D6 : the serial clock input (SCL). D0 to D5 are set to high impedance. When the chip select is not active, D0 to D7 are set to high impedance.

8

A0 I This is connect to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command. A0 = “H”: Indicates that D0 to D7 are display data. A0 = “L”: Indicates that D0 to D7 are control data.

1

RES I When /RES is set to “L,” the settings are initialized. The reset operation is performed by the /RES signal level.

1

CS1 CS2 I

This is the chip select signal. When /CS1 = “L” and CS2 = “H,” then the chip select becomes active, and data/command I/O is enabled.

2

/RD (E) I

• When connected to an 8080 MPU, this is active LOW. (E) This pin is connected to the /RD signal of the 8080 MPU, and the ST7565 series data bus is in an output status when this signal is “L”. • When connected to a 6800 Series MPU, this is active HIGH. This is the 6800 Series MPU enable clock input terminal.

1

/WR (R/W) I

• When connected to an 8080 MPU, this is active LOW. (R/W) This terminal connects to the 8080 MPU /WR signal. The signals on the data bus are latched at the rising edge of the /WR signal. • When connected to a 6800 Series MPU: This is the read/write control signal input terminal. When R/W = “H”: Read. When R/W = “L”: Write.

1

C86 I This is the MPU interface switch terminal. C86 = “H”: 6800 Series MPU interface. C86 = “L”: 8080 MPU interface.

1

P/S I

This is the parallel data input/serial data input switch terminal. P/S = “H”: Parallel data input. P/S = “L”: Serial data input. The following applies depending on the P/S status:

When P/S = “L”, D0 to D5 may be “H”, “L” or Open. /RD (E) and /WR (R/W) are fixed to either “H” or “L”. With serial data input, It is impossible read data from RAM .

P/S Data/Command Data Read/Write Serial Clock

“H” A0 D0 to D7 /RD,/ WR X

“L” A0 SI (D7) Write only SCL (D6)

1

ST7565

Ver 1.0a 10/56 2002/06/24


CLS I

Terminal to select whether or enable or disable the display clock internal oscillator circuit. CLS = “H” : used Internal oscillator circuit . CLS = “L” : used external clock input .(internal oscillator is disable) When CLS = “L”, input the display clock through the CL terminal.

1

M/S I This pin set to VDD 1

CL I/O

This is the display clock input terminal The following is true depending on the M/S and CLS status.

M/S CLS CL

“H” “H” “L”

Output Input

“L” “H” “L”

Input Input

1

FR O This is the liquid crystal alternating current signal terminal. 1

/DOF O This is the LCD blanking control terminal. 1

FRS O This is the output terminal for the static drive. This terminal is only enabled when the static indicator display is ON and is used in conjunction with the FR terminal.

1

IRS I

This terminal selects the resistors for the V5 voltage level adjustment. IRS = “H”: Use the internal resistors IRS = “L”: Do not use the internal resistors. The V5 voltage level is regulated by an external resistive voltage divider attached to the VR terminal

1

/HPM I This is the power control terminal for the power supply circuit for liquid crystal drive. /HPM = “H”: Normal mode /HPM = “L”: High power mode

1

SEL3 SEL2 SEL1

I

These pins are DUTY selection. SEL 3 , 2 , 1 DUTY BIAS

0 , 0 , 0 1/65 1/9 or 1/7

0 , 0 , 1 1/49 1/8 or 1/6

0 , 1 , 0 1/33 1/6 or 1/5

0 , 1 , 1 1/55 1/8 or 1/6

1 , 0 , 0 1/53 1/8 or 1/6

1, X , X ----- -----

3

TEST1 ~ 10 I These are terminals for IC testing . They are set to open . 10

ST7565

Ver 1.0a 11/56 2002/06/24

LCD Driver Pins


SEG0 to

SEG131 O

These are the LCD segment drive outputs. Through a combination of the contents of the display RAM and with the FR signal, a single level is selected from VDD, V2, V3, and V5.

Output Voltage RAM DATA FR

Normal Display Reverse DisplayH H VDD V2 H L V5 V3 L H V2 VDD L L V3 V5

Power save VDD

132

COM0 to

COMn O

These are the LCD common drive outputs.

Through a combination of the contents of the scan data and with the FR signal, a single level is selected from VDD, V1, V4, and V5.

Part No. COM TOTALST7565 COM0 ~ COM63 64 ST7566 COM0 ~ COM47 48 ST7567 COM0 ~ COM31 32 ST7568 COM0 ~ COM53 54 ST7569 COM0 ~ COM51 52

Scan Data FR Output VoltageH H V5 H L VDD L H V1 L L V4

Power save VDD

COMS O These are the COM output terminals for the indicator. Both terminals output the same signal. Leave these open if they are not used.

2

ST7565

Ver 1.0a 12/56 2002/06/24

DDEESSCCRRIIPPTTIIOONN OOFF FFUUNNCCTTIIOONNSS The MPU Interface

Selecting the Interface Type

With the ST7565 chips, data transfers are done through an 8-bit parallel data bus (D7 to D0) or through a serial data input (SI). Through selecting the P/ S terminal polarity to the

“H” or “L” it is possib le to select e i ther para l le l data input or serial data input as shown in Table 1.

Table 1

P/S CS1 CS2 A0 RD WR C86 D7 D6 D5~D0

H: Parallel Input /CS1 CS2 A0 /RD /WR C86 D7 D6 D5~D0L: Serial Input /CS1 CS2 A0 — — — SI SCL (HZ)

“—” indicates fixed to either “H” or to “L”

The Parallel Interface

When the parallel interface has been selected (P/S =“H”), then it is possible to connect directly to either an

8080-system MPU or a 6800 Series MPU (shown in Table 2) by selecting the C86 terminal to either “H” or to “L”.

Table 2

C86 (P/S=H) CS1 CS2 A0 /RD /WR D7~D0

H: 6800 Series /CS1 CS2 A0 E R/W D7~D0 L: 8080 Series /CS1 CS2 A0 /RD /WR D7~D0

Moreover, data bus signals are recognized by a combination of A0, /RD (E), /WR (R/W) signals, as shown in Table 3.

Table 3 Shared 6800 Series 8080 Series

A0 R/W /RD /WR Function

1 1 0 1 Reads the display data

1 0 1 0 Writes the display data

0 1 0 1 Status read

0 0 1 0 Write control data (command)

ST7565

Ver 1.0a 13/56 2002/06/24

The Serial Interface

When the serial interface has been selected (P/S = “L”) then when the chip is in active state (/CS1 = “L” and CS2 = “H”) the serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from the serial data input pin in the rising edge of the serial clocks D7, D6 through D0, in this order. This data is converted to 8 bits parallel data in the rising edge of the eighth serial clock for the processing.

The A0 input is used to determine whether or the serial data input is display data or command data; when A0 = “H”, the data is display data, and when A0 = “L” then the data is command data. The A0 input is read and used for detection every 8th rising edge of the serial clock after the chip becomes active. Figure 1 is a serial interface signal chart.

Figure 1

* When the chip is not active, the shift registers and the counter are reset to their initial states. * Reading is not possible while in serial interface mode. * Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that operation

be rechecked on the actual equipment.

The Chip Select

The ST7565 have two chip select terminals: /CS1 and CS2. T h e M P U i n t e r f a c e o r t h e s e r i a l i n t e r f a c e i s enabled only when /CS1 = “L” and CS2 = “H”.

When the chip select is inactive, D0 to D7 enter a high impedance state, and the A0, /RD, and /WR inputs are inactive. When the serial interface is selected, the shift register and the counter are reset.

The Accessing the Display Data RAM and the Internal Registers

Data transfer at a higher speed is ensured since the MPU is required to satisfy the cycle time (tCYC) requirement alone in accessing the ST7565. Wait time may not be considered. And, in the ST7565, each time data is sent from the MPU, a type of pipeline process between LSIs is performed through the bus holder attached to the internal data bus. Internal data bus. For example, when the MPU writes data to the display data RAM, once the data is stored in the bus holder, then it is written to the display data RAM before the next data write cycle. Moreover, when the MPU reads the display data RAM,

the first data read cycle (dummy) stores the read data in the bus holder, and then the data is read from the bus holder to the system bus at the next data read cycle. There is a certain restriction in the read sequence of the display data RAM. Please be advised that data of the specified address is not generated by the read instruction issued immediately after the address setup. This data is generated in data read of the second time. Thus, a dummy rea d i s re q u i r ed whe n ev e r t he ad d res s se tu p or write cycle operation is conducted. This relationship is shown in Figure 2.

1 2 3 4 5 6 7 8 9 10 11 12 13 14

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2

CS1

CS2

SI

SCL

A0

ST7565

Ver 1.0a 14/56 2002/06/24

The Busy Flag

When the busy flag is “1” it indicates that the ST7565 is running internal processes, and at this time no command aside from a status read will be received. The busy flag is outputted to D7 pin with the read instruction. If the cycle time

(tCYC) is maintained, it is not necessary to check for this flag b e f o r e e a c h c o m m a n d . T h i s m a k e s v a s t improvements in MPU processing capabilities possible.

Figure 2

N N+1 N+2 N+3

N+3N+2N+1N

DATA

BUS Holder

Write Signal

WR

MPU

Internal Timing

Writing

DATA

WR

MPU

Reading

N N n n+1

RD

Preset N Increment N+1 N+2

n n+1N n+2

Address Preset

Read Signal

Column Address

Bus Holder

Internal Timing

Address Set#n

DummyRead

Data Read #nData Read#n+1

ST7565

Ver 1.0a 15/56 2002/06/24

Display Data RAM

Display Data RAM

The display data RAM stores the dot data for the LCD. It has a 65 (8 page x 8 bit +1) x 132 bit structure. as is shown in Figure 3, the D7 to D0 display data from the MPU corresponds to the LCD display common direction, there are few constraints at the time of display data transfer when multiple ST7565 are used, thus and display structures can be created easily and with a high degree of freedom.

Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering).

Figure 3 The Page Address Circuit

Page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access.

Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is a special RAM for icons, and only display data D0 is used. (see Figure 4)

The Column Addresses

The display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Moreover, the incrimination of column addresses stops with 83H. Because the column address is independent of the page address, when moving, for example, from page 0 column 83H to page 1 column 00H,

it is necessary to respectively both the page address and the column address. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized. As is shown in Figure 4,

Table 4

SEG Output ADC

SEG0 SEG 131

(D0) “0” (D0) “1”

0 (H) → Column Address → 83 (H) 83 (H) ← Column Address ← 0 (H)

The Line Address Circuit

The line address circuit, as shown in Table 4, specifies the line address relating to the COM output when the contents of the display data RAM are displayed. Using the display start line address set command, what is normally the top line of the display can be specified (this is the COM0 output when the common output mode is normal, and the COM63 output

for ST7565 , the detail is shown page.11 The display area is a 65 line area for the ST7565. If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed.

0

1

0

0

1

1

0

0

1

0

1

0

0

1

0

1

0

0

1

0

0

0

0

0

0

D0

D1

D2

D3

D4

-

Display data RAM

COM0

COM1

COM2

COM3

COM4

-

Liquid crystal display

ST7565

Ver 1.0a 16/56 2002/06/24

Page Address

D3 D2 D1 D0 Data Line Address When the common

output is normal COM

Output

D0 00H COM0D1 01H COM1D2 02H COM2D3 03H COM3D4 04H COM4D5 05H COM5D6 06H COM6

0 0 0 0

D7

Page 0

07H COM7D0 08H COM8D1 09H COM9D2 0AH COM10D3 0BH COM11D4 0CH COM12D5 0DH COM13D6 0EH COM14

0 0 0 1

D7

Page 1

0FH COM15D0 10H COM16D1 11H COM17D2 12H COM18D3 13H COM19D4 14H COM20D5 15H COM21D6 16H COM22

0 0 1 0

D7

Page 2


0 0 1 1

D7

Page 3


0 1 0 0

D7

Page 4


0 1 0 1

D7

Page 5


0 1 1 0

D7

Page 6


0 1 1 1

D7

Page 7

3FH

COM631 0 0 0 D0 Page 8 COMS

00

01

02

03

04

05

06

07

08 7B

7C

7D

7E

7F

80

81

82

83

0 D0

83

82

81

80

7F

7E

7D

7C

7B 08

07

06

05

04

03

02

01

00 1 D0 AD

C

Col

umn

addr

ess

Regardless of the display start line address, 1/65duty => 65th line, 1/49duty =>49th line.

S0

S1

S2

S3

S4

S5

S6

S7

S8

S123

S124

S125

S126

S127

S128

S129

S130

S131

LCD

O

ut 1/33duty =>33th line,

1/55duty =>55th line, 1/53duty =>53th line.

Figure 4

ST7565

Ver 1.0a 17/56 2002/06/24

The Display Data Latch Circuit

The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. Because the display normal/reverse status, display ON/OFF

status, and display all points ON/OFF commands control only the data within the latch, they do not change the data within the display data RAM itself.

The Oscillator Circuit

This is a CR-type oscillator that produces the display clock. The oscillator circuit is only enabled when M/S= “H” and CLS = “H”.

When CLS = “L” the oscillation stops, and the external clock is input through the CL terminal.

Display Timing Generator Circuit

The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of accesses to the display data RAM by the MPU. Consequently, even if the display data

RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive wave form using a 2 frame alternating current drive method, as is shown in Figure 5, for the liquid crystal drive circuit.

Two-frame alternating current drive waveform

Figure 5

64 65 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6

VDDV1

V4V5

COM0

VDDV1

V4V5

COM1

V5

V3

V2

VDD

RAMData

SEGn

FR

CL

ST7565

Ver 1.0a 18/56 2002/06/24

The Common Output Status Select Circuit

In the ST7565 chips, the COM output scan direction can be selected by the common output status select command.

(See Table 6.) Consequently, the constraints in IC layout at the time of LCD module assembly can be minimized.

Table 6

COM Scan Direction Status

1/65 DUTY 1/49 DUTY 1/33 DUTY 1/55 DUTY 1/53 DUTY Normal Reverse

COM0 → COM63 COM63 → COM0

COM0 → COM47COM47 → COM0


COM0 → COM53 COM53 → COM0


Common output pins

Duty Com dir com[0:15] com[16:23] com[24:26] com[27:36] com[37:39] com[40:47] com[48:63] coms0 com[0:63] coms

1/65 1 com[63:0] coms0 com[0:23] reverse com[24:47] coms

1/49 1 com[47:24] reverse com[23:0] coms0 com[0:15] reverse com[16:31] coms



1/53 1 com[51:26] reverse com[25:0] coms

The LCD Driver Circuits

These are a 197-channel, that generate four voltage levels for driving the LCD . The combination of the display data, the COM scan signal, and the FR signal produces the liquid

crystal drive voltage output. Figure 6 shows examples of the SEG and COM output wave form.

ST7565

Ver 1.0a 19/56 2002/06/24

Figure 6

SEG 0 1 2 3 4

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

VDDVSSVDDV1V2V3V4V5VDDV1V2V3V4V5VDDV1V2V3V4V5VDDV1V2V3V4V5VDDV1V2V3V4V5

VDDV1V2V3V4V5

-V1-V2-V3-V4-V5

VDDV1V2V3V4V5

-V1-V2-V3-V4-V5

FR

COM0

COM1

COM2

SEG0

SEG1

COM0 toSET0

COM0 toSET1

ST7565

Ver 1.0a 20/56 2002/06/24

The Power Supply Circuits

The power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the LCD drivers. They are Booster circuits, voltage regulator circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuits can turn the Booster circuits, the voltage regulator circuits, and the

voltage follower circuits ON or OFF independently through the use of the Power Control Set command. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. Table 7 shows the Power Control Set Command 3-bit data control function, and Table 8 shows reference combinations.

Table 7

bit function Status “1” “0”

D2 D1 D0

Booster circuit control bit Voltage regulator circuit control bit (V/R circuit) Voltage follower circuit control bit (V/F circuit)

ON OFF ON OFF ON OFF

The Control Details of Each Bit of the Power Control Set Command Table 8

Use Settings D2 D1 D0 Voltage booster

Voltage regulator

Voltage follower

External voltage input

Step-up voltage

Only the internal power supply is used 1 1 1 ON ON ON VSS2 Used Only the voltage regulator circuit and the

voltage follower circuit are used 0 1 1 OFF ON ON VOUT, VSS2 Open

Only the V/F circuit is used 0 0 1 OFF OFF ON V5, VSS2 Open

Only the external power supply is used 0 0 0 OFF OFF OFF V1 to V5 Open

Reference Combinations * The “step-up system terminals” refer CAP1+, CAP1–, CAP2+, CAP2–, and CAP3–. * While other combinations, not shown above, are also possible, these combinations are not recommended

because they have no practical use. The Step-up Voltage Circuits

Using the step-up voltage circuits equipped within the ST7565 chips it is possible to product a Quad step-up, a Triple step-up, and a Double step-up of the VDD – VSS2 voltage levels. Quad step-up: Connect capacitor C1 between CAP1+ and

CAP1–, between CAP2+ and CAP2–, between CAP1+ and CAP3–, and between VSS2 and VOUT, to produce a voltage level in the negative direction at the VOUT terminal that is 4 times the voltage level between VDD and VSS2.

Triple step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2– and

between VSS2 and VOUT, and short between CAP3– and VOUT to produce avoltage level in the negative direction at the VOUT terminal that is 3 times the voltage difference between VDD and VSS2.

Double step-up: Connect capacitor C1 between CAP1+ and CAP1–, and between VSS2 and VOUT, leave CAP2+ open, and short between CAP2–, CAP3– and VOUT to produce a voltage in the negative direction at the VOUT terminal that Is twice the voltage between VDD and VSS2.

The step-up voltage relationships are shown in Figure 7.

ST7565

Ver 1.0a 21/56 2002/06/24

Figure 7

* The VSS2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rated value. The Voltage Regulator Circuit

The step-up voltage generated at VOUT outputs the LCD driver voltage V5 through the voltage regulator circuit. Because the ST7565 chips have an internal high-accuracy fixed voltage power supply with a 64-level electronic volume function and internal resistors for the V5 voltage regulator,

systems can be constructed without having to include high-accuracy voltage regulator circuit components. Moreover, in the ST7565, Two types of thermal gradients have been prepared as VREG options: (1) approximately -0.15%/°C (2) external input (supplied to the VRS terminal)

(A) When the V5 Voltage Regulator Internal Resistors Are Used

Through the use of the V5 voltage regulator internal resistors and the electronic volume function the liquid crystal power supply voltage V5 can be controlled by commands alone (without adding any external resistors), making it possible to

adjust the liquid crystal display brightness. The V5 voltage can be calculated using equation A-1 over the range where | V5 | < | VOUT |.

VSS2

VOUT

CAP3-

CAP1+

CAP1-

CAP2-

CAP2+

ST7565

2x step-up voltage circuit

VDD=0V

VSS2=-5V

VOUT=3xVSS2=-10V

2x step-up voltage relationships

OPEN

C1

C1

VSS2

VOUT

CAP3-

CAP1+

CAP1-

CAP2-

CAP2+

ST7565


VDD=0V

VSS2=-3V

VOUT=3xVSS2=-9V


C1

C1

C1

VSS2

VOUT

CAP3-

CAP1+

CAP1-

CAP2-

CAP2+

ST7565


VDD=0V

VSS2=-3V

VOUT=4xVSS2=-12V


C1

C1

C1

C1

ST7565

Ver 1.0a 22/56 2002/06/24

Figure 8 VREG is the IC-internal fixed voltage supply, and its voltage at Ta = 25°C is as shown in Table 9. Table 9

Part no. Equipment Type Thermal Gradient VREG

ST7565-0A (1) Internal Power Supply –0.15 %/°C –2.1V ST7565-0B (2) External Input — VRS

α is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic volume register. Table 10 shows the value for α depending on the electronic volume register settings. Rb/Ra is the V5 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V5 voltage regulator internal resistor ratio set command. The (1 + Rb/Ra) ratio assumes the values shown in Table 11 depending on the 3-bit data settings in the V5 voltage regulator internal resistor ratio register. Table 10

D5 D4 D3 D2 D1 D0 α

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 : : 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1

636261: : 2 1 0

( )RbRa

+1 VEVV5=

=( )RbRa

+1 (1 -α162)VREG

[∵ VEV=(1 -α162)VREG]

Internal Ra

Internal Rb

VEV(constant voltage supply+electronic volume)

VDD

V5

ST7565

Ver 1.0a 23/56 2002/06/24

V5 voltage regulator internal resistance ratio register value and (1 + Rb/Ra) ratio (Reference value) Table 11

Register ST7565-0A ST7565-0B

D2 D1 D0 (1) –0.15 %/°C (2) VRS External Input

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Figures 9, 10 show V5 voltage measured by values of the internal resistance ratio resistor for V5 voltage adjustment and electric volume resister for each temperature grade model.

Figure 9 : (1) For ST7565-0A the Thermal Gradient = -0.15%/°C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register.

-14-13-12-11-10-9-8-7-6-5-4-3-2-1 0

111 110 101 100 011 010 001 000

00H 18H 30H 3FH

V5 UNIT:V

Electronic volume registered D5 ~ D0

V5 voltage regulator internal resistor ratio set D2,D1,D0

Ta = 25 °C and booster off ,regulator, follower on , VOUT=-13V , VSS=-3V

ST7565

Ver 1.0a 24/56 2002/06/24

Figure 10 : (2) For ST7565-0B with External Input VRS

The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. Setup example: When selecting Ta = 25°C and V5 = –7V for an ST7565-0A on which Temperature gradient = –0.15%/°C. Using Figure 9 and the equation A-1, the following setup is enabled. At this time, the variable range and the notch width of the V5 voltage is, as shown Table 13, as dependent on the electronic volume. Table 12

Register Contents D5 D4 D3 D2 D1 D0For V5 voltage regulator Electronic Volume

— — — 0 1 0

1 0 0 1 0 1 Table 13

V5 Min Typ Max Units Variable Range Notch width

–8.4 (63 levels) –6.8 (central value) –5.1 (0 level) [V] 51 [mV]

V5 voltage regulator internal resistor ratio set D2,D1,D0

-14-13-12-11-10-9-8-7-6-5-4-3-2-1 0

111

00H 18H 30H 3FH

V5 UNIT:V

Electronic volume registered D5 ~ D0

Ta = 25 °C and booster off ,regulator, follower on , VOUT=-13V , VSS=-3V,VRS=-2.6V

110 101

100 011 010 001 000

ST7565

Ver 1.0a 25/56 2002/06/24

(B) When an External Resistance is Used (The V5 Voltage Regulator Internal Resistors Are Not Used) (1)

The liquid crystal power supply voltage V5 can also be set without using the V5 voltage regulator internal resistors (IRS terminal = “L”) by adding resistors Ra’ and Rb’ between VDD and VR, and between VR and V5, respectively. When this is done, the use of the electronic volume function makes it possible to adjust the brightness of the liquid crystal display

by controlling the liquid crystal power supply voltage V5 through commands. In the range where | V5 | < | VOUT |, the V5 voltage can be calculated using equation B-1 based on the external resistances Ra’ and Rb’.

Figure 11

Setup example: When selecting Ta = 25°C and V5 = –7 V for ST7565-0A the temperature gradient = –0.15%/°C. When the central value of the electron volume register is (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α = 31 and VREG = –2.1V so, according to equation B-1,

=( )Rb'Ra'

+1 (1 -31162)(-2.1)-7V

=( )Rb'Ra'

+1 (1 -α162)VREGV5

Moreover, when the value of the current running through Ra’ and Rb’ is set to 5 uA,

Rb'=1.4MΩRa'+

Consequently, by equations B-2 and B-3,

=Rb'Ra'

3.12

Ra' =340kΩRb' =1060kΩ

At this time, the V5 voltage variable range and notch width, based on the electron volume function, is as given in Table 14.

Table 14 V5 Min Typ Max Units Variable Range Notch width


( )Rb'Ra'

+1 VEVV5=

=( )Rb'Ra'

+1 (1 -α162)VREG

[∵ VEV=(1 -α162)VREG]

Externalresistor Ra'

VEV(fixed voltage power supply+electronic volume)

VDD

V5

Externalresistor Rb'

ST7565

Ver 1.0a 26/56 2002/06/24

(C) When External Resistors are Used (The V5 Voltage Regulator Internal Resistors Are Not Used) (2)

When the external resistor described above are used, adding a variable resistor as well makes it possible to perform fine adjustments on Ra’ and Rb’, to set the liquid crystal drive voltage V5. In this case, the use of the electronic volume function makes it possible to control the liquid crystal power supply voltage V5 by commands to adjust the liquid

crystal display brightness. In the range where | V5 | < | VOUT | the V5 voltage can be calculated by equation C-1 below based on the R1 and R2 (var iable resistor) and R3 sett ings, where R2 can be subjected to fine adjustments (Δ R2).

Figure 12 Setup example: When selecting Ta = 25°C and V5 = –5 to –9 V (using R2) for an ST7565-0A the temperature gradient = –0.15%/°C. When the central value for the electronic volume register is set at (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α = 31 and VREG = –2.1 V so, according to equation C-1, when ΔR2 = 0 Ω, in order to make V5 = –9 V,

( R3R1+R2

+1-5V= )(1-31162)(-2.1) When ΔR2 = R2, in order to make V = –5 V,

( R3+R2R1

+1-9V= )(1-31162)(-2.1) When the current flowing VDD and V5 is set to 5 uA, With this, according to equation C-2, C-3 and C-4, The V5 voltage variable range and notch width based on the electron volume function is as shown in Table 15.

Table 15 V5 Min Typ Max Units Variable Range Notch width


( )R3+R2-ΔR2R1+ΔR2

+1 VEVV5=

=( )+1 (1-α162)VREG

[∵ VEV=(1 -α162)VREG]

R3+R2-ΔR2R1+ΔR2

Externalresistor R1

VEV(fixed voltage power supply+electronic volume)

VDD

V5

Externalresistor R3

VR

ΔR2Externalresistor R2

Rb'

Ra'

R2 =1.4MΩR1+ R2+

R1= 264kΩ

R2= 211kΩ

R3= 925kΩ

ST7565

Ver 1.0a 27/56 2002/06/24

* When the V5 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands. Moreover, it is necessary to provide a voltage from VOUT when the Booster circuit is OFF.

* The VR terminal is enabled only when the V5 voltage regulator internal resistors are not used (i.e. the IRS terminal = “L”). When the V5 voltage regulator internal resistors are used (i.e. when the IRS terminal = “H”), then the VR terminal

is left open. * Because the input impedance of the VR terminal is high, it is necessary to take into consideration short leads, shield

cables, etc. to handle noise.

The LCD Voltage Generator Circuit

The V5 voltage is produced by a resistive voltage divider within the IC, and can be produced at the V1, V2, V3, and V4 voltage levels required for liquid crystal driving. Moreover,

when the voltage follower changes the impedance, it provides V1, V2, V3 and V4 to the liquid crystal drive circuit.

High Power Mode

The power supply circuit equipped in the ST7565 chips has very low power consumption (normal mode: HPM = “H”). However, for LCDs or panels with large loads, this low-power power supply may cause display quality to degrade. When this occurs, setting the HPM terminal to “L” (high power mode) can improve the quality of the display. We

recommend that the display be checked on actual equipment to determine whether or not to use this mode. Moreover, if the improvement to the display is inadequate even after high power mode has been set, then it is necessary to add a liquid crystal drive power supply externally.

The Internal Power Supply Shutdown Command Sequence

The sequence shown in Figure 13 is recommended for shutting down the internal power supply, first placing the

power supply in power saver mode and then turning the power supply OFF.

Sequence Details Command address

(Command, status) D7 D6 D5 D4 D3 D2 D1 D0 Step1 Display OFF 1 0 1 0 1 1 1 0 Power saver Step2 Display all points ON 1 0 1 0 0 1 0 1 commands End Internal power supply OFF (compound)

Figure 13

The temperature grade of the Internal Power Supply for ST7565-0A (-0.15%/°C) :

Figure 14

V5 0V

-40°C -20°C 0°C 25°C 50°C 85°C

7V

8V

9V

10V

Ta

Ta=-40°C , V5=9.40V

Ta=25°C , V5=8.46V

Ta=85°C , V5=7.60V

ST7565

Ver 1.0a 28/56 2002/06/24

Reference Circuit Examples(standar)

Figure 15 shows reference circuit examples. 1. When used all of the step-up circuit, voltage regulating circuit and V/F circuit (1) When the voltage regulator internal resistor

is used. (Example where VSS2 = VSS, with 4x step-up)

(2) When the voltage regulator internal resistor is not used.

(Example where VSS2 = VSS, with 4x step-up)

2. When the voltage regulator circuit and V/F circuit alone are used (1) When the V5 voltage regulator internal resistor

is not used. (2) When the V5 voltage regulator internal resistor

is used.

VSS2

VOUT

CAP3-

CAP1+

CAP1-

CAP2+

CAP2-

V5

VR

VDD

V1

V2

V3

V4

V5

ST7565

IRS M/S

C1

C1

C1

C1

C2

C2

C2

C2

C2

VDD

VDD

VSSVSS2

VOUT

CAP3-

CAP1+

CAP1-

CAP2+

CAP2-

V5

VR

VDD

V1

V2

V3

V4

V5

ST7565

IRS M/S

C1

C1

C1

C1

C2

C2

C2

C2

C2

VDD

VSS

VDD

R3

R2

R1

VSS2

VOUT

CAP3-

CAP1+

CAP1-

CAP2+

CAP2-

V5

VR

VDD

V1

V2

V3

V4

V5

ST7565

IRS M/S

C2

C2

C2

C2

C2

VDD

VSS

VDD

R3

R2

R1

VSS2

VOUT

CAP3-

CAP1+

CAP1-

CAP2+

CAP2-

V5

VR

VDD

V1

V2

V3

V4

V5

ST7565

IRS M/S

C2

C2

C2

C2

C2

VDD

VDD

VSS

Externalpowersupply

Externalpowersupply

ST7565

Ver 1.0a 29/56 2002/06/24

3. When the V/F circuit alone is used 4. When the built-in power is not used

5. When the built-in power circuit is used to drive a liquid crystal panel heavily loaded with AC or DC, it is recommended to connect an external resistor to stabilize potentials of V1, V2, V3 and V4 which are output from the built-in voltage follower.

Examples of shared reference settings When V5 can vary between –8 and 12 V

Reference set value R4: 100KΩ ~ 1MΩ It is recommended to set an optimum

resistance value R4 taking the liquid crystal display and the drive waveform.

Figure 15 * 1. Because the VR terminal input impedance is high, use short leads and shielded lines. * 2. C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal

drive voltage. Example of the Process by which to Determine the Settings: • Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside. • Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that

stabilizes the liquid crystal drive voltages (V1 to V5). Note that all C2 capacitors must have the same capacitance value.

• Next turn all the power supplies ON and determine C1.

Item Set value Units

C1 C2

1.0 to 4.7 0.1 to 4.7

uF uF

VSS2

VOUT

CAP3-

CAP1+

CAP1-

CAP2+

CAP2-

V5

VR

VDD

V1

V2

V3

V4

V5

ST7565

IRS M/S

C2

C2

C2

C2

C2

VDD

VDD

VSS

Externalpowersupply

VSS2

VOUT

CAP3-

CAP1+

CAP1-

CAP2+

CAP2-

V5

VR

VDD

V1

V2

V3

V4

V5

ST7565

IRS M/S

VDD

VDD

VSS

External power supply

V5

ST7565

VDD,V0

V1

V2

V3

V4

R4 R4

R4 R4

C2 C1 and C2 are determined by the size of the LCD being driven

ST7565

Ver 1.0a 30/56 2002/06/24

Reference Circuit Examples

C1: 1.0uF to 4.7uF C2: 0.1uF to 1.0uF R1:30KΩ.. 300KΩ

IRS M/SV8

VOUT

CAP3-

CAP1+

CAP1-

CAP2+

CAP2-

VRS

VDD

V1

V2

V3

V4

V5

VDD

VSS

VDD

C2

C2

C2

C2

C2

R1

C1

C1

C1

C1ST7565

ST7565

Ver 1.0a 31/56 2002/06/24

The Reset Circuit

When the /RES input comes to the “L” level, these LSIs return to the default state. Their default states are as follows: 1. Display OFF 2. Normal display 3. ADC select: Normal (ADC command D0 = “L”) 4. Power control register: (D2, D1, D0) = (0, 0, 0) 5. Serial interface internal register data clear 6. LCD power supply bias rate:

1/65 DUTY = 1/9 bias 1/49,1/55,1/53 DUTY = 1/8 bias 1/33 DUTY = 1/6 bias

7. All-indicator lamps-on OFF (All-indicator lamps ON/OFF command D0 = “L”)

8. Power saving clear 9. V5 voltage regulator internal resistors Ra and Rb

separation 10. Output conditions of SEG and COM terminals SEG :

V2/V3, COM : V1/V4 11. Read modify write OFF 12. Static indicator OFF Static indicator register : (D1, D2) =

(0, 0) 13. Display start line set to first line 14. Column address set to Address 0 15. Page address set to Page 0 16. Common output status normal 17. V5 voltage regulator internal resistor ratio set mode clear 18. Electronic volume register set mode clear Electronic

volume register : (D5 , D4 , D3 , D2 , D1 , D0 ) = (1 , 0 . 0 , 0 , 0 ,0 ) 19. Test mode clear

On the other hand, when the reset command is used, the above default settings from 11 to 19 are only executed. When the power is turned on, the IC internal state becomes unstable, and it is necessary to initialize it using the /RES terminal. After the initialization, each input terminal should be controlled normally. Moreover, when the control signal from the MPU is in the high impedance, an over current may flow to the IC. After applying a current, it is necessary to take proper measures to prevent the input terminal from getting into the high impedance state. If the internal liquid crystal power supply circuit is not used on ST7565,it is necessary that /RES is “H” when the external liquid crystal power supply is turned on. This IC has the function to discharge V5 when /RES is “L,” and the external power supply short-circuits to VDD when /RES is “L.” While /RES is “L,” the oscillator and the display timing generator stop, and the CL, FR, FRS and /DOF terminals are fixed to “H.” The terminals D0 to D7 are not affected. The VDD level is output from the SEG and COM output terminals. This means that an internal resistor is connected between VDD and V5. When the internal liquid crystal power supply circuit is not used on other models of ST7565 series, it is necessary that /RES is “L” when the external liquid crystal power supply is turned on. While /RES is “L,” the oscillator works but the display timing generator stops, and the CL, FR, FRS and /DOF terminals are fixed to “H.” The terminals D0 to D7 are not affected.

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Ver 1.0a 32/56 2002/06/24

CCOOMMMMAANNDDSS The ST7565 identify the data bus signals by a combination of A0, /RD (E), /WR(R/W) signals. Command interpretation and execution does not depend on the external clock, but rather is performed through internal timing only, and thus the processing is fast enough that normally a busy check is not required. In the 8080 MPU interface, commands are launched by inputting a low pulse to the /RD terminal for reading, and inputting a low pulse to the /WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read mode when an “H” signal is input to the R/W terminal and placed in a write mode when a “L” signal is input to the R/W terminal and then the command is launched by inputting a high pulse to the E terminal. Consequently, the 6800 Series MPU interface is different than the 80x86 Series MPU interface in that in the explanation of commands and the display commands the status read and display data read /RD (E) becomes “1(H)”. In the explanations below the commands are explained using the 8080 Series MPU interface as the example. When the serial interface is selected, the data is input in sequence starting with D7. <Explanation of Commands>

Display ON/OFF

This command turns the display ON and OFF. E R/W

A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0

Setting 0 1 0

1 0 1 0 1 1 1 1

0 Display ON Display OFF

When the display OFF command is executed when in the display all points ON mode, power saver mode is entered. See the section on the power saver for details.

Display Start Line Set

This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further details see the explanation of this function in “The Line Address Circuit”.

E R/W

A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0

Line address 0 1 0

0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0

↓ 1 1 1 1 1 0 1 1 1 1 1 1

0 1 2 ↓ 62 63

Page Address Set

This command specifies the page address corresponding to the low address when the MPU accesses the display data RAM (see Figure 4). Specifying the page address and column address enables to access a desired bit of the display data RAM. Changing the page address does not accompany a change in the status display.

E R/W

A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0

Page address 0 1 0

1 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0

↓ 0 1 1 1 1 0 0 0

0 1 2 ↓ 7 8

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Ver 1.0a 33/56 2002/06/24

Column Address Set

This command specifies the column address of the display data RAM shown in Figure 4. The column address is split into two sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the display data RAM is accessed, the column address automatically increments (+1), making it possible for the MPU to continuously read from/write to the display data. The column address increment is topped at 83H. This does not change the page address continuously. See the function explanation in “The Column Address Circuit,” for details.

E R/W A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0

Columnaddress

High bits → Low bits →

0 1 0

0 0 0 1 A7 A6 A5 A4 0 0 0 0 0 0 0 0 0 A3 A2 A1 A0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0 ↓

1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1

0 1 2 ↓

130 131

Status Read

E R/W A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 BUSY ADC ON/OFF RESET 0 0 0 0

BUSY

BUSY = 1: it indicates that either processing is occurring internally or a reset condition is in process. BUSY = 0: A new command can be accepted . if the cycle time can be satisfied, there is no need to check

for BUSY conditions.

ADC

This shows the relationship between the column address and the segment driver. 0: Reverse (column address 131-n ↔ SEG n) 1: Normal (column address n ↔ SEG n) (The ADC command switches the polarity.)

ON/OFF

ON/OFF: indicates the display ON/OFF state. 0: Display ON 1: Display OFF (This display ON/OFF command switches the polarity.)

RESET

This indicates that the chip is in the process of initialization either because of a /RES signal or because of a reset command.

0: Operating state 1: Reset in progress

Display Data Write

This command writes 8-bit data to the specified display data RAM address. Since the column address is automatically incremented by “1” after the write, the MPU can write the display data.

E R/W A0 /RD / WR

D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 Write data

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Ver 1.0a 34/56 2002/06/24

Display Data Read

This command reads 8-bit data from the specified display data RAM address. Since the column address is automatically incremented by “1” after the read, the CPU can continuously read multiple-word data. One dummy read is required immediately after the column address has been set. See the function explanation in “Display Data RAM” for the explanation of accessing the internal registers. When the serial interface is used, reading of the display data becomes unavailable.

E R/W A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0

1 0 1 Read data ADC Select (Segment Driver Direction Select)

This command can reverse the correspondence between the display RAM data column address and the segment driver output. Thus, sequence of the segment driver output pins may be reversed by the command. See the column address circuit (page 1–20) for the detail. Increment of the column address (by “1”) accompanying the reading or writing the display data is done according to the column address indicated in Figure 4.

E R/W A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0

Setting

0 1 0

1 0 1 0 0 0 0 0 1

Normal Reverse

Display Normal/Reverse

This command can reverse the lit and unlit display without overwriting the contents of the display data RAM. When this is done the display data RAM contents are maintained.

E R/W A0 /RD / WR

D7 D6 D5 D4 D3 D2 D1 D0

Setting

0 1 0

1 0 1 0 0 1 1 0

1

RAM Data “H” LCD ON voltage (normal)

RAM Data “L” LCD ON voltage (reverse)

Display All Points ON/OFF

This command makes it possible to force all display points ON regardless of the content of the display data RAM. The contents of the display data RAM are maintained when this is done. This command takes priority over the display normal/reverse command.

E R/W A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0

Setting

0 1 0

1 0 1 0 0 1 0 0 1

Normal display mode Display all points ON

When the display is in an OFF mode, executing the display all points ON command will place the display in power save mode. For details, see the Power Save section.

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Ver 1.0a 35/56 2002/06/24

LCD Bias Set

This command selects the voltage bias ratio required for the liquid crystal display.

Select Status E R/W

A0 /RD / WR

D7 D6 D5 D4 D3 D2 D1 D0 1/65duty 1/49duty 1/33duty 1/55duty 1/53duty

1/9 bias 1/8 bias 1/6 bias 1/8 bias 1/8 bias0 1 0

1 0 1 0 0 0 1 0

1 1/7 bias 1/6 bias 1/5 bias 1/6 bias 1/6 bias Read/Modify/Write

This command is used paired with the “END” command. Once this command has been input, the display data read command does not change the column address, but only the display data write command increments (+1) the column address. This mode is maintained until the END command is input. When the END command is input, the column address returns to the address it was at when the read/modify/write command was entered. This function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor.

E R/W A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 1 1 1 0 0 0 0 0 * Even in read/modify/write mode, other commands aside from display data read/write commands can also be used. However, the column address set command cannot be used.

END

Page address set

Column address set

Dummy read

Data read

Data write

Changes Finished ?

Read-modify-write cycle

NO

YES

Figure 24 Command Sequence For read modify write

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Ver 1.0a 36/56 2002/06/24

Figure 25 End

This command releases the read/modify/write mode, and returns the column address to the address it was at when the mode was entered.

E R/W A0 /RD / WR

D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 1 1 1 0 1 1 1 0

Reset

This command initializes the display start line, the column address, the page address, the common output mode, the V5 voltage regulator internal resistor ratio, the electronic volume, and the static indicator are reset, and the read/modify/write mode and test mode are released. There is no impact on the display data RAM. See the function explanation in “Reset” for details. The reset operation is performed after the reset command is entered.

E R/W

A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 1 0

The initialization when the power supply is applied must be done through applying a reset signal to the RES terminal. The reset command must not be used instead. Common Output Mode Select

This command can select the scan direction of the COM output terminal. For details, see the function explanation in “Common Output Mode Select Circuit.”

Selected Mode E R/W A0 /RD/ WR

D7 D6 D5 D4 D3 D2 D1 D0

1/65duty 1/49duty 1/33duty 1/55duty 1/53duty

0 1 0 1 1 0 0 0 * * * 1

Normal Reverse

COM0→COM63COM63→COM0


COM0→COM31 COM31→COM0



* Disabled bit

Column address

Read-modify-write mode set

N N+1 N+2 N+3 N+m N

End

Return

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Ver 1.0a 37/56 2002/06/24

Power Controller Set

This command sets the power supply circuit functions. See the function explanation in “The Power Supply Circuit,” for details

E R/W

A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0

Selected Mode 0 0 1 0 1 0

1 Booster circuit: OFF Booster circuit: ON

0 1

Voltage regulator circuit: OFFVoltage regulator circuit: ON 0 1 0

0 1

Voltage follower circuit: OFF Voltage follower circuit: ON

V5 Voltage Regulator Internal Resistor Ratio Set

This command sets the V5 voltage regulator internal resistor ratio. For details, see the function explanation is “The Voltage Regulator circuit " and table 11 .

E R/W

A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0

Rb/Ra Ratio

0 1 0

0 0 1 0 0 0 0 0 0 0 1 0 1 0 ↓ 1 1 1 1 1 1

Small

↓

Large The Electronic Volume (Double Byte Command)

This command makes it possible to adjust the brightness of the liquid crystal display by controlling the LCD drive voltage V5 through the output from the voltage regulator circuits of the internal liquid crystal power supply. This command is a two byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other.

The Electronic Volume Mode Set

When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. Once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released.

E R/W

A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 0 0 0 0 1

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Ver 1.0a 38/56 2002/06/24

Electronic Volume Register Set

By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V5 assumes one of the 64 voltage levels. When this command is input, the electronic volume mode is released after the electronic volume register has been set.

E R/W

A0 RD WR

D7 D6 D5 D4 D3 D2 D1 D0

| V5 |

0 1 0

* * 0 0 0 0 0 1 * * 0 0 0 0 1 0 * * 0 0 0 0 1 1

↓ * * 1 1 1 1 1 0 * * 1 1 1 1 1 1

Small

↓

Large * Inactive bit When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0)

The Electronic Volume Register Set Sequence

Figure 26

Static Indicator (Double Byte Command)

This command controls the static drive system indicator display. The static indicator display is controlled by this command only, and is independent of other display control commands. This is used when one of the static indicator liquid crystal drive electrodes is connected to the FR terminal, and the other is connected to the FRS terminal. A different pattern is recommended for the static indicator electrodes than for the dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes. The static indicator ON command is a double byte command paired with the static indicator register set command, and thus one must execute one after the other. (The static indicator OFF command is a single byte command.)

Static Indicator ON/OFF

When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static indicator ON command has been entered, no other command aside from the static indicator register set command can be used. Th is mode is c leared when data is set in the register by the stat ic indicator reg is ter set command.

E R/W

A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0

Static Indicator

0 1 0 1 0 1 0 1 1 0 0 1

OFF ON

electronic volume mode set

electronic volume register set

Set complete ?

YES

NO Electronic volume mode clear

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Ver 1.0a 39/56 2002/06/24

Static Indicator Register Set

This command sets two bits of data into the static indicator register, and is used to set the static indicator into a blinking mode.

E R/W A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0

Indicator Display State

0 1 0 * * * * * * 0 0

0 1 1 0 1 1

OFF ON (blinking at approximately one second intervals) ON (blinking at approximately 0.5 second intervals) ON (constantly on)

* Disabled bit Static Indicator Register Set Sequence

Figure 27

Power Save (Compound Command)

When the display all points ON is performed while the display is in the OFF mode, the power saver mode is entered, thus greatly reducing power consumption. The power saver mode has two different modes: the sleep mode and the standby mode. When the static indicator is OFF, it is the sleep mode that is entered. When the static indicator is ON, it is the standby mode that is entered. In the sleep mode and in the standby mode, the display data is saved as is the operating mode that was in effect before the power saver mode was initiated, and the MPU is still able to access the display data RAM. Refer to figure 28 for power save off sequence.

Figure 28

Static indicator mode set

Static indicator register set

Set complete ?

YES

NO Static indicator mode clear

Static indicator OFF

Display OFF

Display all point ON

Sleep mode

Power save OFF Display all point OFF

Static indicator ON (2 bytes)

Sleep mode cancel

Static indicator ON

Display OFF

Display all point ON

Standby mode

Power save OFF ( Display all point OFF )

Standby mode cancel

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Ver 1.0a 40/56 2002/06/24

Sleep Mode

This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows: 1. The oscillator circuit and the LCD power supply circuit are halted. 2. All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VDD level. Standby Mode

The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode. 1 The LCD power supply circuits are halted. The oscillator circuit continues to operate. 2 The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs output a VDD level. The static drive system does not operate. When a reset command is performed while in standby mode, the system enters sleep mode. * When an external power supply is used, it is recommended that the functions of the external power supply circuit be stopped

when the power saver mode is started. For example, when the various levels of liquid crystal drive voltage are provided by external resistive voltage dividers, it is recommended that a circuit be added in order to cut the electrical current flowing through the resistive voltage divider circuit when the power saver mode is in effect. The ST7565 series chips have a liquid crystal display blanking control terminal /DOF. This terminal enters an “L” state when the power saver mode is launched. Using the output of /DOF, it is possible to stop the function of an external power supply circuit.

* When the master is turned on, the oscillator circuit is operable immediately after the powering on. NOP

Non-OPeration Command

E R/W

A0 /RD / WR

D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 1 1

Test

This is a command for IC chip testing. Please do not use it. If the test command is used by accident, it can be cleared by applying a “L” signal to the /RES input by the reset command or by using an NOP.

E R/W

A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 1 * * * *

* Inactive bit Note: The ST7565 maintain their operating modes until something happens to change them. Consequently, excessive

external noise, etc., can change the internal modes of the ST7565 . Thus in the packaging and system design it is necessary to suppress the noise or take measure to prevent the noise from influencing the chip. Moreover, it is recommended that the operating modes be refreshed periodically to prevent the effects of unanticipated noise.

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Ver 1.0a 41/56 2002/06/24

Table 16: Table of ST7565 Commands

Command Code Command

A0 /RD /WR

D7 D6 D5 D4 D3 D2 D1 D0 Function

(1) Display ON/OFF 0 1 0 1 0 1 0 1 1 1 0 1

LCD display ON/OFF 0: OFF, 1: ON

(2) Display start line set 0 1 0 0 1 Display start address Sets the display RAM display start line address

(3) Page address set 0 1 0 1 0 1 1 Page address Sets the display RAM page address

(4) Column address set upper bit Column address set lower bit

0 1 0 0 1 0

0 0 0 1 Most significant column address

0 0 0 0 Least significantcolumn address

Sets the most significant 4 bits of the display RAM column address.Sets the least significant 4 bits of the display RAM column address.

(5) Status read 0 0 1 Status 0 0 0 0 Reads the status data

(6) Display data write 1 1 0 Write data Writes to the display RAM

(7) Display data read 1 0 1 Read data Reads from the display RAM

(8) ADC select 0 1 0 1 0 1 0 0 0 0 0 1

Sets the display RAM address SEG output correspondence 0: normal, 1: reverse

(9) Display normal/ reverse 0 1 0 1 0 1 0 0 1 1 0

1

Sets the LCD display normal/ reverse 0: normal, 1: reverse

(10) Display all points ON/OFF 0 1 0 1 0 1 0 0 1 0 0

1

Display all points 0: normal display 1: all points ON

(11) LCD bias set 0 1 0 1 0 1 0 0 0 1 0 1

Sets the LCD drive voltage bias ratio 0: 1/9 bias, 1: 1/7 bias (ST7565)

(12) Read/modify/write 0 1 0 1 1 1 0 0 0 0 0 Column address increment At write: +1 At read: 0

(13) End 0 1 0 1 1 1 0 1 1 1 0 Clear read/modify/write

(14) Reset 0 1 0 1 1 1 0 0 0 1 0 Internal reset

(15) Common output mode select 0 1 0 1 1 0 0 0 * * *

1

Select COM output scan direction0: normal direction 1: reverse direction

(16) Power control set 0 1 0 0 0 1 0 1 Operating mode

Select internal power supply operating mode

(17) V5 voltage regulator internal resistor ratio set

0 1 0 0 0 1 0 0 Resistor ratio

Select internal resistor ratio(Rb/Ra) mode

(18) Electronic volume mode set

Electronic volume register set

0 1 0 1 0 0 0 0 0 0 1 0 0 Electronic volume value

Set the V5 output voltage electronic volume register

(19) Static indicator ON/OFF

Static indicator register set

0 1 0 1 0 1 0 1 1 0 0

1 0 0 0 0 0 0 Mode

0: OFF, 1: ON Set the flashing mode

(20) Power saver Display OFF and display all points ON compound command

(21) NOP 0 1 0 1 1 1 0 0 0 1 1 Command for non-operation

(22) Test 0 1 0 1 1 1 1 * * * * Command for IC test. Do not use this command

(Note) *: disabled data

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Ver 1.0a 42/56 2002/06/24

CCOOMMMMAANNDD DDEESSCCRRIIPPTTIIOONN Instruction Setup: Reference

(1) Initialization Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG pin) and V1 and V4 (COM pin) are output through the LCD driving output pins SEG and COM. When electric charge is remaining in the smoothing capacitor connecting between the LCD driving voltage output pins (V1 ~ V5) and the VDD pin, the picture on the display may become totally dark instantaneously when the power is turned on. To avoid occurrence of such a failure, we recommend the following flow when turning on the power. 1. When the built-in power is being used immediately after turning on the power: * The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing

capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below.

*1: Description of functions; Resetting circuit *2: Command description; LCD bias setting *3: Command description; ADC selection *4: Command description; Common output state selection *5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of

the V5 voltage *6: Description of functions; Power circuit & Command description; Electronic volume control *7: Description of functions; Power circuit & Command description; Power control setting

Turn ON the power and keeping the /RES pin = “L”.

When the power is stabilized

Release the reset state. (/RES pin = “H”)

This concludes the initialization

Function setup by command input (User setup) (16) Power control setting *7

Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V5 voltage *5 (18) Electronic volume control *6

Function setup by command input (User setup) (11) LCD bias setting *2 (8) ADC selection *3 (15) Common output state selection *4

Initialized state (Default) *1

Arrange to execute all theprocedures from releasing thereset state through setting thepower control within 5ms. (In case of other models)execute the procedures fromturning on the power to settingthe power control in 5ms.

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Ver 1.0a 43/56 2002/06/24

2. When the built-in power is not being used immediately after turning on the power: * The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing

capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below. *1: Description of functions; Resetting circuit *2: Command description; LCD bias setting *3: Command description; ADC selection *4: Command description; Common output state selection *5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V5

voltage *6: Description of functions; Power circuit & Command description; Electronic volume control *7: Description of functions; Power circuit & Command description; Power control setting *8: The power saver ON state can either be in sleep state or stand-by state.

Command description; Power saver START (multiple commands)

Turn ON the VDD-VSS power keeping the /RES pin = “L”.

When the power is stabilized

Release the reset state. (/RES pin = “H”)

Power saver OFF *8

Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V5 voltage *5 (18) Electronic volume control *6

Function setup by command input (User setup) (11) LCD bias setting *2 (8) ADC selection *3 (15) Common output state selection *4

Power saver START (multiple commands) *8

Initialized state (Default) *1

Arrange to start thepower saver within5ms after releasing thereset state. (In case ofother models) executethe procedures fromturning on the powerto setting the powercontrol in 5ms.

Function setup by command input (User setup) (16) Power control setting *7

This concludes the initialization

Arrange to start powercontrol setting within5ms after turning OFFthe power saver.

ST7565

Ver 1.0a 44/56 2002/06/24

(2) Data Display Notes: Reference items

*9: Command Description; Display start line set *10: Command Description; Page address set *11: Command Description; Column address set *12: Command Description; Display data write *13: Command Description; Display ON/OFF

Avoid displaying all the data at the data display start (when the display is ON) in white. (3) Power OFF *14 Notes: Reference items

*14: The logic circuit of this IC’s power supply VDD - VSS controls the driver of the LCD power supply VDD - V5. So, if the power supply VDD - VSS is cut off when the LCD power supply VDD - V5 has still any residual voltage, the driver (COM. SEG) may output any uncontrolled voltage. When turning off the power, observe the following basic procedures: • After turning off the internal power supply, make sure that the potential V5 ~ V1 has become below the threshold voltage of the LCD panel, and then turn off this IC’s power supply (VDD - VSS). 6. Description of Function, 6.7 Power Circuit

*15: After inputting the power save command, be sure to reset the function using the /RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (20) Power Save

*16: After inputting the power save command, do not reset the function using the /RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (20) Power Save

Function setup by command input (User setup) (2) Display start line set *9 (3) Page address set *10 (4) Column address set *11

Function setup by command input (User setup) (6) Display data write *12

End of data display

Function setup by command input (User setup) (1) Display ON/OFF *13

End of initialization

Function setup by command input (User setup) (20) Power save *15

VDD – VSS power OFF

Reset active (/RES pin = “L”)

Optional status Set the time (tL) from resetactive to turning off the VDD -VSS power (VDD - VSS = 1.8V)longer than the time (tH) whenthe poten t ia l o f V 5 ~ V1becomes below the thresholdvoltage (approximately 1V) ofthe LCD panel. For tH, refer tothe <Reference Data> of thisevent. When tH is too long,insert a resistor between V5and VDD to reduce it.

ST7565

Ver 1.0a 45/56 2002/06/24

Refresh

It is recommended to turn on the refresh sequence regularly at a specified interval.

Precautions on Turning off the power

<Turning the power (VDD - VSS) off> 1) Power Save (The LCD powers (VDD - V5) are off.) → Reset input → Power (VDD - VSS) OFF • Observe tL > tH. • When tL < tH, an irregular display may occur. Set tL on the MPU according to the software. tH is determined according to the external capacity C2 (smoothing capacity of V5 ~ V1) and the driver’s discharging capacity.

Reset command or NOP command

Refreshing of DRAM

Set all commands to the ready state

Refresh sequence

ResetPower save

Power Off

tL

1.8V

VDD

VDD

tH

V1V2V3V4V5

COM

SEG

VDD

RES

About 1V:below Vth of the LCD Panel

Since the power (VDD-VSS) is cut off,theoutput comes not to be fixed.

ST7565

Ver 1.0a 46/56 2002/06/24

<Turning the power (VDD - VSS) off : When command control is not possible.> 2) Reset (The LCD powers (VDD - VSS) are off.) → Power (VDD - VSS) OFF • Observe tL > tH. • When tL < tH, an irregular display may occur. For tL, make the power (VDD - VSS) falling characteristics longer or consider any other method. tH is determined according to the external capacity C2 (smoothing capacity of V5 to V1) and the driver’s discharging

capacity. <Reference Data>

V5 voltage falling (discharge) time (tH) after the process of operation → power save → reset. V5 voltage falling (discharge) time (tH) after the process of operation → reset.

Figure 29

Reset Power Off

tL

1.8V

VDD

VDD

tH

V1V2V3V4V5

COM

SEG

VDD

RES

About 1V:below Vth of the LCD Panel

Since the power (VDD-VSS) is cut off,theoutput comes not be fixed.

5.0

4.0

3.0

2.4

1.8

1.00.50

50

100

VDD-VSS(V)

C2 : V1 to V5 capacity (uF)

V5 voltage falling time (mSec)

ST7565

Ver 1.0a 47/56 2002/06/24

AABBSSOOLLUUTTEE MMAAXXIIMMUUMM RRAATTIINNGGSS Unless otherwise noted, VSS = 0V

Table 17 Parameter Symbol Conditions Unit

Power Supply Voltage VSS –0.3 ~ +6.0 V

Power supply voltage (VDD standard) VSS2 –2.0 ~ -6.0 V

Power supply voltage (VDD standard) V5, VOUT –20.0 ~ +0.3V V

Power supply voltage (VDD standard) V1, V2, V3, V4 V5 to +0.3 V

Input voltage VIN –0.3 to VDD + 0.3 V

Output voltage VO –0.3 to VDD + 0.3 V

Operating temperature TOPR –40 to +85 °C Storage temperature

TCP Bare chip TSTR –55 to +100

–55 to +125 °C

Figure 30

Notes and Cautions

1. The VSS2, V1 to V5 and VOUT are relative to the VDD = 0V reference. 2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VDD ≧ V1 ≧ V2 ≧ V3 ≧ V4 ≧ V5. 3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is

recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the LSI outside of these conditions may not only result in malfunctions of the LSI, but may have a negative impact on the LSI reliability as well.

VDD

VSS2,V1 to V4

V5.,VOUT

VDD

VSS

VCC

GND

System (MPU) side ST7565 chip side

ST7565

Ver 1.0a 48/56 2002/06/24

DDCC CCHHAARRAACCTTEERRIISSTTIICCSS Unless otherwise specified, VSS = 0 V, VDD = 3.0 V ± 10%, Ta = –40 to 85°C

Table 18 Rating Item Symbol Condition Min. Typ. Max. Units Applicable

Pin

Operating Voltage (1) Vss -5.5 — -4.0 V Vss*1

Operating Voltage (2) VSS2 (Relative to VDD) –5.5 — –2.0 V VSS2

–13.0 — –4.0 V5 *2

0.4 x V5 — VDD V1, V2 Operating Voltage (3) VSS2 (Relative to VDD)

V5 — 0.6 x V5

V

V3, V4

High-level Input Voltage VIHC 0.8 x VDD — VDD V *3

Low-level Input Voltage VILC VSS — 0.2 x VDD V *3

High-level Output Voltage VOHC IOH = –0.5 mA 0.8 x VDD — VDD V *4

Low-level Output Voltage VOLC IOL = 0.5 mA VSS — 0.2 x VDD V *4

Input leakage current ILI VIN = VDD or VSS –1.0 — 1.0 μA *5

Output leakage current ILO VIN = VDD or VSS –3.0 — 3.0 μA *6

V5 = –13.0 V — 2.0 3.5 Liquid Crystal Driver ON

Resistance RON Ta = 25°C (Relative To VDD)

V5 = –8.0 V — 3.2 5.4 KΩ SEGn

COMn *7

Static Consumption Current ISSQ — 0.01 2 μA VSS, VSS2

Output Leakage Current I5Q

V5 = –13.0 V(Relative To VDD)

— 0.01 10 μA V5

Input Terminal Capacitance CIN Ta = 25°C , f = 1 MHz — 5.0 8.0 pF Internal

Oscillator fOSC 17 20 24 kHz *8 Oscillator Frequency External

Input fCL 1/65 duty , Ta = 25°C

17 20 24 kHz CL

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Ver 1.0a 49/56 2002/06/24

Table 19

Rating Item Symbol Condition Min. Typ. Max. Units Applicable Pin

Input voltage VSS2 (Relative To VDD) –5.5 — –2.0 V VSS2 Supply Step-up output

voltage Circuit VOUT (Relative To VDD) –18.0 — — V VOUT

Voltage regulator Circuit Operating

Voltage VOUT (Relative To VDD) –18.0 — –6.0 V VOUT

Voltage Follower Circuit Operating

Voltage V5 (Relative To VDD) –13.0 — –4.0 V V5 * 9 In

tern

al P

ower

Base Voltage VRS Ta = 25°C , (Relative To VDD)–0.05%/°C –2.04 –2.10 –2.16 V *10

• Dynamic Consumption Current : During Display, with the Internal Power Supply OFF Current consumed by total ICs

when an external power supply is used . Table 20

Rating Test pattern Symbol Condition Min. Typ. Max. Units Notes

Display Pattern OFF IDD VDD = 5.0 V,

V5 – VDD = –11.0 V — 4 12 μA *11

Display Pattern Checker IDD VDD = 5.0 V,

V5 – VDD = –11.0 V — 7 21 μA *11

• Dynamic Consumption Current : During Display, with the Internal Power Supply ON

Table 21 Rating Test pattern Symbol Condition Min. Typ. Max. Units Notes

Normal Mode — 70 110 Display

Pattern OFF IDD VDD = 5.0 V,

Quad step-up voltage. V5 – VDD = –11.0 V High-Power Mode — 90 150

μA *12

Normal Mode — 95 130 Display Pattern Checker

IDD VDD = 5.0 V,

Quad step-up voltage. V5 – VDD = –11.0 V High-Power Mode — 130 180

μA *12

• Consumption Current at Time of Power Saver Mode : VSS = -5.0 V ± 10%

Table 22 Rating Item Symbol Condition Min. Typ. Max. Units Notes

Sleep mode IDD Ta = 25°C — 0.01 2 Standby Mode IDD Ta = 25°C — 4 8

μA

ST7565

Ver 1.0a 50/56 2002/06/24

• The Relationship Between Oscillator Frequency fOSC, Display Clock Frequency fCL and the Liquid Crystal Frame

Rate Frequency fFR Table 23

Item fCL fFR

Used internal oscillator circuit fOSC / 4 fOSC / (4*65) 1/65 DUTY

Used external display clock External input (fCL) fCL / 260








Used external display clock External input (fCL) fCL / 212 (fFR is the liquid crystal alternating current period, and not the FR signal period.) References for items market with * *1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden

fluctuations to the voltage while the MPU is being accessed. *2 The operating voltage range for the VDD system and the V5 system is. This applies when the external power supply is

being used. *3 The A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), /WR (R/W), /CS1, CS2, CLS, CL, FR, M/S, C86, P/S,/DOF, /RES, IRS, and

/HPM terminals.

*4 The D0 to D7, FR, FRS,/DOF, and CL terminals. *5 The A0, /RD (E), /WR (R/W), /CS1, CS2, CLS, M/S, C86, P/S,/RES, IRS, and/ HPM terminals. *6 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and /DOF terminals are in a high impedance state. *7 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the

various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage (3) range. RON = 0.1 V /ΔI (Where ΔI is the current that flows when 0.1 V is applied while the power supply is ON.)

*8 See Table 23 for the relationship between the oscillator frequency and the frame rate frequency. *9 The V5 voltage regulator circuit regulates within the operating voltage range of the voltage follower. *10 This is the internal voltage reference supply for the V5 voltage regulator circuit. In the ST7565-0A , the temperature range

approximately –0.15%/°C. *11, 12 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on.

The ST7565 is 1/9 biased. Does not include the current due to the LCD panel capacity and wiring capacity. Applicable only when there is no access from the MPU.

*12 It is the value on a ST7565-0A having the VREG temperature gradient is –0.15%/°C when the V5 voltage regulator internal resistor is used.

ST7565

Ver 1.0a 51/56 2002/06/24

TTIIMMIINNGG CCHHAARRAACCTTEERRIISSTTIICCSS System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)

Figure 37

Table 24

(VDD = 4.5 V to 5.5 V, Ta =25°C) Rating Item Signal Symbol Condition Min. Max. Units

Address hold time tAH8 0 —

Address setup time tAW8 0 —

System cycle time

A0

tCYC8 240 —

Enable L pulse width (WRITE) tCCLW 80 —

Enable H pulse width (WRITE) /WR

tCCHW 80 —

Enable L pulse width (READ) tCCLR 140 —

Enable H pulse width (READ) /RD

tCCHR 80

WRITE Data setup time tDS8 40 —

WRITE Address hold time tDH8 0 —

READ access time tACC8 CL = 100 pF — 70

READ Output disable time

D0 to D7

tOH8 CL = 100 pF 5 50

ns

*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.

*2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between /CS1 being “L” (CS2 = “H”) and/WR and /RD being at the “L” level.

tAH8tAW8

tCYC8

tCCLR,tCCLW

tCCHR,tCCHW

tDS8

tACC8 tOH8

tDH8

CS1(CS2="1")

WR,RD

A0

D0 to D7(Write)

D0 to D7(Read)

ST7565

Ver 1.0a 52/56 2002/06/24

System Bus Read/Write Characteristics 2 (For the 6800 Series MPU)

Figure 38

Table 25

(VDD = 4.5 V to 5.5 V, Ta = 25°C ) Rating Item Signal Symbol Condition Min. Max. Units

Address hold time tAH6 0 —

Address setup time tAW6 0 —

System cycle time

A0

tCYC6 240 —

Enable L pulse width (WRITE) tEWLW 80 —

Enable H pulse width (WRITE) /WR

tEWHW 80 —

Enable L pulse width (READ) tEWLR 80 —

Enable H pulse width (READ) /RD

tEWHR 140

WRITE Data setup time tDS6 40 —

WRITE Address hold time tDH6 0 —

READ access time tACC6 CL = 100 pF — 70

READ Output disable time

D0 to D7

tOH6 CL = 100 pF 5 50

ns

*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,

(tr +tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and E.

tAH6tAW6

tCYC6

tCCLR,tCCLW

tCCHR,tCCHW

tDS6

tACC6 tOH6

tDH6

CS1(CS2="1")

E

A0R/W

D0 to D7(Write)

D0 to D7(Read)

ST7565

Ver 1.0a 53/56 2002/06/24

The Serial Interface

Figure 39

Table 26 (VDD = 4.5 V to 5.5 V, Ta =25°C )

Rating Item Signal Symbol Condition Min. Max. Units

Serial Clock Period tSCYC 400 — SCL “H” pulse width tSHW 120 — SCL “L” pulse width

SCL tSLW 120 —

Address setup time tSAS 50 — Address hold time

A0 tSAH 50 —

Data setup time tSDS 50 — Data hold time

SI tSDH 50 —

CS-SCL time tCSS 50 — CS-SCL time

CS tCSH 150 —

ns

*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.

tCSH

CS1(CS2="1")

A0

SI

SCL

tCCSS

tSAS tSAH

tSCYC

tSLW

tSHW

tSDHtSDS

tftr

ST7565

Ver 1.0a 54/56 2002/06/24

Reset Timing

Figure 41

Table27

(VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C ) Rating Item Signal Symbol Condition Min. Typ. Max. Units

Reset time tR — — 0.5 μsReset “L” pulse width RES tRW 0.5 — — μs

*1 All timing is specified with 20% and 80% of VDD as the standard.

Internalstatus

tRW

tR

During reset Reset complete

RES

ST7565

Ver 1.0a 55/56 2002/06/24

TTHHEE MMPPUU IINNTTEERRFFAACCEE ((RREEFFEERREENNCCEE EEXXAAMMPPLLEESS)) The ST7565 Series can be connected to either 80X86 Series MPUs or to 68000 Series MPUs. Moreover, using the serial interface it is possible to operate the ST7565 series chips with fewer signal lines. The display area can be enlarged by using multiple ST7565 Series chips. When this is done, the chip select signal can be used to select the individual ICs to access. (1) 8080 Series MPUs

Figure 42-1

(2) 6800 Series MPUs

Figure 42-2

(3) Using the Serial Interface

Figure 42-3

A0

A1 to A7IORQ

DO to D7RDWRRES

VCC

GND

MPU

A0

CS2

DO to D7RDWRRES

VDD

VSS

ST7565

CS1Decoder

RESET

C86

P/S

VDD

VSS

A0

A1 to A15VMA

DO to D7E

R/WRES

VCC

GND

A0

CS2

DO to D7ER/WRES

VDD

VSS

CS1Decoder

RESET

C86

P/S

VDD

VSS

MPU

ST7565

A0

A1 to A7

Port 1Port 2RES

VCC

GND

A0

CS2

SISCLRES

VDD

VSS

CS1Decoder

RESET

C86

P/S

VDD or VSS

VSS

MPU

ST7565

ST7565

Ver 1.0a 56/56 2002/06/24

Revisions Version 0.4 - Page 16 Modify Figure 4.

- Page 55 Add Revisions page. Version 0.5 - Page 1 Modify FEATURES.

- Page 2 Modify PIN DIMENSIONS. - Page 3~6 Modify Pad Center Coordinates. - Page 7,10 Modify PIN DESCRIPTIONS. - Page 18 Modify Table 6. - Page 22~27 Modify The Voltage Regulator Circuit.

Version 0.6 - Page 2 Modify PIN DIMENSIONS. Version 0.7 - Page 4,5 Modify PAD CENTER COORDINATES Version 0.8 - Page 7 Add new page for BLOCK DIAGRAM - Page 12 Modify PIN OPTION TERMUNALS

- Page 13 Modify Table 2 - Page 31 Modify "the built-in power is not used" and "when the V/F circuit alone is used" - Page 51 Modify Table 25

Version 0.9 - Cancel master/slave mode . Modify DC characteristics Version 0.9a - Reference Circuit Examples(2” & 1.4” panel) Version 0.9b - Modify Reference Circuit C1,C2 value Version 0.9c - Modify page 30 Version 0.9d - Modify page 29 Version 1.0a - Modify Logic power supply VDD – VSS = 4.0V to 5.5V, VOUT= -18V

ST Sitronix ST7565 - HP InfoTech · 2019-10-21 · ST Sitronix ST7565 65 x 132 Dot Matrix LCD...

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