Mohsen Hassanpourghadi, Qiaochu Zhang, Praveen Sharma ......Tony Levi, Mike Chen, Sandeep Gupta...
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Mohsen Hassanpourghadi, Qiaochu Zhang, Praveen Sharma, Jaewon Nam, Shiyu Su, Subhajit Chowdhury, Jagannathan Sathyamoorthy, Walter Unglaub, Mutian Zhu Tony Levi, Mike Chen, Sandeep Gupta University of Southern California ERI Design: USC POSH Automated Analog Mixed Signal (AMS) IP generator for CMOS technologies FA8650-18-2-7853 Under contract June 25, 2018. Phase IA completed June 24, 2019 1 ERI Detroit meeting 3.40pm, Wednesday July 17, 2019
Transcript of Mohsen Hassanpourghadi, Qiaochu Zhang, Praveen Sharma ......Tony Levi, Mike Chen, Sandeep Gupta...
Mohsen Hassanpourghadi, Qiaochu Zhang, Praveen Sharma, Jaewon Nam, Shiyu Su, Subhajit Chowdhury, Jagannathan Sathyamoorthy, Walter Unglaub, Mutian Zhu
Tony Levi, Mike Chen, Sandeep Gupta
University of Southern California
ERI Design: USC POSH
Automated Analog Mixed Signal (AMS) IP generator for CMOS technologiesFA8650-18-2-7853
Under contract June 25, 2018. Phase IA completed June 24, 2019
1
ERI Detroit meeting
3.40pm, Wednesday July 17, 2019
2
Public open-source USC POSH repository, https://github.com/USCPOSH
USC POSH Group
Local optimization & retargeting
Sanitizer
Categories
AMPSE
Tools
Other
Collaborations
Regression tool
Known Good Designs
AMS_KGD
DARPA
Traversing NDA-protected and NDA-free zones
NDA protected PDK information NDA protected PDK information
USC
AMPSE
PDK
sanitizer
Clearance
check
PDK
model
User intentFinal netlist
with PDK info.
Open-source IP
netlist w/o PDK
info
Download
open-source IP
Open-source
cloud repository
USC
AMS
Gen.
PDK
model
PDK
desanitizer
User Intent
Final netlist
with PDK info.
Open-source IP developer perspective Open-source IP user perspective
Regression
model
USC
AMPSE
Other design
environment
or
PDK
sanitizer
NDA-free Zone
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Public open-source USC POSH repository, https://github.com/USCPOSH
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DARPA
Traversing NDA-protected and NDA-free zones with sanitization
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Sanitization
Netlist with PDK information (GF65)
Sanitized Netlist
Eliminating PDK information
(NMOS / PMOS)
Netlist with PDK information
Sanitized Netlist
Adding PDK information
necessary for accurate
simulations
Desanitization
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Public open-source USC POSH repository, https://github.com/USCPOSH
DARPA
Database
𝐅Spice
Final Netlist
Generation
Module Library
Generation
Exploration using
Regression Model
Spice 𝐅
𝐅Python
𝐅Spice
User Intent
Database
Design Spec.Designer knowledgeDesign PrioritiesDesign Constraints
Designer knowledge
Known-Good-Design
LocalOptimization
IP validation(TRUST)
Analog Mixed-signal Parameter Search Engine (AMPSE) Design Flow
Expand AMS Design Space beyond single specification/technologyfor open-source (including Xyce) ecosystem
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https://github.com/USCPOSH
SAR Logic
Size(DF)
Size(INV) Speed
PowerSize(SC)
Size(NAND)
Size(NOR)
Comparator
Size(DF)
Size(INV)
Size(INV_COMP)
Size(LATCH_COMP)
Speed
Power
Noise
Size(NAND_COMP)
Size(NAND)
Size(NOR)
S/H and DAC
Size(SC)
Size(SS)
Size(DF)
Fs
Fin
SFDR
SNDR
BW
Size(SS)
Size(DF)
Fin
Fs
Size(SC) SFDR
SDR
Size(LATCH-COMP)
Size(INV)
Size(INV_COMP)
Size(DF)
Size(NAND-COMP)
Size(NAND)
Size(NOR)Power
Noise
Size(INV)
Size(DF)
Size(NAND)
Size(NOR)
Size(SC)
Speed
AMPSE design: SAR ADC
Access broad range of design objectives
(1) ∑ TCOMP,k + (N-1)∙Max{ TRS, TDAC } < 75% Tperiod
(2) SFDR > SFDRtarget
(3) SNDR > SNDRtarget
~10X speed difference
~16X resolutiondifference
• 50MS/s 10-bit SAR ADC
• 150MS/s 8-bit SAR ADC
• 450MS/s 6-bit SAR ADC
Let’s try these…
(4) …
Formulate corresponding constraints function for AMPSE
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Use AMPSE for 10-bit ADC (schematic level)
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Parameter search process: 10-Bit SAR ADC design
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Parameter search process: 10-Bit SAR ADC design
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Parameter search process: 10-Bit SAR ADC design
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• 50MS/s, 10-bit SAR ADC
SPICE validation of AMPSE design (schematic level)
Performance Metric AMPSE design SPICE Simulation
ENOB 9.14 8.5
SFDR 80.7dB(T/H Module) 60.15dB
Power Consumption 2.4mW 3.8mW
Performance Metric AMPSE design SPICE Simulation
ENOB 7.9 7.6
SFDR 70.76dB(T/H Module) 54.12dB
Power Consumption 4.43mW 6.7mW
• 450MS/s, 6-bit SAR ADC
Performance Metric AMPSE design SPICE Simulation
ENOB 5.9 5.3
SFDR 58.2dB(T/H Module) 41.2dB
Power Consumption 10.9mW 12.6mW
• 150MS/s, 8-bit SAR ADC
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ERI Design: USC POSH
Automated Analog Mixed Signal (AMS) IP generator for CMOS technologiesFA8650-18-2-7853
Under contract June 25, 2018. Phase IA completed June 24, 2019
15
ERI Detroit meeting
3.40pm, Wednesday July 17, 2019
USC POSH repository, https://github.com/USCPOSH
The views, opinions and/or findings expressed are those of the authors and should not be interpreted as representing the official views or policies
of the Department of Defense or the U.S. Government.
