MICRO CONTROLLER DAS

8/7/2019 MICRO CONTROLLER DAS

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GHATKESAR, HYDERABAD

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Micro Controller Based analog 8 channel Data Acquisition System 1

A PROJECT REPORT ON MICROCONTROLLER BASED

EIGHT CHANNEL ANALOG DATA ACQUISTION SYSTEM AT

INSTRUMENTATION SECTION

NUCLEAR FUEL COMPLEX

HYDERABAD

UNDER THE GUIDANCE OF

SHRI V.NAGA BHASKAR

MANAGER (IMS F)

SUBMITTED BY

A.ROHIT REDDY

M.YASEEN HUSSAIN

M.V.N.R.SUDHEER

ELECTRONICS AND COMPUTER ENGINEERING(EComp.E)

SREENIDHI INSTITUTE OF SCIENCE AND TECHNOLOGY


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NUCLEAR FUEL COMPLEX

GOVERNMENT OF INDIA

HYDERABAD

BONAFIDE CERTIFICATE

THIS IS TO CERTIFY THATA.ROHIT REDDY 07311A1940

M.YASEEN HUSSAIN 07311A1907

M.V.N.R. SUDHEER -07311A1934

HAVE DONE THEIR FINAL YEAR PROJECT UNDER MY GUIDANCE DURING THE

PERIOD FROM 15-12-2010 TO 31-01-2011 IN NUCLEAR FUEL COMPLEX.

IT IS ENSURED THAT THE REPORT DOES NOT CONTAIN CLASSIFIED OR PLANT

OPERATIONAL DATA IN ANY FORM AND SUCH DATA IS NOT GIVEN TO THESTUDENTS.

PLACE: HYDERABAD

DATE:

Signature :

Name :

Designation :

Office Seal :

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We take immense pleasure in thanking the management of NFC for having permitted me

to carry out this project work.

We wish to express our deep sense of gratitude to our Project Guide, Shri V.NAGA

BHASKAR, Manager, IMS-F, NFC. His guidance and motivation has helped us in

carrying out the project work efficiently and effectively.

Mr.RAMA KRISHNA , Scientific Officer-C, IMS, who had constantly monitored our

work and inspired us to develop a scientific thinking. It wouldnt have been possible to

complete the project without his able guidance.

We would express our heartfelt thanks to the Supervisor and Operating Staff in the CFFP

and------ for their great cooperation and support.

Their experience has taught us many things apart from the project. It was a great

experience to work in NFC, and we are looking forward to work here again, if given an

opportunity.

A.ROHIT REDDY

M.YASEEN HUSSAIN

M.V.N.R SUDHEER

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Table of contents

I Introduction

1.0 Data Acquistion system

2.0 Principle of operation

3.0 Block Diagram

4.0 Functional description

4.1 Micro controller

4.2 Analog to Digital converter TC7109A

4.3 LCD

4.4 Precision Centigrade Temperature Sensors LM35

4.5 Multiplexer CD4051B

4.6 Power Supply

4.7 Differential Bus Transreceiver SN75176

4.8 MAX 232 Serial Level Converter

4.9 Modbus Protocol

5.0 Software

6.0 Schematic Diagram

7.0 Conclusions and Recommendations

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8.0 References

CHAPTER 1

INTRODUCTION

As technology advancements take place, we seek for better methods to operate our plants and

thus improve upon our processes. Data acquisitionis the process of sampling

signals that measure real world physical conditions and converting the resultingsamples into digital numeric values that can be manipulated by a computer.The

components of data acquisition systems include:

Sensors that convert physical parameters to electrical signals.

Signal conditioning circuitry to convert sensor signals into a form that can be converted

to digital values.

Analog-to-digital converters, which convert conditioned sensor signals to digital values.

The data acquisition systems thus become essential part of any automated system.Consider the

following five components when building a data acquisition system.

Source:

Data acquisition begins with the physical phenomenon orphysical property to be

measured. Examples of this include temperature, light intensity, gas pressure, fluid flow,

and force. Regardless of the type of physical property to be measured, the physical state

that is to be measured must first be transformed into a unified form that can be sampled

by a data acquisition system. The task of performing such transformations falls on

devices called sensors. DAQ systems also employ various signal conditioning techniques

to adequately modify various different electrical signals into voltage that can then be

digitized using an Analog-to-digital converter(ADC).

Signals:

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http://en.wikipedia.org/wiki/Physical_phenomenonhttp://en.wikipedia.org/wiki/Physical_propertyhttp://en.wikipedia.org/wiki/Signal_conditioninghttp://en.wikipedia.org/wiki/Analog-to-digital_converterhttp://en.wikipedia.org/wiki/Physical_phenomenonhttp://en.wikipedia.org/wiki/Physical_propertyhttp://en.wikipedia.org/wiki/Signal_conditioninghttp://en.wikipedia.org/wiki/Analog-to-digital_converter


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Signals may be digital (also called logic signals sometimes) oranalog depending on

the transducer used.

DAQ Hardware: DAQ hardware is what usually interfaces between the signal and a PC.

It could be in the form of modules that can be connected to the computer's ports (parallel,

serial, USB, etc.) or cards connected to slots in the mother board. DAQ cards often

contain multiple components (multiplexer, ADC, DAC, TTL-IO, high speed timers,

RAM). These are accessible via a bus by a microcontroller, which can run small

programs. A controller is more flexible than a hard wired logic, yet cheaper than a CPU

so that it is alright to block it with simple polling loops. For example: Waiting for a

trigger, starting the ADC, looking up the time, waiting for the ADC to finish, move value

to RAM, switch multiplexer, get TTL input, let DAC proceed with voltage ramp. Many

times reconfigurable logic is used to achieve high speed for specific tasks and Digital

signal processors are used after the data has been acquired to obtain some results. The

fixed connection with the PC allows for comfortable compilation and debugging

DAQ software: It is needed in order for the DAQ hardware to work with a PC. Software

transforms the pc and the data acquisition hardware into complete

acquisition,analysis,presentation tool.Driver software is the layer of software for easily

communicating with the hardware. It prevents a programmer from having to do register

level programming or complicated commands to access the hardware functions.

2.0 Principle of operation:

The proposed DAS project digitizes eight analog inputs by using multiplexer and A/D converter.

These digitized analog samples processed and transmitted through RS485 serial bus using

MODBUS protocol. The 89C51 core microcontroller will be used to run and control these

activities.the observations will be displayed on LCD or PC using MODSCAN software.. A

crystal oscillator circuit is used to synchronize all the frequencies. The frequency of crystal

oscillator used is 11.0592MHZ. In order to initialize all the internal register and operations a reset

circuit is used. This reset circuit is done in the programming. As the micro controller needs +5V

dc, this supply is obtained from the power supply circuit consists of a step down transformer and

two diodes which acts as rectifiers and a regulator to get an output voltage of +5V. This +5V is

given to the micro controller

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http://en.wikipedia.org/wiki/Digitalhttp://en.wikipedia.org/wiki/Analog_signalhttp://en.wikipedia.org/wiki/Parallel_porthttp://en.wikipedia.org/wiki/Serial_porthttp://en.wikipedia.org/wiki/USB_porthttp://en.wikipedia.org/wiki/Mother_boardhttp://en.wikipedia.org/wiki/Bushttp://en.wikipedia.org/wiki/Microcontrollerhttp://en.wikipedia.org/wiki/Digital_signal_processorhttp://en.wikipedia.org/wiki/Digital_signal_processorhttp://en.wikipedia.org/wiki/Cross_compilerhttp://en.wikipedia.org/wiki/Debugginghttp://en.wikipedia.org/wiki/Digitalhttp://en.wikipedia.org/wiki/Analog_signalhttp://en.wikipedia.org/wiki/Parallel_porthttp://en.wikipedia.org/wiki/Serial_porthttp://en.wikipedia.org/wiki/USB_porthttp://en.wikipedia.org/wiki/Mother_boardhttp://en.wikipedia.org/wiki/Bushttp://en.wikipedia.org/wiki/Microcontrollerhttp://en.wikipedia.org/wiki/Digital_signal_processorhttp://en.wikipedia.org/wiki/Digital_signal_processorhttp://en.wikipedia.org/wiki/Cross_compilerhttp://en.wikipedia.org/wiki/Debugging


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.

3.0 Functional Description

3.1 8 Bit Micro controller (89C51):

3.1.1 Introduction

Looking back into the history of microcomputers, one would first come across the

development of microprocessor that is the processing element, and later on the peripheral devices.

The three basic elements-the CPU, I/O devices and memory-have developed in d

directions. While the CPU has been the proprietary item, the memory devices fall into general-purpose category and the I/O devices may be grouped somewhere in-between.

Micro controllers:

Figure shows the block diagram of a typical micro controller, which is a true computer on a chip.

The design incorporates all of the features in a microprocessor CPU ALU, PC, SP, and registers.

It also has added the other features needed to make a complete computer. ROM, RAM, parallel

I/O, serial I/O, counters and a clock circuit.

Like the microprocessor, the micro controller is a general purpose device that is meant to read

data, program limited calculations. The prime use of a micro controller is to control the operation

of a machine using a fixed program that is stored in ROM and that does not change over the

lifetime of the system.

The micro controller design uses a much more limited set of single and double byte instructions,

which are used to move code and data from internal memory to the ALU. Many instructions are

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coupled with pins on the integrated circuit package; the pins are programmable that is, capable

of having several different functions depending on the wishes of the programmer.

The micro controller is concerned with getting data from and to its own pins; the architecture and

instructions set are optimized to handle data in bit and byte size.

Features:

The P89C51RD2 device contains a non-volatile 64kB Flash program memory that is both parallel

programmable and serial In-System and In-Application Programmable. In-System Programming

(ISP) allows the user to download new code while the microcontroller sits in the application.In-

Application Programming (IAP) means that the microcontroller fetches new program code and

reprograms itself while in the system. This allows for remote programming over a modem link.

A default serial loader (boot loader) program in ROM allows serial In-System programming of

the Flash memory via the UART without the need for a loader in the Flash code. For In-

Application Programming, the user program erases and reprograms the Flash memory by use of

standard routines contained in ROM.This device executes one machine cycle in 6 clock cycles,

hence providing twice the speed of a conventional 80C51. An OTP configuration bit lets the user

select conventional 12 clock timing if desired.This device is a Single-Chip 8-Bit Microcontroller

manufactured in advanced CMOS process and is a derivative of the 80C51 microcontroller

family. The instruction set is 100% compatible with the 80C51 instruction set.

The device also has four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-

priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing

circuits.

The added features of the P89C51RD2 makes it a powerful microcontroller for applications that

require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor

control.

The P89C51RD2 has the following on-chip facilities:

64KB ISP/IAP Flash program memory.

8 bit program counter (PC), data pointer (DPTR), program status word (PSW) and stack

pointer (SP).

Internal ROM or EPROM of 0 to 64K.

Internal RAM of 1KB bytes.

Four register banks each containing 8 registers.

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16 bytes , which may be addressed at bit level.

32 input-output port lines.

Three 16-bit timer/counters.

A full duplex enhanced UART

-Framing error detection

-Automatic Address recognition

Control registers: TCON, TMOD, SCON, PCON, IP and IE.

On-chip clock oscillator and power on reset circuitry.

7 interrupt sources and 4 level priority interrupt

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3.1.2 Internal Block diagram

P89C51 internal block diagram

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The 89C51 can be configured to bypass, the internal 64kB ROM and run solely with

external program memory. For this its external access (EA) pin has to be grounded, which makes

it equivalent to 8031. The program store enable (PSEN) signal acts as read pulse for program

memory. The data memory is external only and a separate RD* signal is available for reading its

contents.

The UART utilizes one of the internal timers for generation of baud rate. The crystal used

for generation of CPU clock has therefore to be chosen carefully. The 11.0592 MHz crystals;

available abundantly, can provide a baud rate of 9600.

The P89C51RB2/RC2/RD2 has internal data memory that is mapped into four separate segments:

1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are

directly and indirectly addressable.

2. The Upper 128 bytes of RAM (addresses 80H to FFH) are

indirectly addressable only.

3. The Special Function Registers, SFRs, (addresses 80H to FFH)

are directly addressable only.

4. The 256/768-bytes expanded RAM (ERAM, 00H 1FFH/2FFH)

are indirectly accessed by move external instruction, MOVX, and with the EXTRAM bit cleared.

The list of special function registers along with their hex addresses is given .

Table 4.3 P89C51 Address register

Address Port/Register

80 P0 (Port 0)

81 SP (stack pointer)

82 DPH (data pointer High)

83 DPL (data pointer Low)

88 TCON (timer control)

89 TMOD (timer mode)

8A TLO (timer 0 low byte)

8B TL1 (timer 1 low byte)

8C TH0 (timer 0 high byte)

8D TH1 (timer 1 high byte)

90 P1 (port 1)

98 SCON (serial control)

99 SBUF (serial buffer)

A0 P2 (port 2)

A8 Interrupt enable (IE)

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B0 P3 (port 3)

B8 Interrupt priority (IP)

D0 Processor status word (PSW)

E0 Accumulator (ACC)

F0 B register

Table 4.3.1 P89C51RD2 SFR

P89C51 Serial port pins

PIN ALTERNATE USE SFR

P3.ORXD Serial data input SBUF

P3.ITXD Serial data output SBUF

P3.2INTO External interrupt 0 TCON-1

P3.3INT1 External interrupt 1 TCON- 2

P3.4TO External timer 0 input TMOD

P3.5T1 External timer 1 input TMODP3.6WR External memory write pulse ---------

P3.7RD External memory read pulse ----

Table 4.4.1 P89C51 serial port pins

Reset:

A high on this pin for two machine cycles while the oscillator is running,

resets the device. An internal resistor to VSS permits a power-on reset using only

an external capacitor to VCC.

3.1.4 In-System Programming (ISP):

The In-System Programming (ISP) is performed without removing the microcontroller from the

system. The In-System Programming (ISP) facility consists of a series of internal hardware

resources coupled with internal firmware to facilitate remote programming of

P89C51RB2/RC2/RD2 through the serial port. This firmware is provided by Philips and

embedded within each P89C51RB2/RC2/RD2 device.

The ISP function uses five pins: TxD, RxD, VSS, VCC, and VPP . Only a small connector needs

to be available to interface your application to an external circuit in order to use this feature .The

VPP supply should be adequately decoupled and VPP not allowed to exceed datasheet limits.

The ISP feature allows for a wide range of baud rates to be used in your application, independent

of the oscillator frequency. It is also adaptable to a wide range of oscillator frequencies. This is

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accomplished by measuring the bit-time of a single bit in a received character. This information

is then used to program the baud rate in terms of timer counts based on the oscillator frequency.

The ISP feature requires that an initial character (an uppercase U) be sen

P89C51RB2/RC2/RD2 to establish the baud rate. The ISP firmware provides auto-echo of

received characters.

Once baud rate initialization has been performed, the ISP firmware will only accept Intel Hex-

type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values

and are summarized below:

:NNAAAARRDD..DDCC

In the Intel Hex record, the NN represents the number of data bytes in the record. The

P89C51RB2/RC2/RD2 will accept up to 16(10H) data bytes. The AAAA string represents the

address of the first byte in the record. If there are zero bytes in the record, this field is often set to

0000. The RR string indicates the record type. A record type of 00 is a data record. A record

type of 01 indicates the end-of-file mark. In this application, additional record types will

be added to indicate either commands or data for the ISP facility.The maximum number of data

bytes in a record is limited to 16 (decimal).

WinISP, a software utility to implement ISP programming with a PC,is available from Philips.

Commercial serial ISP programmers are available from third parties.

Dual DPTR:

The dual DPTR structure is a way by which the chip will specify the address of an external data

memory location. There are two 16-bit DPTR registers that address the external memory, and a

single bit called DPS = AUXR1/bit0 that allows the program code to switch between them.

New Register Name: AUXR1#

SFR Address: A2H

Reset Value: xxxxxxx0B

AUXR1 (A2H):

7 6 5 4 3 2 1 0

Where:

DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.

Select Reg DPS

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- - ENBOOT - GF2 0 - DPS


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DPTR0 0

DPTR1 1

The DPS bit status should be saved by software when switching between DPTR0 and DPTR1.

The GF2 bit is a general purpose user-defined flag. Note that bit 2 is not writable and is always

read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC

AUXR1 instruction without affecting the GF2 bit.

Flags and program status word:

Flags are bit wise registers provided to store the results of certain program instructions. Other

instructions can test the conditions of the flag and make decisions based on the flag states. The

flags are grouped inside the PSW and the power control (PCON) registers. The 89C51 has 4

mathematical flags which include carry (CF), Auxiliary carry (AC),Over flow(OF) and Parity(P)

and three general purpose user flags which can be set to one or cleared to zero by the

programmer.

Stack and stack pointer:

The stack refers to an area of internal RAM that is used in conjunction with certain opcodes to

store and retrieve data quickly. The 8-bit stack pointer (SP) register is used by micro controller to

hold an internal RAM address, that is called the top of the stack.

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3.1.5Pin Description

VCC

Supply voltage.

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GND

Ground.

Port 0:

Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and

can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data

bus during accesses to external program and data memory. In this application, it uses strong

internal pull-ups when emitting 1s.

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups The Port 1 output buffers

can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the

internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled

low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order

address bytes during Flash programming and verification.

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers

can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the


low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address

byte during fetches from external program memory and during accesses to external data memory

that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups

when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @

RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-

order address bits and some control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can

sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the


low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various

special features of the P89C51 as listed below: Port 3 also receives some control signals for

Flash programming and verification.

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ALE/PROG

Address Latch Enable (ALE) output pulse for latching the low byte of the address during accesses

to external memory. This pin is also the program pulse input (PROG) during Flash Programming.

In normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency, and may be

used for external timing or clocking purposes. Note, however, that one pulse is skipped during

each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0

of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction.

Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has noEffect if the micro

controller is in external execution mode.

PSEN

Program Store Enable (PSEN) is the read strobe to external program memory. When the

AT89C51 is executing code from external program memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access to external data

memory.

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code

from external program memory locations starting at 0000H up to FFFFH. Note, however, that if

lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC

for internal program executions. This pin also receives the 12-volt programming enable voltage

(VPP) during Flash programming, for parts that require 12-volt VPP.

XTAL1

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Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Oscillator and clock circuit:

The heart of the micro controller is the crystal oscillator that generates the clock pulses by which

all internal operations are synchronized. Pins XTAL1 and XTAL2 are provided for connection of

the resonant network to form an oscillator.

The clock frequency F, establishes the smallest internal time within the micro controller called

the pulse time. The smallest internal time to accomplish any simple instruction, or the part of

complex instruction be the machine cycle.The time to execute the instruction is obtained by

Tinst = No of cycles x12d

Crystal frequency

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier, which can

be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or

ceramic resonator may be used. To drive the device from an external clock source, XTAL2

should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no

requirements on the duty cycle of the external clock signal, since the input to the internal clocking

circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low

time specifications must be observed.

Specifying Quartz Crystals

Counters and Timers:

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Three 16 bit microprocessor counters named T0 and T1 and T2 are provided for the general use

of the programmer. Each counter may be programmed to count internal clock pulses acting as a

timer or programmed to count external pulses as counter. The counters are divided into two 8-bit

registers called the timer low (TL0, TL1) and high (TH0, TH1) bytes. All counter action is

controlled by bit states in the time mode control register (TMOD), the timer/counter control

register (TCON) and certain program instructions.

TMOD is dedicated solely to the two timers and can be considered to be two duplicate four bit

registers each of which controls the action of one of the TCON has control bits and flags for

timers in upper nibble and for timers external interrupts in lower nibble.

Serial data Input/Output:

Onecost effective way to communicate with other computers is to send and receive data bits

serially. The 89C51 has a serial data communication circuit but uses register SBUF to hold data.

Register SCON controls data communication and register PCON controls data rates and pins

RXD (P3.0) and TXD(P3.1) connect to the serial data network. SBUF is physically two registers.

One is write only and used to hold data to be transmitted out of the micro controller using TXD.

The other is read only and hold- receive data from external sources using RXD.

Interrupts:

The P89C51RB2/RC2/RD2 has a 7 source four-level interrupt structure.There are 3 SFRs

associated with the four-level interrupt. They are the IE, IP, and IPH. The IPH (Interrupt

Priority High) register makes the four-level interrupt structure possible. The IPH is located at

SFR address B7H. The function of the IPH SFR, when combined with the IP SFR,determines the

priority of each interrupt.

The priority of each interrupt is determined as shown in the following table

IPH.x

PRIORITYBITS

IP.x

PRIORITYBITS

Interrupt

priority level

0 0 Level 0

(low

priority )0 1 Level 1

1 0 Level 2

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1 1 Level 3

(high

priority)

Interrupts may be generated by the internal chip operations or provided by external sources. Fiveinterrupts are provided in the 89C51.Internal operations timer flag0, timer flag1 and the serial

port generate three of these automatically interrupt (R1 or T1). Two interrupts are triggered by

external signals provided by circuitry which are connected to pins INT0 and INT1.

The priority scheme for servicing the interrupts is the same as that for the 80C51, except there are

four interrupt levels rather than two as on the 80C51. An interrupt will be serviced as long as an

interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher

level priority is being serviced, the new interrupt will wait until it is finished before beingserviced. If a lower priority level interrupt is being serviced, it will be stopped and the new

interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was

stopped will be completed.

3.2 Analog to Digital converter TC7109A:

Description:

The ICL7109 is a high performance, CMOS, low power integrating A/D converter designed to

easily interface with microprocessors and micro controllers.The output data (12 bits, polarity and

over-range) may be directly accessed under control of two byte enable inputs and a chip select

input for a single parallel bus interface. A UART handshake mode is provided to allow the

ICL7109 to work with industry-standard UARTs in providing serial data transmission. The

RUN/HOLD input and STATUS output allow monitoring and control of conversion timing.

The ICL7109 provides the user with the high accuracy, low noise, low drift versatility and

economy of the dual-slope integrating A/D converter. Features like true differential input and

reference, drift of less than 1V/oC, maximum input bias current of 10pA, and typical power

consumption of 20mW make the ICL7109 an attractive per-channel alternative to analog

multiplexing for many data acquisition applications.

Features:

12-Bit Binary (Plus Polarity and Over-Range) Dual Slope Integrating Analog-to-Digital

Converter

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Byte-Organized, TTL Compatible Three-State Outputs and UART Handshake Mode for Simple

Parallel or Serial Interfacing to Microprocessor Systems

RUN/HOLD Input and STATUS Output Can Be Used to Monitor and Control Conversion

Timing.

True Differential Input and Differential Reference

Low Noise (Typ) . . . . . . . . . . . . . . . . . . . . . . . . 15[VP-P]

Input Current (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . .1pA

Operates At Up to 30 Conversions/s

On-Chip Oscillator Operates with Inexpensive 3.58MHz

TV Crystal Giving 7.5 Conversions/s for 60Hz Rejection.May Also Be Used with An RC

Network Oscillator for other clock frequencies.

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Oscillator:

The ICL7109 is provided with a versatile three terminal oscillator to generate the internal clock.

The oscillator may be overdriven, or may be operated with an RC network or crystal. The

OSCILLATOR SELECT input changes the internal configuration of the oscillator to optimize it

for RC or crystal operation.

When the OSCILLATOR SELECT input is high or left open (the input is provided with a pullup

resistor), the oscillator is configured for RC operation, and the internal clock will be of the same

frequency and phase as the signal at the BUFFERED OSCILLATOR OUTPUT. The circuit will

oscillate at a frequency given by f = 0.45/RC. A 100k resistor is recommended for useful ranges

of frequency. For optimum 60Hz line rejection, the capacitor value should be chosen such that

2048 clock periods is close to an integral multiple of the 60Hz period (but should not be less than

50pF).When the OSCILLATOR SELECT input is low a feedback device and output and input

capacitors are added to the oscillator If at any time the oscillator is to be overdriven, the

overdriving signal should be applied at the OSCILLATOR INPUT, and the OSCILLATOR

OUTPUT should be left open. The internal clock will be of the same frequency, duty cycle, and

phase as the input signal when OSCILLATOR SELECT is left open.

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Mode input:

The MODE input is used to control the output mode of the converter. When the MODE pin is low

or left open the converter is in its Direct output mode, where the output data is directly

accessible under the control of the chip and byte enable inputs. When the MODE input is pulsed

high, the converter enters the UART handshake mode and outputs the data in two bytes, then

returns to direct mode. When the MODE input is left high, the converter will output data in the

handshake mode at the end of every conversion cycle.

Direct Mode:

When the MODE pin is left at a low level, the data outputs (bits 1 through 8 low order byte, bits 9

through 12, polarity and over-range high order byte) are accessible under control of the byte and

chip enable terminals as inputs. These three inputs are all active low, and are provided with

pullup resistors to ensure an inactive high level when left open. When the chip enable input is

low, taking a byte enable input low will allow the outputs of that byte to become active (three-

stated on).This allows a variety of parallel data accessing techniques to be used,It should be noted

that these control inputs are asynchronous with respect to the converter clock - the data may be

accessed at any time. Thus it is possible to access the latches while they are being updated, which

could lead to erroneous data. Synchronizing the access of the latches with the conversion cycle by

monitoring the STATUS output will prevent this. Data is never updated while STATUS is low.

RUN/HOLD INPUT:

When the Run/Hold input is tied high,the ICL7109 continuously performs A/D conversions with

a fixed length of 8192 clock cycles per conversion.When Run/Hold is taken low,the ICL7109 will

complete the conversion in progress,then wait in the autozero phase.After the minimum autozero

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time has been completed,a high going pulse on Run/Hold of atleast 200 nanoseconds is required

to start anew conversion;but any pulses during a conversion or upto 2048 clock cycles after Status

goes low will be ignored.If the ICL 7109 is holding at the end of the autozero phase,a new

conversion will start and status will go high within 7 clock cycles after Run/Hold goes high.

Test Input

When the TEST input is taken to a level halfway between V+ and GND, the counter output

latches are enabled, allowing the counter contents to be examined anytime.When the RUN/HOLD

is low and the TEST input is connected to GND, the counter outputs are all forced into the high

state, and the internal clock is disabled. When the RUN/HOLD returns high and the TEST input

returns to the 1/2 (V+ - GND) voltage (or to V+) and one clock is applied,all the counter outputs

will be clocked to the low state. This allows easy testing of the counter and its outputs.

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3.3 LCD (LIQUID CRYSTAL DISPLAY)

An intelligent LCD display of two lines, 16 characters per line is interfaced

microcontroller. The protocol for the display is shown below.

G +5V-5V +5V G

D0 D1 D2 D3 D4 D5 D6 D7 RS R/W EN

The display contains two internal byte-wide registers, one for commands (RS=0) and the second

for characters to be displayed (RS=1). It also contains a user-programmed RAM area(the

character RAM) that can be programmed to generate any desired character that can be formed

using a dot matrix. To distinguish between these two data areas, the hex command byte 80 will be

used to signify that the display RAM address 00h is chosen.

Port1 is used to furnish the command or data byte, and ports 3.2 to 3.4 furnish register select and

read/write levels.

LCDs can add a lot to your application in terms of providing an useful interface for the

user, debugging an application or just giving it a "professional" look. The most common type of

LCD controller is the Hitachi 44780, which provides a relatively simple interface between a

processor and an LCD. In experienced designers do often not attempt using this interface and

programming because it is difficult to find good documentation on the interface, initializing the

interface can be a problem and the displays themselves are expensive.

Pins Description

1 Ground

2 Vcc

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1 2 3 15

7 8 9 10 11 12 13 14 4 5

TWO LINES X 16 CHARACTERS

INTELLIGENT LCD DISPLAY


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3 Contrast Voltage

4 "R/S" _Instruction/Register Select

5 "R/W" _Read/Write LCD Registers

6 "E" Clock

7 14 Data I/O Pins

The interface is a parallel bus,

allowing simple and fast reading/writing

of data to and from the LCD.

This waveform will write an

ASCII Byte out to the LCD's screen. The

ASCII code to be displayed is eight bits

long and is sent to the LCD either four or eight bits at a time. If four bit mode is used, two

"nibbles" of data (Sent high four bits and then low four bits with an "E" Clock pulse with each

nibbles) are sent to make up a full eight bit transfer. The "E" Clock is used to initiate the data

transfer within the LCD.

Sending parallel data as either four or eight bits are the two primary modes of operation.

While there are secondary considerations and modes, deciding how to send the data to the LCD is

most critical decision to be made for an LCD interface application.

Eight-bit mode is best used when speed is required in an application and at least ten I/O

pins are available. Four bit mode requires a minimum of six bits. To wire a micro controller to an

LCD in four bit mode, just the top four bits (DB4-7) are written to.

The "R/S" bit is used to select whether data or an instruction is being transferred between

the micro controller and the LCD. If the Bit is set, then the byte at the current LCD "Cursor"

Position can be read or written. When the Bit is reset, either an instruction is being sent to the

LCD or the execution status of the last instruction is read back (whether or not it has completed).

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The different instructions available for use with the 44780 are shown in the table below:

R/S R/W D7 D6 D5 D4 D3 D2 D1 D0 Instruction/Description

4 5 14 13 12 11 10 9 8 7 Pins

0 0 0 0 0 0 0 0 0 1 Clear Display0 0 0 0 0 0 0 0 1 * Return Cursor and LCD to Home Position

0 0 0 0 0 0 0 1 ID S Set Cursor Move Direction

0 0 0 0 0 0 1 D C B Enable Display/Cursor

0 0 0 0 0 1 SC RL * * Move Cursor/Shift Display

0 0 0 0 1 DL N F * * Set Interface Length

0 0 0 1 A A A A A A Move Cursor into CGRAM

0 0 1 A A A A A A A Move Cursor to Display

0 1 BF * * * * * * * Poll the "Busy Flag"

1 0 D D D D D D D DWrite a Character to the Display at the Current

Cursor Position

1 1 D D D D D D D DRead the Character on the Display at the Current

Cursor Position

Reading Data back is best used in applications which required data to be moved back and

forth on the LCD (such as in applications which scroll data between lines). The "Busy Flag" can

be polled to determine when the last instruction that has been sent has completed processing. In

most applications, just tie the "R/W" line to ground because I don't read anything back. This

simplifies the application because when data is read back, the micro controller I/O pins have to be

alternated between input and output modes.

For most applications, there really is no reason to read from the LCD. I usually tie "R/W"

to ground and just wait the maximum amount of time for each instruction (4.1 milliseconds for

clearing the display or moving the cursor/display to the "home position", 160 microseconds for

all other commands). As well as making my application software simpler, it also frees up a micro

controller pin for other uses. Different LCDs execute instructions at different rates and to avoid

problems later on (such as if the LCD is changed to a slower unit), I recommend just using the

maximum delays given above.

The LCD can be thought of as a "Teletype" display because in normal operation, after a

character has been sent to the LCD, the internal "Cursor" is moved one character to the right. The

"Clear Display" and "Return Cursor and LCD to Home Position" instructions are used to reset the

Cursor's position to the top right character on the display.

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To move the Cursor, the "Move Cursor to Display" instruction is used. For this

instruction, bit 7 of the instruction byte is set with the remaining seven bits used as the address of

the character on the LCD the cursor is to move to. These seven bits provide 128 addresses, which

matches the maximum number of LCD character addresses available. The table above should be

used to determine the address of a character offset on a particular line of an LCD display.

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The Character Set available in the 44780 is basically ASCII. I say "basically" because

some characters do not follow the ASCII convention fully (probably the most significant

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difference is 0x05B or "\" is not available). The ASCII Control Characters (0x008 to 0x01F) do

not respond as control characters and may display funny (Japanese) characters.

The last aspect of the LCD to discuss is how to specify a contrast voltage to the Display. I

typically use a potentiometer wired as a voltage divider. This will provide an easily variablevoltage between Ground and Vcc, which will be used to specify the contrast (or "darkness") of

the characters on the LCD screen. You may find that different LCDs work differently with lower

voltages providing darker characters in some and higher voltages do the same thing in others.

There are a variety of different ways of wiring up an LCD. Above, I noted that the 44780

could interface with four or eight bits. To simplify the demands in micro controllers, a shift

register is often used (as is shown in the diagram below) to reduce the number of I/O pins to

three.

In the diagram to the right, I have shown how the shift register is written to for this circuit

to work. Before data can be written to it, the shift register is cleared by loading every latch with

zeros. Next, a "1" (to provide the "E" Gate) is written followed by the "R/S" bit and the four data

bits. Once that is loaded in correctly, the "Data" line is pulsed to Strobe the "E" bit. The biggest

difference between the three wire and two wire interface is that the shift register has to be cleared

before it can be loaded and the two wire operation requires more than twice the number of clock

cycles to load four bits into the LCD.

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3.4 Precision Centigrade Temperature Sensors: LM35

General Description:

The LM35 series are precision integrated-circuit temperature sensors, whose output voltage is

linearly proportional to the Celsius (Centigrade) temperature. The LM35 thus has an advantage

over linear temperature sensors calibrated in Kelvin, as the user is not required to subtract a

large constant voltage from its output to obtain convenient Centigrade scaling. The LM35 does

not require any external calibration or trimming to provide typical accuracies of 14C at room

temperature and 34C over a full 55 to +150C temperature range. The LM35s low output

impedance,linear output, and precise inherent calibration make interfacing to readout or control

circuitry especially easy. It can be used with single power supplies, or with plus and minus

supplies. As it draws only 60 A from its supply, it has very low self-heating, less than 0.1C in

still air. The LM35 is rated to operate over a 55 to +150C temperature range.

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FEATURES:

The output voltage is converted to temperature by a simple conversion factor.

The sensor has a sensitivity of 10mV / oC.

Use a conversion factor that is the reciprocal, that is 100 oC/V.

The general equation used to convert output voltage to temperature is:

Temperature ( oC) = Vout * (100 oC/V)

So if Vout is 1V , then Temperature = 100oC

The output voltage varies linearly with temperature.

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Typical Applications:

3.4 MULTIPLEXER CD4051B:

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The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog

switches having low ON impedance and very low OFF leakage current. Control of

analog signals up to 20VP-P can be achieved by digital signal amplitudes of 4.5V to 20V (if

VDD-VSS = 3V, a VDD-VEE of up to 13V can be controlled; for VDD-VEE level

differences above 13V, a VDD-VSS of at least 4.5V is required).

For example, if VDD = +4.5V, VSS = 0V, and VEE = -13.5V, analog signals from -13.5V to

+4.5V can be controlled by digital inputs of 0V to 5V. These multiplexer circuits dissipate

extremely low quiescent power over the full VDD-VSS and VDD-VEE supply-voltage ranges,

independent of the logic state of the control signals. When a logic 1 is present at the inhibit

input terminal, all channels are off.

The CD4051B is a single 8-Channel multiplexer having three binary control inputs, A, B, and C,

and an inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect

one of the 8 inputs to the output. The CD4052B is a differential 4-Channel multiplexer having

two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 of

4 pairs of channels to be turned on and connect the analog inputs to the outputs.

When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the

outputs and the COMMON OUT/IN terminals are the inputs.

Applications:

Analog and Digital Multiplexing and Demultiplexing

A/D and D/A Conversion

Signal Gating

Power Supply

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Power supply unit provides 5V regulates power supply to the systems. It consists of two parts

namely,

1. Rectifier

2. Monolithic voltage regulator

Rectifier:

Here the step down transformer 230-0v/12-0-12V gives the secondary current up to 500mA, to

the Rectifier. The secondary Transformer is provided with a center tap. Hence the voltage V1

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and V2 are equal and are having a phase difference of 180 0. So it is anode of Diode D1 which is

positive with respect to the center tap, the anode of the other diode d2 will be negative with

respect to the center tap. During the positive half cycle of the supply D1 conducts and current

flows through the center tap D1 and load. During this period D2 will not conduct as its anode is

at negative potential. During the negative half cycle of the supply voltage, the voltage on the

diode D2 will be positive and hence D2 conducts. The current flows through the transformer

winding, Diode D2 and load. It is to be noted that the current i1 and i2 are flowing in the same

direction in load.

The average of the two current i1 and i2 flows through the load producing a voltage drop, which

is the D.C. output voltage of the rectifier. Using monolithic IC voltage regulators, voltage can be

regulated.

Monolithic IC voltage regulator:

A voltage regulator is a circuit that supplies a constant voltage regardless of changes in load

currents. Although voltage regulators can be designed using op-amps, it is quicker and easier to

use IC voltage regulators. Furthermore, IC voltage regulators are versatile and relatively

inexpensive and are available with features such as programmable output, current/voltage

boosting, internal short-circuit current limiting, thermal shutdown and floating operation for high

voltage applications

Here 7800 series voltage regulators are used. The 7800 series consists of 3-terminal positive

voltage regulators with seven voltage options. These ICs are designed as fixed voltage regulators

and with adequate heat sinking can deliver output currents in excess of 1A. Although these

devices do not require external components, such components can be used to obtain adjustable

voltages and currents. For proper operation a common ground between input and output voltages

is required. In addition, the difference between input and output voltages (Vi Vo) called drop

out voltage, must be typically 1.5V even during the low point as the input ripple voltage. The

capacitor Ci is required if the regulator is located at an appreciable distance from a power supply

filter. Even though Co is not needed, it may be used to improve the transient response of the

regulator.

Typical performance parameters for voltage regulators are line regulation, lo

regulation, temperature stability and ripple rejection. Line regulation is defined as the change in

output voltage for a change in the input voltage and is usually expressed in milli volts or as a

percentage of Vo. Temperature stability or average temperature coefficient of output voltage

(TCVo) is the change in output voltage per unit change in temperature and is expressed in either

milli volts/C or parts per million (PPM/C). Ripple rejection is the measure of a regulators

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ability to reject ripple voltage. It is usually expressed in decibels. The smaller the values of line

regulation, load regulation and temperature stability better the regulation.

3.5 DIFFERENTIAL BUS TRANSCEIVER SN75176:

SN75176A differential bus transceiver is a monolithic integrated circuit designed for bidirectional

data communication on multipoint bus-transmission lines. It is designed for bala

transmission lines and meets ANSI Standard EIA/TIA-422-B and ITU Recommendation V.11.

The heart of this communication is the Texas Instruments SN75176 Differential Bus Transceiver

chip. This chip converts RS485 signals to RS232 TTL-level signals allowing devices that

traditionally communicate over standard RS232 serial connections to communicate over a single

two-wire RS485 network.

The SN75176B combines a 3-state differential line driver and a differential input line receiver,

both of which operate from a single 5-V power supply. The driver and receiver have active-high

and active-low enables, respectively, that can be externally connected together to function as a

direction control. The driver differential outputs and the receiver differential inputs are connected

internally to form differential input/output (I/O) bus ports that are designed to offer minimum

loading to the bus whenever the driver is disabled or VCC = 0. These ports feature wide positive

and negative common-mode voltage ranges making the device suitable for partyapplications.

The SN75176 chip has only 8 pins Setting RE (Not Receiver Enable) to Low, the R (Receiver)

pin is enabled, allowing the micro contrllerr to receive any data coming over the A and B RS485

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network lines. Setting DE (Driver Enable) to High allows the microcontroller to transmit data

over the RS485 network

3.6 MAX 232 Serial Level Converter:

The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to supply

TIA/EIA-232-F voltage levels from a single 5-V supply. Each receiver converts TIA/EIA-232-F

inputs to 5-V TTL/CMOS levels.These receivers have a typical threshold of 1.3 V, a typical

hysteresis of 0.5 V, and can accept 30-V inputs.Each driver converts TTL/CMOS input levels

into TIA/EIA-232-F levels.

RS-232 TTL Logic------------- ---------------- - ----------

-15V ...-3V +2V ... +5V 1

+3V ... +15V 0V ... +0.8V 0

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Serial RS-232 (V.24) communication works with voltages -15V to +15V for high and low. On

the other hand, TTL logic operates between 0V and +5V . Modern low power consumption logic

operates in the range of 0V and +3.3V or even lower.

Thus the RS-232 signal levels are far too high TTL electronics, and the negative RS-232 voltage

for high cant be handled at all by computer logic. To receive serial data from an RS-232

interfacethe voltage has to be reduced. Also the low andhigh voltage level has to be inverted.

This levelconverteruses a Max232 and five capacitors .

The MAX232 from Maxim was the first IC which in one package contains the necessary

drivers and receivers to adapt the RS-232 signal voltage levels to TTL logic. It became popular,

because it just needs one voltage (+5V or +3.3V) and generates the necessary RS-232 voltage

levels.

3.7 MODICON MODBUS Protocol

Modicon programmable controllers can communicate with each other and with other

devices over a variety of networks. Supported networks include the Modicon Modbus

and Modbus Plus industrial networks, and standard networks such as MAP and

Ethernet.

The common language used by all Modicon controllers is the Modbus protocol.This protocol

defines a message structure that controllers will recognize and use,regardless of the type of

networks over which they communicate. It describes the process a controller uses to request

access to another device, how it will respond to requests from the other devices, and how errors

will be detected and reported. It establishes a common format for the layout and contents of

message fields.

Controllers communicate using a masterslave technique, in which only onedevice (the master)

can initiate transactions (called queries). The other devices (the slaves) respond by supplying

the requested data to the master, or by takingthe action requested in the query. Typical master

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devices include host processors and programming panels. Typical slaves include programmable

controllers.

The master can address individual slaves, or can initiate a broadcast message to all slaves. Slaves

return a message (called a response) to queries that are addressed to them individually.

Responses are not returned to broadcast queries from the master.

At the message level, the Modbus protocol still applies the masterslave principle even though

the network communication method is peertopeer. If a controller originates a message, it does

so as a master device, and expects a response from a slave device. Similarly, when a controller

receives a message it constructs a slave response and returns it to the originating controller.

The QueryResponse Cycle:

The Query: The function code in the query tells the addressed slave device what kind of action

to perform. The data bytes contain any additional information that the slave will need to perform

the function. For example, function code 03 will query the slave to read holding registers and

respond with their contents. The data field must contain the information telling the slave which

register to start at

and how many registers to read. The error check field provides a method for the slave to validate

the integrity of the message contents.

The Response: If the slave makes a normal response, the function code in the response is an

echo of the function code in the query. The data bytes contain the data collected by the slave,

such as register values or status. If an error occurs, the function code is modified to indicate that

the response is an error response, and the data bytes contain a code that describes the error.

The Two Serial Transmission Modes

Controllers can be setup to communicate on standard Modbus networks using either of two

transmission modes: ASCII or RTU. Users select the desired mode,along with the serial port

communication parameters (baud rate, parity mode, etc),during configuration of each controller.

The mode and serial parameters must be the same for all devices on a Modbus network .

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The selection of ASCII or RTU mode pertains only to standard Modbus networks.It defines the

bit contents of message fields transmitted serially on those networks.It determines

information will be packed into the message fields and decoded.

ASCII Mode:

When controllers are setup to communicate on a Modbus network using ASCII(American

Standard Code for Information Interchange) mode, each 8bit byte in a message is sent as two

ASCII characters. The main advantage of this mode is that it allows time intervals of up to one

second to occur between characters

without causing an error.

The format for each byte in ASCII mode is

Coding System: Hexadecimal, ASCII characters 09, AF

One hexadecimal character contained in each

ASCII character of the message

Bits per Byte: 1 start bit

7 data bits, least significant bit sent first

1 bit for even/odd parity; no bit for no parity

1 stop bit if parity is used; 2 bits if no parity

Error Check Field: Longitudinal Redundancy Check (LRC)

RTU Mode:

When controllers are setup to communicate on a Modbus network using RTU (Remote Terminal

Unit) mode, each 8bit byte in a message contains two 4bit hexadecimal characters. The main

advantage of this mode is that its greater character density allows better data throughput than

ASCII for the same baud rate.

Each message must be transmitted in a continuous stream.

The format for each byte in RTU mode is:

Coding System: 8bit binary, hexadecimal 09, AF

Two hexadecimal characters contained in each

8bit field of the message

Bits per Byte: 1 start bit

8 data bits, least significant bit sent first

1 bit for even/odd parity; no bit for no parity

1 stop bit if parity is used; 2 bits if no parity

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Error Check Field Cyclical Redundancy Check (CRC)

Modbus Message Framing:

In either of the two serial transmission modes (ASCII or RTU), a Modbus message is placed by

the transmitting device into a frame that has a known beginning and ending point. This allows

receiving devices to begin at the start of the message,read the address portion and determine

which device is addressed (or all devices,if the message is broadcast), and to know when the

message is completed. Partial messages can be detected and errors can be set as a result.

ASCII Framing

In ASCII mode, messages start with a colon ( : ) character (ASCII 3A hex), and end with a

carriage return line feed (CRLF) pair (ASCII 0D and 0A hex).

The allowable characters transmitted for all other fields are hexadecimal 09, AF. Networked

devices monitor the network bus continuously for the colon character.When one is received,

each device decodes the next field (the address field) to find out if it is the addressed device.

Intervals of up to one second can elapse between characters within the message.

START ADDRESS

FUNCTION DATA

LRC

CHECK END

1CHAR 2 CHARS 2 CHARS N

CHARS

2

CHARS

2

CHARS

CRLF

ASCII MESSAGE FORMAT

RTU Framing

In RTU mode, messages start with a silent interval of at least 3.5 character times.This is most

easily implemented as a multiple of character times at the baud rate that is being used on the

networkThe allowable characters transmitted for all fields are hexadecimal 09, AF.Networked

devices monitor the network bus continuously, including during the silent intervals. When the

first field (the address field) is received, each device decodes it to find out if it is the addressed

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device.The entire message frame must be transmitted as a continuous stream. If a silent

interval of more than 1.5 character times occurs before completion of the frame, the receiving

device flushes the incomplete message and assumes that the next byte will be the address field of

a new message.

Similarly, if a new message begins earlier than 3.5 character times following a previous message,

the receiving device will consider it a continuation of the previous message. This will set an

error, as the value in the final CRC field will not be valid for the combined messages. A typical

message frame is shown below

START ADDRESS

FUNCTIO

N

DATA

LRC

CHECK END

T1-T2-T3-T4 8 BITS 8 BITS N* 8

BITS

16 BITS T1-T2-T3-

T4

RTU MESSAGE FRAME

When RTU mode is used for character framing, the error checking field contains a16bit value

implemented as two 8bit bytes. The error check value is the result of a Cyclical Redundancy

Check calculation performed on the message contents The CRC field is appended to the message

as the last field in the message.

When this is done, the loworder byte of the field is appended first, followed by the

highorder byte. The CRC highorder byte is the last byte to be sent in the

message. When messages are transmitted on standard Modbus serial networks, each

character or byte is sent in this order (left to right):

With RTU character framing, the bit sequence is:

Bit Order(RTU):

With parity checking

start 1 2 3 4 5 6 7 8 par stop

Without parity checking

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4.0 SOFTWARE

/* ------------------------------------------------------------------------------*/

N U O F P - C & I (F) ,NUCLEAR FUEL COMPLEX

PROJECT : MCU BASED ANALOG DATA AQUISITION

MCU : AT89C51

MEMORY : 64 K ROM (PROGRAM MEMORY)

2 K EEPROM (SERIAL)

UTILITY : MCS51 KEIL 'C'COMPILER

VERSION : V0.0

ORGANISATION : SINGLE TASK

START Dt : 15-01-2010

LAST MODIFIED Dt: 26-01-2011 added No parity feature and

LED1 for Rx communication

LED2 for Tx communication

LED1 & 2 Blinking for Error

//features added

- channel data canbe read through func.code 03 Read Input Reg.

- input register address ranges from 0000 to 0007

- Com settings 19200,8 data,1 stop, no parity

------------------------------------------------------------------------- */

#define MY_ADD 1

// FILES INCLUDED

#include

#include //MCU internal

#include //project header

#include // key scan

________________________________________________________________________


start 1 2 3 4 5 6 7 8 stop stop


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//------------------------------------------------------------

/*

void timer1 (void) interrupt 3{

ET1 = 0;

TR1 = 0;

if(!f_dummy_pkt){

f_pkt_ready = 1;

}

else f_dummy_pkt = 0;

rx_state = START;

if(!f_error) po_led1=OFF;

}

*/

//--------------------------------------------------------------------------

void timer0 (void) interrupt 1 using 1{

TL0 = 0xff; //K_TIMER0_LO; /* for 1msec interrupt */

TH0 = 0xf3; // K_TIMER0_HI;

two_msecs_count++;

if(rtu_tout){

rtu_tout--;

if(rtu_tout==0){

if(!f_dummy_pkt){

f_pkt_ready = 1;

}


rx_state = START;

if(!f_error) po_led1=OFF;

}

}

if(msecs_rt) msecs_rt--;

// else msecs_rt = 0;

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Run_adc();

switch(two_msecs_count){

case 1:

case 2:break;

case 3:break;

case 4:

if(f_error){

one_sec_count++;

if(one_sec_count > 20){

one_sec_count=0;

po_led1 = ~po_led1;

po_led2 = ~po_led2;

}

}

break;

case 5:break;

case 6:break;

case 7:break;

case 8:break;

case 9:break;

case 10:

default:two_msecs_count = 0;

}

}

//---------------------------------------------------//

void serial_port_int(void)interrupt 4 using 2 {

unsigned char sbuf;

if(TI){

TI=0;

com_send();

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}

if(RI){

sbuf = SBUF;

com_receive(sbuf);

RI = 0;

}

}

//---------------------------------------------------

void adc_status_isr(void)interrupt 0 using 3{

f_eoc = 1;

po_adc_run = HOLD;

EX0 = 0;

}

//---------------------------------------------------

void initialise(void){

IE = 0; /* disable the interrupts */

P1 = K_P1_DIRECTION;

P3 = K_P3_DIRECTION;

P0 = K_PORT0_DIRECTION; /* direction assignment to the ports */

P2 = K_PORT2_DIRECTION;

msecs_rt = 0;

// TMOD = K_TMOD;

// TCON = K_TCON;

// SCON = K_SCON;

// T2CON = K_T2CON;

// TH2 = RCAP2H = K_RCAP2H;

// TL2 = RCAP2L = K_RCAP2L;

// TL0 = K_TIMER0_LO; /* for 2msec interrupt */

// TH0 = K_TIMER0_HI;

// TL1 = K_TIMER1_LO; /* reload the timer values */

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// IE = K_IE;

adc_run_state = STEP1;

po_adc_run = HOLD;

po_led1 = OFF;

po_led2 = OFF;

po_adc_oebar = 1;

po_485_en = 0;

current_ch = 0;

// IE = K_IE;

// ET1 = 0;

// TR1 = 0;

// ES = 1;

// EA = 1; /* global enable the interrupts */

TCON=0x50;

TMOD=0x21;

SCON=0x50;

TL1=0xFB;

TH1=0xFB;

TH0=0xF3;

TL0=0xFF;

ET0=1;

ES=1;

EA=1;

}

//----------------------------------------------------------//

void main(void){

initialise();

TB8 = 1;

//power on blinking

ES=0;

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f_error = 0;

po_led1 = po_led2 = OFF;

delayms(300);

for(gc1=0; gc1


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} nw_send(19);

}

f_pkt_ready = 0;

}

}

}

}

//-----------------------------------------------------------------------//

void delayms(unsigned int tag){

msecs_rt = tag;

while(msecs_rt);

}

//-----------------------------------------------------------------------//

void Run_adc(void) using 1{

unsigned int a;

switch(adc_run_state){

case STEP1:

P1 &= 0xe0;

P1 |= (15 - current_ch);


break;

case STEP2:

po_adc_run = RUN;

f_eoc = 0;

EX0 = 1;


break;

case STEP3:

if(!f_eoc)break;

po_adc_oebar = 0;

a = ADC_DATA_HI;

a


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a += ADC_DATA_LO;

po_adc_oebar = 1;

a &= 0xfff;

analog_values[current_ch] = a;


break;

case STEP4:

current_ch++;

if(current_ch > 7) current_ch = 0;


break;

}

}

//-----------------------------------------------------------------------//

END OF AI

//------------------------ MODBUS.C------------------------------------

// MODBUS COM ROUTINES IN RTU MODE

//---------------------------------------------------------------------

/*

//MODBUS FUNCTION CODES

#define FC_READ_COIL_STATUS 0X01

-> 01

1st coil add Hi

1st coil add Lo

No.of coils Hi

No.of coils Lo


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--

#define FC_READ_INPUT_STATUS 0X02

-> 02

1st input add Hi

1st input add Lo

No.of inputs Hi

No.of inputs Lo

03

1st Register add Hi

1st Register add Lo

No.of Register Hi (set to 0)

No.of Register Lo

04

1st Register add Hi

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1st Register add Lo

No.of Register Hi (set to 0)

No.of Register Lo

05

coil add Hi

coil add Lo

(High Byte) 0xff = Coil SET or 0x00 = Coil RESET

(Low Byte) Set to 00

06

Reg add Hi

Reg add Lo

New Reg Data(High Byte)

New Reg Data(Low Byte)


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Reg add Hi

Reg add Lo

New Reg Data(High Byte)

New Reg Data(Low Byte)

#define FC_FORCE_MULTIPLE_COILS 0x0F

-> 0F

1st coil add Hi

1st coil add Lo

No. of coils forced Hi

No. of coils force Low

No. of bytes in the Query Data Buffer

Query Data Buffer First Byte

--

--

10

1st Register add Hi

1st Register add Lo

No.of Register Hi

No.of Register Lo

No. of bytes in the Query data buffer

Query data buffer first byte

--

--


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1st Register add Hi

1st Register add Lo

No.of Register Hi

No.of Register Lo

*/

//--------------------------------------------------------//

void com_init(void){

po_485_en = 0;

rx_state = tx_state = START;

combuf_count = 0;

f_dummy_pkt = 0;

f_pkt_ready=0;

f_transmission_over=1;

f_parity_error = 0;

}

//--------------------------------------------------------//

void nw_send(unsigned char length){

get_crc(length);

combuf[length++] = crcHI;

combuf[length++] = crcLO;

combuf_index = 1;

combuf_count = length;


// f_pkt_ready = 0;

delayms(2); //Pkt start 3.5 char

po_485_en=1;


// TB8 = get_even_parity(combuf[0]);

tx_state = START;

TI=0;

SBUF = combuf[0];

po_led2 = ON;

while(!f_transmission_over);

po_led2 = OFF;

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po_485_en = 0;

}

//--------------------------------------------------------//

void com_send(void) using 2 {

switch(tx_state){

case START:

if(combuf_count){

//TB8 = get_even_parity(combuf[combuf_index]);

SBUF = combuf[combuf_index++];

if(combuf_index >= combuf_count) tx_state = STEP1;

}

break;

case STEP1:


combuf_count = 0;

tx_state = START;

// po_485_en = 0;

break;

}

}

//--------------------------------------------------------//

void com_receive(unsigned char scombuf) using 2 {

switch(rx_state){

case START:

if(f_pkt_ready)break;

if(scombuf!=MY_ADD){

f_dummy_pkt = 1;

}


rx_state = STEP1;

if(!f_error) po_led1=ON;

f_parity_error = 0;

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if(!f_dummy_pkt){

combuf[0] = scombuf;

//if(get_even_parity(scombuf) != RB8) f_parity_error = 1;

}

combuf_count = 1;

rtu_tout=5;

// TL1 = K_TIMER1_LO;


// TR1 = 1;

// ET1 = 1;

break;

case STEP1:

// TR1=0;

// TL1 = K_TIMER1_LO;


// TR1=1;

rtu_tout=5;

if(!f_dummy_pkt){

if(combuf_count < INBUF_LIMIT){

combuf[combuf_count++] = scombuf;

//if(get_even_parity(scombuf) != RB8) f_parity_error = 1;

}

}

break;

}

}

//--------------------------------------------------------

bit nw_receive(void){

msecs_rt = RX_TIMOUT;

while(!f_pkt_ready){

if(!msecs_rt)return 0;

}

return 1;

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/*

Calculation of crc for modbus message combuffer.

Arguments:message pointer,length of the message

Return value: unsigned int value or crc (Already swapped) i.e.

ret value can be send HI byte first Low byte next.

*/

/* Table of CRC values for highorder byte */

unsigned char code HItbl[] = {

0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0,

0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,

0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0,

0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,

0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1,

0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,

0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1,

0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,

0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0,

0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40,

0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1,

0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,

0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0,

0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40,

0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0,

0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,

0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0,

0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,

0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0,

0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,

0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0,

0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40,

0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1,

0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,

0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0,

0x80, 0x41, 0x00, 0xC1, 0x81, 0x40

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} ;

/* Table of CRC values for loworder byte */

unsigned char code LOtbl[] = {

0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06,

0x07, 0xC7, 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD,

0x0F, 0xCF, 0xCE, 0x0E, 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09,

0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A,

0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC, 0x14, 0xD4,

0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3,

0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3,

0xF2, 0x32, 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4,

0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A,

0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38, 0x28, 0xE8, 0xE9, 0x29,

0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF, 0x2D, 0xED,

0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,

0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60,

0x61, 0xA1, 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67,

0xA5, 0x65, 0x64, 0xA4, 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F,

0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68,

0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA, 0xBE, 0x7E,

0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5,

0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71,

0x70, 0xB0, 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92,

0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C,

0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E, 0x5A, 0x9A, 0x9B, 0x5B,

0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89, 0x4B, 0x8B,

0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,

0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42,

0x43, 0x83, 0x41, 0x81, 0x80, 0x40

} ;

void get_crc(unsigned char length){

unsigned char index,a;

crcHI = crcLO = 0xff;

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a=0;

while(length--){

index = (crcHI ^ combuf[a]);

a++;

crcHI = (crcLO ^ HItbl[index]);

crcLO = LOtbl[index];

}

}

//--------------------------------------------------------//

END OF MODBUS PROT

//------------------ GNRL_TYP.H --------------------------------

typedef unsigned char T_UINT8;

typedef char T_INT8;

typedef unsigned int T_UINT16;

typedef int T_INT16;

typedef unsigned long T_UINT32;

typedef long int T_INT32;

typedef unsigned char UC;

typedef unsigned int USI;

typedef unsigned long ULI;

enum {FALSE=0,TRUE=1};

enum {OFF=0,ON=1};

END OF GENERAL

________________________________________________________________________



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/* ******************** PROJECT HEADER ******************************** */

#define CRYSTAL 20

#define K_P1_DIRECTION 0xff

#define K_P3_DIRECTION 0xff

#define K_PORT0_DIRECTION 0Xff

#define K_PORT2_DIRECTION 0Xff

//for 1msecs

#define TIMER_COUNT (0XFFFF-0x682)

#define K_TIMER0_LO (unsigned char)(TIMER_COUNT%0X100)

#define K_TIMER0_HI (unsigned char)(TIMER_COUNT/0X100)

//rtu delay for 4msecs

#define RTU_DELAY (0XFFFF-0x1A08)

#define K_TIMER1_LO (unsigned char)(RTU_DELAY%0X100)

#define K_TIMER1_HI (unsigned char)(RTU_DELAY/0X100)

/*

#define RTU_START_DELAY (50000000/K_BAUD)

#define TIMER1_COUNT (0XFFFF-((RTU_START_DELAY*CRYSTAL)/12))

#define K_TIMER1_LO (unsigned char)(TIMER1_COUNT%0X100)

#define K_TIMER1_HI (unsigned char)(TIMER1_COUNT/0X100)

*/

/*

modes 1,3 Baud Rate = Osc.Freq./(32*[65536-RCAP])

RCAP = 65536 - [Osc.Freq/(32*BR)]

*/

//for 19200 baud

#define K_RCAP2H 0xff

_____________________________________________

MICRO CONTROLLER DAS

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