MC1650-DataSheet
Transcript of MC1650-DataSheet
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SEMICONDUCTOR TECHNICAL DATA
4334 REV 5Motorola, Inc. 1996
3/93
The MC1650 and the MC1651 are very high speed comparators utilizing
differential amplifier inputs to sense analog signals above or below a reference
level. An output latch provides a unique sample-hold feature. The MC1650
provides high impedance Darlington inputs, while the MC1651 is a lowerimpedance option, with higher input slew rate and higher speed capability.
The clock inputs (Caand Cb) operate from MECL III or MECL 10,000 digital
levels. When Cais at a logic high level, Q0 will be at a logic high level provided
that V1 V2(V1is more positive than V2). Q0 is the logic complement of Q0.
When the clock input goes to a low logic level, the outputs are latched in their
present state.
Assessment of the performance differences between the MC1650 and the
MC1651 may be based upon the relative behaviors shown in Figures 4 and 7.
PD = 330 mW typ/pkg (No Load) tpd = 3.5 ns typ (MC1650)
= 3.0 ns typ (MC1651)
Input Slew Rate = 350 V/s (MC1650)= 500 V/ s (MC1651)
Differential Input Voltage: 5.0 V (30C to +85C) Common Mode Range:
3.0 V to +2.5 V (30C to +85C) (MC1651)2.5 V to +3.0 V (30C to +85C) (MC1650)
Resolution: 20 mV (30C to +85C) Drives 50 lines
Number at end of terminal denotes pin number for L package (Case 620).
LOGIC DIAGRAM
+
+
V1A6
V2A5
CA4
V1B12
V2B11
CB13
2 Q0
3 Q0
14 Q1
15 Q1
VCC = +5.0 V = PIN 7, 10
VEE = 5.2 V = PIN 8
GND = PIN 1, 16
D Q
Q
D Q
Q
TRUTH TABLE
C V1, V2 Q0n+1 Q0n+1
H V1 V2 H L
H V1 V2 L H
L X X Q0n Q0n
PIN ASSIGNMENT
GND
Q0
Q0
CA
V2A
V1A
VCC
VEE
GND
Q1
Q1
CB
V1B
V2B
VCC
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L SUFFIX
CERAMIC PACKAGE
CASE 62010
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MC1650 MC1651
4335 MOTOROLAMECL Data
DL122 Rev 6
ELECTRICAL CHARACTERISTICS
Test Limits
30C +25C +85C
Characteristic Symbol Min Max Min Max Min Max Unit
Power Supply Drain Current Positive
Negative
ICCIE
25*
55*
mAdc
Input Current MC1650
MC1651
Iin 10
40
Adc
Input Leakage Current MC1650
MC1651
IR 7.0
10.0
Adc
Clock Input Current IinH 350
Output Voltage Logic 1 VOH 1.045 0.875 0.960 0.810 0.890 0.700 Vdc
Output Voltage Logic 0 VOL 1.890 1.650 1.850 1.620 1.830 1.575 Vdc
Threshold Voltage (Note 2.) Logic 1 VOHA 1.065 0.980 0.910 Vdc
Threshold Voltage (Note 2.) Logic 0 VOLA 1.630 1.600 1.555 Vdc
1. All data is for 1/2 MC1650 or MC1651, except data marked (*) which refers to the entire package.2. These tests are done in order indicated. See Figure 5.
3. Maximum Power Supply Voltages (beyond which device life may be impaired): |VEE| + |VCC|
12 Vdc.
4. All Temperature VA3 VA4 VA5 VA6
MC1650 +3.0 +2.98 2.5 2.48
MC1651 +2.5 +2.48 3.0 2.98
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MC1650 MC1651
MOTOROLA MECL DataDL122 Rev 6
4336
ELECTRICAL CHARACTERISTICS(continued)
TEST VOLTAGE VALUES(Volts)
@ Test Temperature VIHmax VILmin VIHAmin VILAmax VA1 VA2 VA3 VA4 VA5 VA6 VCC3. VEE
3.
30C 0.875 1.890 1.180 1.515 +0.02 +0.02 +5.0 5.2
+25C 0.810 1.850 1.095 1.485 +0.02 +0.02 See Note 4. +5.0 5.2
+85C 0.700 1.830 1.025 1.440 +0.02 +0.02 +5.0 5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Characteristic Symbol VIHmax VILmin VIHAmin VILAmax VA1 VA2 VA3 VA4 VA5 VA6
(VCC)Gnd
Power Supply Pos
Drain Current Neg
ICCIE 4,13
4,13 6,12
6,12
1,5,11,16
1,5,11,16
Input Current MC1650
MC1651
Iin 4 13 12 6 1,5,11,16
Input Leakage MC1650
Current MC1651
IR 4 13 12 6 1,5,11,16
Clock Input Current IinH 4 13 6,12 1,5,11,16
Output Voltage Logic 1 VOH 4,13 6,12
5,11
5,11
6,12
6,12
5,11
5,11
6,12
5,11
6,12
6,12
5,11
1,5,11,16
1,6,12,16
1,161,16
1,5,11,16
1,6,12,16
1,16
1,16
Output Voltage Logic 0 VOL 4,13
5,11
6,12
6,12
5,11
5,11
6,12
6,12
5,11
6,12
5,11
5,11
6,12
1,5,11,16
1,6,12,16
1,16
1,16
1,5,11,16
1,6,12,16
1,16
1,16
Threshold Logic 1Voltage
Note 2.
VOHA 13 4
4
4
4
6
6
6
6
1,5,16
Threshold Logic 0
Voltage
Note 2.
VOLA 13 4
4
4
4
6
6
6
6
1,5,16
1. All data is for 1/2 MC1650 or MC1651, except data marked (*) which refers to the entire package.2. These tests are done in order indicated. See Figure 5.3. Maximum Power Supply Voltages (beyond which device life may be impaired): |VEE| + |VCC| 12 Vdc.
4. All Temperature VA3 VA4 VA5 VA6
MC1650 +3.0 +2.98 2.5 2.48
MC1651 +2.5 +2.48 3.0 2.98
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50ohm resistor to 2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.
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MC1650 MC1651
4337 MOTOROLAMECL Data
DL122 Rev 6
MC1651 Inputs
VCC7, 10
Gnd
1
Gnd
16
A
B
C
2 Q
3 Q
4
Clock
RP
8 VEE
D
E
(Both Devices)A
BC
D
E
V1
6
V25
MC1650 Inputs
A
BC
V16
V25
D
E
CIRCUIT SCHEMATIC1/2 of Device Shown
SWITCHING TEST VOLTAGE VALUES
@Test (Volts)
Temperature VR1 VR2 VR3 VX VXX VCC1 VEE
1
30C +2.0 +1.04 +2.0 +7.0 3.2
+25C +2.0 See Note 4 +1.11 +2.0 +7.0 3.2
+85C +2.0 +1.19 +2.0 +7.0 3.2
30C +25C +85C Conditions
Characteristic Symbol Min Max Min Max Min Max Unit (See Figures 13)
Switching Times
Propagation Delay
(50% to 50%) V-Input
tpd
2.0 5.0 2.0 5.0 2.0 5.7
ns VR1to V2, VXto Clock, P1to V1, or,
VR2to V2, VXto Clock, P2to V1, or,
VR3to V2, VXto Clock, P3to V1.
Clock2 2.0 4.7 2.0 4.7 2.0 5.2 VR1to V2, P1to V1and P4to Clock,
or, VR1to V1, P1to V2and P4to Clock.
Clock Enable3 tsetup 2.5 ns
Clock Aperture3 tap 1.5 nsR1 o 2, 1 o 1, 4 o oc
Rise Time (10% to 90%) t+ 1.0 3.5 1.0 3.5 1.0 3.8 ns
Fall Time (10% to 90%) t 1.0 3.0 1.0 3.0 1.0 3.3 nsVRto V2, VXto Clock, P1to V1.
NOTES:
1. Maximum Power Supply Voltages (beyond which device life
may be impaired:
VCC+ VEE 12 Vdc.2. Unused clock inputs may be tied to ground.
3. See Figure 3.
All Temperatures VR2
MC1650 +4.9
MC1651 +4.4
VR3
0.4
0.9
4.
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MC1650 MC1651
MOTOROLA MECL DataDL122 Rev 6
4338
FIGURE 1 SWITCHING TIME TEST CIRCUIT @ 25C
Vinto Channel A
VR1, VR2, VR3
P1P2P3
VX
P4
+
VCC=
+7.0 Vdc
VXX=
+2.0 Vdc
Voutto
Channel B
0.1 F 0.1 F
10 7 1 16
VEE
0.1 F
VEE=
3.2 Vdc
VCC Gnd
D Q
QC
D Q
C Q
Note: All power supply and logic levels are shown shifted 2.0 volts positive.50 ohm termination to ground located in each scope channel input.All input and output cables to the scope are equal lengths of 50 ohm coaxial cable.
+
V INPUT TO OUTPUTCLOCK TO OUTPUT
Vin
Q
50%
tpd
50%
tpd
90%
t+
10%
50%
t
VIH
VR
VIL
Test pulses: t +, t= 1.5 0.2 ns (10% to 90%)f = 5.0 MHz
50% Duty Cycle
P1
Vin
30 ns
P4
C
Q
50%
tpd
50%
40 ns
50%
30 ns
30 ns40 ns
30 ns
tpd
+0.31 V
+1.11 V
VIH+ 2.1 V
VR+ 2.0 V
VIL+ 1.9 V
P4: t +, t= 1.5 0.2 ns.
FIGURE 2 SWITCHING AND PROPAGATION WAVEFORMS @ 25C
The pulse levels shown are used to check ac parameters
over the full common-mode range.
Coax
P1 P2 P3
TEST PULSE LEVELS
VIL
VR
VIH
MC1650 MC1651 MC1650 MC1651 MC1650 MC1651
+2.1 V +2.1 V +5.0 V +4.5 V 0.3 V 0.8 V
+2.0 V +2.0 V +4.9 V +4.4 V 0.4 V 0.9 V
+1.9 V +1.9 V +4.8 V +4.3 V 0.5 V 1.0 V
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4339 MOTOROLAMECL Data
DL122 Rev 6
Vinto Channel A
VEE= 3.2 Vdc8
0.1 F
50
VEE
D
Vin
0.1F
D
10 7
+
Q
Q
C
VR
Q
Q
16
C
Gnd
+
VCC1
Voutto Channel B
0.1F
FIGURE 3 CLOCK ENABLE AND APERTURE TIME TEST CIRCUIT AND WAVEFORMS @ 25C
VinNegative
VinPositive
C
Q Positive
Q Negative
Clock AperatureTime
50%V 1
0
1
V
50%
VR+ 100 mV = +2.1 V
Clock EnableTime
VR= 2.0 V
VR 100 mV = +1.9 V
VIH= +1.11 V
VIL= +0.31 V
0
Clock enable time = minimum time between analog and clock signal such that output switches, and tpd(analog to Q) is not degraded by more than 200 ps.
Clock aperture time = time difference between clock enable time and time that output does not switch andV is less than 150 mV.
Note: All power supply and logic levels are shown shifted 2.0 volts positive.
50%
ANALOG SIGNAL POSITIVE AND NEGATIVE SLEW CASE
50 ohm termination to ground located in each scope channel input.All input and output cables to the scope are equal lengths of 50 ohms coaxial cable.
Vdc VdcVCC= +7.0 VXX= +2.0
tpd
tpd
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MOTOROLA MECL DataDL122 Rev 6
4340
TEST CIRCUIT
POSITIVE PULSE DIAGRAM NEGATIVE PULSE DIAGRAM
PROPAGATION DELAY versusPULSE AMPLITUDE
PROPAGATION DELAY versusOVERDRIVE
FIGURE 4 PROPAGATION DELAY (tpd) versus
INPUT PULSE AMPLITUDE AND CONSTANT OVERDRIVE
Vin
Vref
VIH
50
Vref= Gnd
D Q
1/2 Device
C Q
Q
50502.0 V
PositiveOverdrive
Vref
VinPA
tpd
50%Q
NegativeOverdrive
PBVin
Vref
tpd
Q
Input Switching time is constantat 1.5 ns (10% to 90%).
+
MC1651
MC1650
OVERDRIVE (VOLTS)
0.3 0.5 0.7
1.0
0.04 102.50.07 1.00.20.1
2.0
0.0200.01
MC1650
tpdreferenced to PA, PB= 20 mV
102.51.00.50.20.10.050.020.01
4.0
PULSE AMPLITUDE PA, PB(VOLTS)
0
1.0
2.0
3.0
5.0
Negative Going Pulse
PROPAGATIOND
ELAYINCREASE(ns)
PROPAGATION
DELAYINCREASE(ns)
Overdrive Constant @ 100 mVPositive Going Pulse
tpdis referenced to 2.5 V overdrive.
PA, PB, Constant @ 100 mV
Positive Overdrive (PA)Negative Overdrive (PB)
tpdis measured from Vrefon the inputto 50% on the output.
MC1651
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MC1650 MC1651
4341 MOTOROLAMECL Data
DL122 Rev 6
FIGURE 5 LOGIC THRESHOLD TESTS (WAVEFORM SEQUENCE DIAGRAM)
+0.02 V
0.02 VVin
VIHA
VILA
C
1
0
1
Q
0
Q
1 2 3 4
Sequential
Test Number
(See Test Table)
DifferentialInputVin
+
VIH
Vref
D Q
C Q
Q
50
2.0 Vdc
1/2 Device
2.5 Vdc Vref +2.5 Vdc
+
Q.OUTPUTVOLTAGE(VOLTS)
0
1.0
2.020 15 10 5.0
Vref
5.0 10 15 20
Logic 1
Logic 0
Vin,DIFFERENTIAL INPUT VOLTAGE (mV)
TYPICAL TRANSFER CURVES
FIGURE 6 TRANSFER CHARACTERISTICS (Q versusVin)
TEST CONFIGURATION
Resolution
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MC1650 MC1651
MOTOROLA MECL DataDL122 Rev 6
4342
(A) TEST CIRCUIT
(B) TYPICAL OUTPUT LOGIC SWING versus FREQUENCY
FIGURE 7 OUTPUT VOLTAGE SWING versusFREQUENCY
VIH
V1
V2D Q
C Q
1/2 Device
Q
5050
2.0 Vdc
+
50
FREQUENCY (MHz)
MC1650
FREQUENCY (MHz)
50 75 100
MC1651
2001000
0.85
0.65
0.45
0.25
0.05
10 20 30 50 70 100 200 300
0.45
0.25
0.05
10 20 30 50 70 100 200 300
0.65
0.85
PEAK-TO-PEAKOUTPUT(VOLTS)
PEAK-TO-PEAKOUTPUT(VOLTS)
Input Voltage
mV Peak-to-Peak
20010075Input Voltage
mV Peak-to-Peak
1000
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4343 MOTOROLAMECL Data
DL122 Rev 6
TEST CIRCUIT
FIGURE 8 INPUT CURRENT versusINPUT VOLTAGE
VCC+5.0 Vdc
0.1 F7 10
+
+
D Q
C Q
D Q
C Q
V1
V2
VCC VCC50
502.0 Vdc
VIH
VEE Gnd Gnd
16180.1 F
VEE5.2 Vdc
Iin
Vin
+
I
,INPUTCURRENT(
A)
in
Vin, INPUT VOLTAGE (VOLTS)
Typical MC1651 (Complementary Input Grounded)
30C
+85C
+25C30C
+85C
Typical MC1650 (Complementary Input Grounded)
0 +112 +2
30
0
5
2.5
5
5
25
20
Vin, INPUT VOLTAGE (VOLTS)
15
10
5
0 21122.5
0
2.5
I
,INPUTCURRENT(
A)
in
+2.5
+25C
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MC1650 MC1651
MOTOROLA MECL Data4344
OUTLINE DIMENSIONS
L SUFFIXCERAMIC DIP PACKAGE
CASE 62010ISSUE V NOTES:
1. DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHENFORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)WHERE THE LEAD ENTERS THE CERAMICBODY.
A
B
T
F
E
G
N K
C
SEATING
PLANE
16 PLD
SAM0.25 (0.010) T
16 PLJSBM0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.93B 0.240 0.295 6.10 7.49C 0.200 5.08D 0.015 0.020 0.39 0.50E 0.050 BSC 1.27 BSCF 0.055 0.065 1.40 1.65G 0.100 BSC 2.54 BSCH 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSCM 0 15 0 15N 0.020 0.040 0.51 1.01
16 9
1 8
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MC1650/D