Chip design for a time encoding A/D converter Dries Vercaemer · 2013. 9. 19. · H (s) ADC DAC U V...

Dries Vercaemer

Chip design for a time encoding A/D converter

Academiejaar 2012-2013Faculteit Ingenieurswetenschappen en ArchitectuurVoorzitter: prof. dr. ir. Jan Van CampenhoutVakgroep Elektronica en Informatiesystemen

Master in de ingenieurswetenschappen: elektrotechniekMasterproef ingediend tot het behalen van de academische graad van

Begeleider: Amir Babaie FishaniPromotor: prof. dr. ir. Pieter Rombouts

Dankwoord

Na vijf jaar studeren schrijf ik nu mijn masterproef als kroon op het werk. Het zou niet

tot stand gekomen zijn zonder de hulp van een aantal personen. Vooreerst wil ik mijn

promotor, Prof. Pieter Rombouts bedanken voor de tijd die hij genomen heeft om mij

hierbij te begeleiden. Met aanstekelijk enthousiasme verschafte hij uitleg en hielp hij deze

thesis tot een goed einde te brengen. Verder kan Amir Babaie Fishani ook niet ontbreken.

In geval van problemen was zijn deur snel gevonden. Ik bedank ook Maarten De Bock

voor het oplossen van een aantal praktische zaken. En ten slotte ook Johan Raman die

een belangrijke intellectuele bijdrage heeft geleverd.

Toelating tot bruikleen

De auteur geeft de toelating deze masterproef voor consultatie beschikbaar te stellen en de-

len van de masterproef te kopieren voor persoonlijk gebruik. Elk ander gebruik valt onder

de beperkingen van het auteursrecht, in het bijzonder met betrekking tot de verplichting

de bron uitdrukkelijk te vermelden bij het aanhalen van resultaten uit deze masterproef.

The author gives permission to make this master dissertation available for consultation

and to copy parts of this master dissertation for personal use. In the case of any other

use, the limitations of the copyright have to be respected, in particular with regard to the

obligation to state expressly the source when quoting results from this master dissertation.

Dries Vercaemer, juni 2013

Chip design for a time encoding A/D converter

Dries Vercaemer

Promotor:prof. dr. ir. Pieter Rombouts

Begeleider: Amir Babaie Fishani

Masterproef ingediend tot het behalen van de academische graad van

Master in de ingenieurswetenschappen: elektrotechniek

Vakgroep Elektronica en Informatiesystemen

Voorzitter: prof. dr. ir. Jan Van Campenhout

Faculteit Ingenieurswetenschappen en Architectuur

Academiejaar 2012-2013

Trefwoorden: Self-oscillating, Time encoding, Analog digital converter, Sigma delta

modulator

Extended Abstract

Inleiding

In het verloop van deze thesis is een zelf-oscillerende Σ∆ modulator ontworpen, zowel

op systeemniveau als circuit niveau. Het doel is een laag vermogen ADC met 20MHz

bandbreedte en een SNDR hoger dan 70dB te ontwerpen. Het circuit is geımplementeerd

in een 60nm technologie en de bemonsteringsfrequentie is 2GHz. Het vermogensverbruik

van de op-amps in de lus filter is ongeveer 1,2mW. Het voordeel van de zelf-oscillatie

is dat de lus slechts signalen aan moet kunnen met een frequentie maximaal gelijk aan

de oscillatie-frequentie. Aangezien deze een derde is van de bemonsteringsfrequentie kan

de bandbreedte van de op-amps in de lus gereduceerd worden wat vermogen bespaart.

Verder is een nieuwe aanpak toegepast om de slewing-vereisten verder te versoepelen.

Een laagdoorlaatfilter is in de lus geplaatst om de oscillatie te onderdrukken. Om de

invloed van dit filter op het lusfilter te elimineren is er een compensatiefilter toegevoegd in

parallel met de eerste integrator. Op circuit niveau is het lus filter geımplementeerd met

feedforward op-amps wegens hun laag vermogengebruik. Deze thesis bouwt onder andere

voort op de ontwerpen beschreven in [5] en [6].

PWM

Het systeem gaat uit van een Σ∆ modulator, afgebeeld in Figuur 1. Het idee is om puls-

breedtemodulatie(PWM) te gebruiken voor de ADC aan de uitgang van de modulator.

Deze modulatie techniek stelt de waarde van zijn ingangssignaal voor door de lengte van

een puls. Figuur 2 toont dit concept. De ingang is gesuperponeerd met een oscillatie en

dit signaal wordt aan een comparator aangelegd. Het resultaat is een blokgolf waarvan

de breedte een maat is voor het ingangssignaal. PWM heeft het voordeel dat een 1

bits DAC kan gebruikt worden in het terugkoppelpad, hetgeen betekent dat deze perfect

lineair is. Daarnaast speelt PWM perfect in op de eigenschappen van moderne halfgelei-

der technologieen namelijk een lage voedingsspanning en de capaciteit om nauwkeurig

tijdsintervallen te meten dankzij de hoge mogelijke snelheden. Belangrijker nog is het feit

dat het pulsbreedtegemodulleerd signaal slechts twee keer verandert per oscillatieperiode.

Dit betekent dat de lus de bemonsteringsfrequentie niet hoeft aan te kunnen. Het hoeft

ten snelste te werken aan de oscillatiefrequentie, fosc. Bovendien kan de bemonsteringsfre-

Σ H(s) ADC

DAC

U V

Figuur 1: Diagram van een algemeen sigma delta modulator

Figuur 2: Werking van PWM

quentie verhoogd worden zonder de lus aan te hoeven passen, zolang de oscillatiefrequentie

maar gelijk blijft.

Hoewel PWM slechts 1 bit quantisatie gebruikt is het uitgangssignaal toch een ver-

liesloze voorstelling van de ingang. Omdat de informatie is opgeslagen in de breedte van

de puls is het de bemonstering die een fout introduceert, zelfs als de bemonsteringsfre-

quentie hoger is dan de nyquistfrequentie. Deze fout kan voorgesteld worden door witte

quantisatieruis met volgende variantie:

σ2 =2fosc3fs

(1)

De quantisatieruis neemt dus toe met de oscillatiefrequentie en neemt af als de bemon-

steringsfrequentie verhoogt.

Zelf-oscillatie

De oscillatie die nodig is voor PWM wordt gecreeerd door de lus zelf. De lus wordt

onstabiel gemaakt door een vertraging toe te voegen in het terugkoppelpad. Figuur 3 toont

het systeem. Indien de DAC een non return to zero puls heeft moet de oscillatiefrequentie

aan volgende vergelijking voldoen:

− ωdTs −ωTs

2+ α(H(s)) = π (2)

De lusfilter van het ontworpen systeem zal een eerste orde integrator benaderen voor hoge

frequenties. We kunnen vergelijking 2 als volgt oplossen in dat geval: fosc = fs4(d+ 1

2).

Vervolgens wordt de comparator gelineariseerd. Zijn ingang bestaat uit een snel os-

cillerende component, en een tragere component gerelateerd aan het ingangssignaal van

Σ H(s)

DAC

U Vfs

z−d1 bit

Figuur 3: Diagram van een zelf-oscillerende sigma delta modulator

het systeem, U. Volgens [2] kan men de comparator voorstellen als een versterker op voor-

waarde dat de trage component een kleinere amplitude heeft dan de snelle oscillerende

component. De resulterende versterker heeft een versterking Gosc = 4πA voor de snelle

component, en een versterking Gs = 2πA voor de tragere en kleinere component. Hierin is

A de amplitude van de oscillatie aan de ingang van de comparator. Indien we de blokgolf

aan de uitgang van de comparator benaderen door de eerste term uit zijn fourierreeks, dan

vinden we dat A gelijk is aan 4π |H(jωosc)DAC(jωosc)| ≈ 4

π |H(jωosc)|. Nadat we Vergelijk-

ing 2 oplossen naar fosc kunnen we dus de comparator lineariseren en een transferfunctie

opstellen voor de quantisatieruis. Als we dit dan paren met Vergelijking 1 kunnen we de

prestatie van de modulator schatten.

Systeemniveau

Figuur 4 toont het diagram van het systeemniveau van de ontworpen modulator. Er zijn

twee lussen zichtbaar. Een buitenlus die drie integratoren bevat, en een binnenlus die er

slechts een bevat. De oscillatie is merendeels beperkt tot de binnenste lus. Ze wordt hard

onderdrukt door de drie integratoren in de buitenlus. Hierdoor hoeft de tweede integrator

de oscillatie niet te verwerken. De lokale terugkoppeling zorgt voor een nul in de ruistrans-

ferfunctie met hoekfrequentie√gc1c2. Door g aan te passen kan deze nul dicht tegen de

bandbreedte van de modulator geplaatst worden waar de quantisatieruis het hoogste is.

Dit verhoogt de SNR van het systeem. Er is een inkoppelpad van de ingang naar de derde

integrator. Dit maakt de signaaltransferfunctie vlakker en verlaagt de uitgangszwaai van

de eerste integrator. De vertraging in de buitenlus verlaagt de benodigde insteltijd voor

de eerste twee integratoren. Het systeem is in Simulink gesimuleerd en tevens is er een

ruistransferfunctie afgeleid met het lineaire model. het resultaat is te zien op Figuur 5.

De SNR is 75dB voor een -1.9dBFS ingangssignaal. Het lineaire model voorspelt een SNR

van 76dB.

Hoewel het niet nodig is voor de goede werking van de modulator dat de buitenste lus

de oscillatie verwerkt heeft de eerste integrator dit groot en snel signaal wel aan zijn ingang.

De integratoren zijn met op-amps geımplementeerd en hun uitgang kan voorgesteld worden

als een spanningsgestuurde stroombron die een capaciteit oplaadt. De stroom die deze bron

kan leveren is echter beperkt en door de wet van de condensator, is dus de afgeleide van de

Σ

DAC

U Vfs

z−d

1 bit

c1s

c2s

c3sΣ

g

DAC

z−12

1 bit

Figuur 4: Diagram van de derde orde SOSDM

10−4

10−3

10−2

10−1

−160

−140

−120

−100

−80

−60

−40

−20

0

f*Ts

FFT(dB)

Figuur 5: Spectrum van de uitgang na simulatie van de modulator samen met de lineaire be-

nadering

uitgangsspanning beperkt. Wanneer de op-amp deze maximale stroom levert wordt gezegd

dat ze slewt. Dit slewen is een niet lineair effect dat distorsie introduceert en het moet

voorkomen worden om de prestatie van het systeem te behouden. Dit kan gedaan worden

door de maximale leverbare stroom van de op-amp te verhogen maar dit kost vermogen.

In deze thesis is een nieuwe aanpak geımplementeerd om de oscillatie te onderdrukken in

de buitenste lus om slewing te voorkomen.

Er wordt een laagdoorlaatfilter in het terugkoppelpad geplaatst met een afsnijfrequen-

tie die lager ligt dan fosc. Dit filter beınvloedt echter de lusfilter en de stabiliteit van de

lus wat het ontwerp bemoeilijkt. Dit kan voorkomen worden door een compensatiefilter,

Hc, toe te voegen in parallel met de laagdoorlaatfilter en de eerste integrator. Indien

de laagdoorlaatfilter volgende vorm heeft 11+sτ moet Hc = c1τ

1+sτ . Gedurende simulatie

is het duidelijk geworden dat indien de afsnijfrequentie te dicht bij de doorlaatband van

de modulator ligt, de uitgangszwaai van de eerste integrator verhoogt. Er zal dus een

afweging moeten gemaakt worden tussen de maximaal toegelaten uitgangszwaai en de on-

derdrukking die het laagdoorlaatfilter biedt. In dit ontwerp is het oscillatiesignaal met een

factor hoger dan 6 onderdrukt.

Circuitniveau

Het integreren en someren wordt geımplementeerd met op-amps. Figuur 7 toont een

integrator met als ingang de som van twee signalen waarvan een door een laagdoorlaatfilter

gaat. In het totale circuit van de modulator zijn er drie op-amps en zij zijn de meest

cruciale componenten. De eerste op-amp in het bijzonder omdat die het leeuwendeel van

het vermogensverbruik voor zijn rekening neemt. De op-amps zijn geımplementeerd in

een feed forward architectuur met drie trappen. Het kleinsignaal circuit is afgebeeld op

Figuur 8. Volgende transferfunctie is gewenst:

A(s) = − 1

sτ1

(1 + sτ2

sτ2

)2

(3)

Vanwege stabiliteit moet τ1 kleiner zijn dan τ2. Het versterkingsbandbreedteprod-

uct(GBWP) is gegeven door 12πτ1

en wordt bepaald door de derde feedforward trap. Deze

trap verbruikt het meeste vermogen van de op-amp. De drie trappen van de eerste op-amp

staan afgebeeld op Figuren 5.3, 5.5, en 5.6 van de thesis. De tweede en derde op-amp

zijn heel gelijkaardig aan de eerste.

Het hoogste niveau van het circuit is afgebeeld op Figuur 4.3 van de thesis. De com-

parator met bemonstering is gerealiseerd door een voorversterker gevolgd door een flip

flop. De vertraging van een halve klok periode is geımplementeerd met een flip flop die

gestuurd wordt door een inverse klok. Alleen de invertoren komen niet op het systeem-

diagram voor. Ze opereren als buffers tussen het analoog en het digitaal deel van het

circuit. Ze hebben een hoge ingangsimpedantie en worden belast door de lage impedantie

van het analoge circuit. Door de lage resistieve belasting van de invertoren verbruiken zij

heel wat vermogen. Een ruwe schatting voor hun verbruik is 0,5mW. De drie op-amps

daarentegen verbruiken zo’n 1,2mW samen waarvan de eerste op-amp 0,9mW voor zijn

rekening neemt. Het verbruik in de flip-flops en de voorversterker is verwaarloosbaar.

Σ

DAC

U Vfs

z−d

1 bit

c1s

c2s

c3sΣ

g

DAC

z−12

1 bit

11+sτ c1τ

1+sτ

Σ

Hc

x

y

Figuur 6: Diagram van de zelf-oscillerende sigma delta modulator met oscillatie onderdrukking

X2+ Y+

X2- Y-

+

--+

X1+

X1-

V+

V-

C

C

R1RLP

R2

CLP

RLP R1

R2

Figuur 7: Integratie van de som van twee signalen van welke een laagdoorlaatgefilterd is.

R1 R2 R3C1 C2 C3gm1Vin gm2V1 gm3V2

V1 V2 Vuit

gmFF2Vin gmFF3Vin

Figuur 8: Het kleinsignaalcircuit van een drie-traps feedforward op-amp.

Besluit

In het verloop van deze thesis is een laag vermogen ADC ontworpen met een bemonster-

ingsfrequentie van 2GHz. Er werd gestart vanuit een Σ ∆ modulator. Door PWM te

gebruiken en de lus te laten oscilleren aan 666,7MHz werd het vermogensverbruik gere-

duceerd. Deze werd verder teruggedrongen door een laagdoorlaatfilter toe te voegen. Een

compensatiefilter elimineerde de invloed van dit laagdoorlaatfilter op het lusfilter. Het

ontwerp is geımplementeerd op circuitniveau met feedforward op-amps in een 60nm tech-

nologie. De bandbreedte is 20MHz en de maximale SNR 74dB. De op-amps verbruiken

ongeveer 1,2mW

Extended Abstract

Introduction

In this thesis, a self-oscillating Σ∆ modulator is designed on system and circuit level.

The aim is to design a low power ADC with 20 MHz bandwidth and an SNDR higher

than 70dB. The sample frequency is 2GHz and the circuit is implemented in a 60nm

technology. The power consumption of the op-amps in the loop filter is only 1.2mW. The

advantage of the self-oscillation is that the highest frequency of the signals in the loop

is the oscillation frequency. As the loop oscillates at a third of the sample frequency,

this means the bandwidth of the op-amps in the loop is reduced, saving power. A novel

approach is applied to further reduce slewing requirements. A low pass filter is introduced

in the loop to suppress the oscilation, and a compensation filter is added, bypassing the

first integrator, to eliminate the influence of the low pass filter on the loop filter. On

circuit level the loop filter is implemented with feed forward op-amps as they have a low

power consumption. This thesis started from the designs described in [5] and [6].

PWM

The system starts from a sigma delta modulator, depicted on Figure 1. The idea is to

use pulse width modulation in the ADC at the output of the sigma delta modulator.

Pulse width modulation represents the value of its input voltage into a length of a pulse.

Figure 2 shows the operation. The input is summed with an oscillating signal and applied

at a comparator. The output is a square wave which width is proportional to the value of

the input. PWM has the advantage that a one bit DAC can be used in the feedback path,

which means it is perfectly linear. Also PWM makes perfect use of the characteristics of

modern semi-conductor technologies: low voltage headroom and accurate measuring of

Σ H(s) ADC

DAC

U V

Figure 1: Diagram of a general sigma delta modulator

Figure 2: Operation of PWM

time intervals due to high speeds. But more importantly, the PWM signal changes only

twice every oscillation period. This means the loop does not have to handle the sample

frequency but only the oscillation frequency, fosc. Furthermore, the sample frequency can

be increased without affecting the loop as long as the oscillation frequency remains the

same.

Although PWM uses one bit quantization, the output is a lossless representation of its

input. Because the information is stored in the width of a pulse, it is the sampling that

will introduce an error, even if the sample frequency is higher than the Nyquist frequency.

This error can be represented by white quantization noise with a variance of:

σ2 =2fosc3fs

(1)

This means the quantization noise decreases with increasing sample frequency and de-

creasing fosc.

Self-Oscillation

The oscillation needed to perform PWM is generated by the loop itself. A delay is added,

making the loop unstable. Figure 3 shows the system. If a non return to zero pulse is

assumed for the DAC, the oscillation frequency has to satisfy:

− ωdTs −ωTs

2+ α(H(s)) = π (2)

The loop filter for the designed system will approximate a first order integrator for high

frequencies. If that is the case, Equation 2 can be solved and the result is: fosc = fs4(d+ 1

2).

Σ H(s)

DAC

U Vfs

z−d1 bit

Figure 3: Diagram of the self-oscillating sigma delta modulator

Next the comparator is linearized. Its input consists of a oscillation component and a

slower component related to the system input U. From [2] it is learned that if this slow

component is smaller than the fast input component, the comparator can be linearized as

a gain Gosc = 4πA for the fast oscillating component, and a gain Gs = 2

πA for the slower

signal component. A is the amplitude of the oscillation at the input of the comparator. If

the square wave oscillating output of the comparator is approximated by the first term of

its Fourier series, A is found to be 4π |H(jωosc)DAC(jωosc)| ≈ 4

π |H(jωosc)|. After solving

Eq. 2 for the oscillation frequency, a transfer function can be derived for the quantization

noise by using the equivalent comparator gain Gs. After coupling this with Eq. 1 an

estimate can be made of the systems performance.

System level

Figure 4 shows the system level diagram of the designed modulator. There are two loops

visible. An outer loop containing three integrators and an inner loop with only one. The

oscillation is chiefly contained in the inner loop. It is very weak in the outer loop because

of the suppression with a third order integrator. This way, the second integrator does

not need to process the fast oscillation. The local feedback path introduces a zero in the

noise transfer function of the system at the angular frequency√gc1c2. By changing the

feedback gain g, this zero can be placed close to the bandwidth, where the output noise is

highest. This effectively increases the SNR. A feed forward path is also introduced from

the input to the third integrator. This flattens the signal transfer function and reduces

the output swing of the first integrator. The delay in the outer loop reduces the settle

time requirements of the first two integrators. The system is simulated in simulink and

the noise transfer function is calculated using the linear model of the system. Figure 5

shows the result. The SNR is 75dB for a -1.9dBFS input signal, while the linear model

predicts a SNR of 76dB. This is a good fit.

Although the outer loop does not need to process the oscillation for the good operation

of the modulator, the first op-amp still receives this large and fast signal at its input. The

Σ

DAC

U Vfs

z−d

1 bit

c1s

c2s

c3sΣ

g

DAC

z−12

1 bit

Figure 4: Diagram of a third order SOSDM

10−4

10−3

10−2

10−1

−160

−140

−120

−100

−80

−60

−40

−20

0

f*Ts

FFT(dB)

Figure 5: Spectrum of the output of the simulated system and the linear approximation

integrator is implemented with an op-amp. The output of this op-amp can be represented

as a voltage controlled current source loaded by a capacitor. The maximum current this

source can deliver is limited. As a result the maximum rate of change of the output voltage

is limited. When the op-amp delivers this maximum current, the op-amp is said to be

slewing. This is a non-linear effect that introduces distortion and it should be prevented to

safeguard the performance of the modulator. Slewing is avoided by increasing the current

the op-amp can deliver but this also increases the power consumption. In this thesis a

novel approach was tested to suppress the oscillation in the outer loop and hence reduce

the slewing specifications for the first op-amp.

A low pass filter is introduced with a cut off frequency lower than fosc. This filter

does however influence the loop filter and the stability of the loop. This makes the design

process more complex. However by introducing a compensation filter, Hc, that bypasses

the first integrator, the effect of the low pass filter on the system can be eliminated.

Figure 6 shows the system diagram. For a first order low pass filter 11+sτ , Hc is found

to be c1τ1+sτ . It has been observed that placing the cut off frequency too close to the pass

band of the modulator increases the output swing of the first integrator. This means a

trade off will have to be made between suppression and output swing. In this design the

oscillation amplitude was suppressed by a factor 6.

Circuit level

The integrating and summing is implemented using op-amps. Figure 7 shows an integrator

that acts on the sum of two signals, one of which is low pass filtered. There are three

op-amps in the modulator circuit and they are the most crucial components. Especially

the first op-amp as it determines most of the power consumption. All op-amps have been

implemented using a feed forward architecture with three stages. The small signal circuit

Σ

DAC

U Vfs

z−d

1 bit

c1s

c2s

c3sΣ

g

DAC

z−12

1 bit

11+sτ c1τ

1+sτ

Σ

Hc

x

y

Figure 6: Diagram of a third order SOSDM with oscillation suppression

is depicted in Figure 8. Following transfer function is wanted:

A(s) = − 1

sτ1

(1 + sτ2

sτ2

)2

(3)

For stability τ1 should be smaller than τ2. The GBWP equals 12πτ1

and is determined by

the third feed forward stage. This stage consumes most of the power of the first op-amp.

The three stages of the first op-amp are represented in Figures 5.3, 5.5, and 5.6 of the

thesis. The second and third op-amps are very similar to the first.

X2+ Y+

X2- Y-

+

--+

X1+

X1-

V+

V-

C

C

R1RLP

R2

CLP

RLP R1

R2

Figure 7: Integration of the sum of two signals, one of which is low pass filtered


V1 V2 Vuit

gmFF2Vin gmFF3Vin

Figure 8: Small signal circuit of a three stage feed forward op-amp

The top level circuit is depicted in Figure 4.3 of the thesis. The sampled comparator is

implemented with a preamp followed by a flip flop. The half clock cycle delay is realized

with a flip flop clocked at the inverse clock. Only one set of components has not been

discussed: the inverters. They act as buffers between the analog and digital parts of

the circuit. They offer a high input impedance and are loaded by the low impedance of

the analog part of the circuit. They also are responsible for a large part of the power

consumption because of their low resistive loading. A raw estimate of their consumption

is 0.5mW. An estimated consumption of the three op-amps together is 1.2mW, of which

0.9mW is consumed in the first op-amp. The consumption in the preamp and flip-flops is

negligible.

Conclusion

In this thesis a low power ADC was designed with a sample frequency of 2GHz. The

starting point was a Σ ∆ modulator. By using PWM and making the loop oscillate at

666,7MHz, the power consumption was reduced.It was further reduced by introducing a

low pass filter. A compensation filter eliminated the influence of the low pas filter on the

loop filter. The design was implemented on the circuit level using feed forward op-amps

in a 60nm technology. The bandwidth of the system was 20MHz and the maximum SNR

was 74dB. The op-amps consumed approximately 1.2mW.

Contents

Glossary

1 Introduction 1

2 Self-Oscillating Sigma Delta Modulator 3

2.1 The ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.2 Sigma Delta Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.3 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.4 Self-Oscillating Sigma Delta Modulator . . . . . . . . . . . . . . . . . . . . 8

3 System design 13

3.1 A third order SOSDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Results of the linear approximation . . . . . . . . . . . . . . . . . . . . . . . 16

3.3 Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4 Slewing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.5 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 The circuit 23

4.1 Top level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2 Dimensioning the Passive components . . . . . . . . . . . . . . . . . . . . . 26

4.3 Preamp, Flip Flops and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . 27

5 Op-Amp Design 31

5.1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1.1 GBWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1.2 DC Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1.3 Slewing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.1.4 Other Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.2 General Feed Forward Op-Amp Design Flow . . . . . . . . . . . . . . . . . 34

5.3 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.3.1 CMFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.3.2 Outputswing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Contents

5.3.3 Cascode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.3.4 Biassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.3.5 Other Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.3.6 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.3.7 Op-Amp1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.3.8 Op-Amp2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.3.9 Op-Amp3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.10 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6 Conclusion 53

Bibliography 55

Glossary

ADC analog to digital converter.

CMFB common mode feedback.

DAC digital to analog converter.

dbFS value relative to full scale in decibel.

FF op-amp feedforward op-amp.

GBWP gain bandwidth product.

IirT invariant impulse response transformation.

NRZ non return to zero (pulse).

NTF noise transfer function.

op-amp operational amplifier.

OSR oversampling ratio.

Preamp preamplifier.

PWM pulse width modulation.

SDM sigma delta modulator.

SNDR signal to noise and distortion ratio.

SNR signal to noise ratio.

SOSDM self-oscillating sigma delta modulator.

Glossary

Chapter 1

Introduction

Digital electronics have become an important part of our lives. Costs decreased and speed

rose due to Moore’s law, which enabled electronics to penetrate deeper into our world.

There are dozens of chips in modern factories and cars. Digital consumer products are

omnipresent. However, though it would be very convenient, the physical world stubbornly

refuses to go digital. High clock speeds and fast memories are useless without data. This

is where analog digital converters come in to play. They are the bridge between our digital

world and the analog reality. Manny micro controllers work in real time and if their digital

speed increases, the ADC’s must follow. On top of this, more and more systems become

wireless and have to rely on battery power. This creates a market for high bandwidth low

power ADC’s.

The aim of this thesis is to design a self-oscillating sigma delta modulator with low

power consumption and a bandwidth of 20MHz. It will have a sample frequency of 2GHz

and offer a SNR higher than 70dB.

The design will first take place on the system level. The operation of the SOSDM will

be explained, starting from the conventional sigma delta modulator. A linear model will

be proposed to predict the performance of the system. Afterwards the coefficients of the

system will be optimized for a high SNR. Still on the system level, a novel technique will

be used to further decrease the power consumption of the system.

After the system level design is complete, the design will shift to the circuit level. The

modulator will be implemented in a 65nm technology. Feed forward op-amps will be used

due to their power friendliness.

I used [5] and [6] as a starting point for this thesis.

1

Chapter 1. Introduction 2

Chapter 2

Self-Oscillating Sigma Delta

Modulator

2.1 The ADC

Signals in the analog world are continuous, both in time and value. To store them without

precision loss would require an infinite memory. The analog digital converter approximates

its analog input so that it can be stored in a digital memory with finite dimensions. The

ADC performs two operations. First it samples its input. Every sample period, it stores

the value of the input signal at that time. Nyquist proved that if the sample frequency

is higher than twice the maximum frequency of the input(the Nyquist frequency), this

sampling does not lead to precision loss. The second operation is quantization. Every

value of the sampled input is rounded to a quantization level. This operation does lead to

information loss. It is the quantization that limits the resolution of the ADC. The error

introduced by the quantization is often represented as white noise, called the quantization

noise.

There are several types of ADC’s. Flash converters are very fast but require a large

chip area. Successive approximation leads to high precision ADC’s with limited chip area

but it is rather slow. The design of this thesis is based on the sigma-delta modulator.

The SDM is able to offer high precision in reasonable time but it does require high sample

frequencies.

2.2 Sigma Delta Modulator

The basic schematic of a sigma delta modulator is depicted in figure 2.1. It is a feedback

loop. It uses a simple, low accuracy ADC and uses feedback to reduce its error. The

sampling frequency by which the loop operates is much higher than the Nyquist frequency.

This is called oversampling and is crucial to the operation of the sigma delta modulator.

3

Chapter 2. Self-Oscillating Sigma Delta Modulator 4

The oversampling ratio or OSR is given by fs2BB . The effect of the loop filter is that it

pushes the quantization noise, produced by the simple ADC, away from the baseband to

higher frequencies. If the output of the loop is low pass filtered, a lot of the quantization

noise will be filtered out, leading to much higher accuracy than the simple ADC could

deliver.

Σ H(s) ADC

DAC

U V

Figure 2.1: A sigma-delta modulator with a loop filter in continuous time

The accuracy of most ADC’s is limited to the accuracy of the components. Components

with high precision values are difficult to produce so performance is often limited. Some

integrating ADC can obtain high accuracy with low precision components but they achieve

this at the cost of low conversion rates. This shows the strength of the SDM. It can obtain

high precision in a limited time with a low influence of the accuracy of the components

on the performance. The trade off is the oversampling which necessitates a fast circuit.

The operation is illustrated for a modulator with a first order loop filter and a one

bit ADC. The ADC consists of a sampler and a one bit quantizer which is basically a

comparator. The comparator projects its input to +1 or -1 and hence produces an error.

It is well established [4] that this error, under certain conditions, closely resembles white

noise. So the ADC can be approximated as an amplifier followed by a sampler with a

white noise source at its output. Figure 2.2 shows this system.

Σa

sTs

UG Σ

E

DAC

Vfs

Figure 2.2: SDM with first order loop filter and one bit DAC.

If the sampling is neglected, the transfer function from the noise to the output issTs

sTs+aG . The bode plot is shown on figure 2.3. It is clear that the noise transfer function,

NTF, pushes the noise away from baseband. The loop filter ’shapes’ the noise. If the OSR


is increased by decreasing the bandwidth or increasing the sample frequency (and the inte-

grator constant) less quantization noise would fall in the bandwidth and our performance

would increase. The signal transfer function is:

aGsTs

1 + aGsTs

(2.1)

which, for low frequencies approximates as 1.

10−2

10−1

100

101

102

−50

−45

−40

−35

−30

−25

−20

−15

−10

−5

0

Mag

nit

ud

e (

dB

)

Bode Diagram

Frequency (rad/sec)

Figure 2.3: NTF of first order SDM

Another way of explaining the SDM operation and the noise shaping is in the time

domain. Assume a zero input and a small charge on the integrator. The output of the

comparator would be one volt. This leads to a an negative input of the integrator and

at the next clock cycle the output of the integrator will have decreased. After a few

clock cycles it will be negative. The comparator switches to -1 and every few clock cycles

the output switches between +1 and -1. We assumed the output is low pass filtered or

averaged. In this case the average output will be zero which is a better representation of

the input than the simple 1 bit ADC could offer. This also works for a non zero input. If

the input is positive the output will be +1 for more clock cycles because the error signal

will have a positive offset. The averaged output will get a decent approximation of the

input. If the sample frequency is increased, there will be more values to average over and

the result will be more accurate.

This simple system can now be used to illustrate the problem of overloading, which

will limit the input range of the design. Assume an input U, higher than the output of the

comparator. The input of the integrator, the error signal, is U-1 which is always positive.

This means the integrated signal will increase without end. This desensitizes the system to

its input and will lead to non-linearities as the limit of the systems components is reached.


It is called overloading the quantizer. For big signals the white noise approximation of

the quantization is no longer valid and the circuit becomes unstable. This instability is

sometimes hard to predict for higher order systems, which can become unstable even at

zero input.

This SDM has a continuous time loop filter, H(s). A discrete loop filter is also possible

by sampling before the loop filter. The advantage of a continuous loop filter is that the op-

amps can have a lower settling time, because no stable value has to be reached before the

next clock cycle as opposed to a switched C realization. Another advantage specifically for

the Self-Oscillating SDM is the scalability of the sampling frequency as will be illustrated

later.

2.3 PWM

To improve the accuracy of the ADC, The OSR can be increased. However, if a high

bandwidth is required, this leads to a high sampling frequency. Although the scaling of

the semi conductor technology allows for high frequencies, high enough OSR’s can often

not be achieved due to power limitations. Another way to increase the accuracy is to

use a multi bit quantizer. However this has some drawbacks. Firstly, a multi bit ADC

and DAC contain some non-linearities. The non-linearities of the ADC are not a limiting

factor since they are suppressed, like the quantization noise, by the loop filter. The non

linearities of the DAC in the feedback path are a bigger problem. They directly influence

the performance of the SDM. This problem does not pose itself for a one bit DAC. A one

bit DAC is always linear since two points define a straight line.

Another problem of the multi bit quantizer is the low supply voltage of new high speed

technologies. The newest semiconductor technologies barely achieve a supply of one volt.

A classical ADC, like the flash ADC, produces its bit by comparing its input with multiple

voltage levels. Because of the falling supply voltage these levels become very close to each

other which decreases precision.

A solution to these two problems is to use a PWM-quantizer. Instead of comparing

the input voltage to different voltage levels, a rapid oscillating signal is added to the input

and the result is compared to zero. This is illustrated in Figure 2.4.

PWM produces a square wave output signal. The width of each pulse is a measure

of the input signal. The quantization happens in time, not in the voltage of the signal.

Also the output is a one bit signal so the feedback DAC is inherently linear. Pulse width

modulation is adapted to new, fast speed technologies. It is able to work with low supply

voltages and makes use of the abilities to measure time with high accuracy. However the

main reason to use PWM is that it leads to lower power consumption. The square wave

output signal only changes twice every oscillation period. This means the fastest signal

the loop of the SDM has to handle changes at this oscillation frequency, not the sample


Figure 2.4: Pulsewidth modulation

frequency. This leads to bandwidth reduction for the op-amps in the loop, and hence

power saving.

The signal at the output of the PWM-Quantizer is an exact representation of the

input signal. Unlike conventional quantizers, the error is not introduced by the quantizer.

Because the signal level is represented by the length of a pulse, the quantization error is

caused by sampling. If sampling doesn’t happen at the moments that the output square

wave makes a transition, an error is made in determining the pulse length and thus an

error in determining the signal level. The loop filter shapes the error signal at its input.

+2

-2

-1

-1

+1

+1

Figure 2.5: Output of the comparator before and after sampling together with error signals

This signal is the difference between the continuous input and the zero order hold version

of the output. Therefore a good representation of the error made by quantizing is the


difference between the comparator output before sampling and the shifted zero order hold

version of the sampled comparator output. We have to shift the second signal because the

zero order hold pulse introduces a half clock cycle delay. This error pulse, E1, will have

a maximum length of Ts and a height of +/-2 and appears twice every oscillation period.

A sampled error signal, E2, is now constructed by demanding that its zero order hold

version has the same area as the error signal E1. E2 ranges from −8fosc/fs to 8fosc/fs

and represents the quantization noise. The variance of a stochastic variable, uniformly

distributed over [−∆,∆], is ∆12 . If the quantization noise is assumed to be uniformly

distributed, its variance is:

∆/12 =2

3

foscfs

(2.2)

Figure 2.5 shows the output signal before and after sampling together with the error

signals.

2.4 Self-Oscillating Sigma Delta Modulator

To implement a PWM ADC, an oscillation is needed. An easy way to implement this

oscillating signal is by adding some delay in the loop. Figure 2.6 shows the SOSDM. By

Σ H(s)

DAC

U Vfs

z−d1 bit

Figure 2.6: Diagram of SOSD-modulator

adding this delay, the loop becomes unstable thus an oscillation is created. The output

comparator changes at the oscillation frequency. This means the fastest frequency the loop

has to handle is the oscillation frequency not the sample frequency. This reduces the power

consumption, as the bandwidth of the components in the loop can be reduced. Earlier it

was mentioned that an advantage of a continuous loop filter is scalability. Equation 2.2

shows that the noise decreases with increasing sample frequency. However the loop filter

does not operate at the sample frequency. The sample frequency can be increased without

affecting the loop filter, as long as the delay is also increased to offer the same oscillation.

This eases the way to newer technologies. Old designs can easily be translated to newer

technologies, allowing the sample frequency to be increased. This means a better noise

performance without the need to completely redesign the loop filter.

The loop will start to oscillate at the frequency at which the total phase shift of the


loop becomes 180. So the phase shift of the loop and the delay determine the frequency

of oscillation. As illustration the frequency of oscillation for a first order loop filter is

calculated.

If the DAC has a non return to zero pulse it’s transfer function is 1−esTssTs

. If the effect

of sampling is ignored, the total phase shift of the loop is:

− 90 − ωdTs − ωTs/2. (2.3)

This equals 180 for ωTS = π2(d+1/2) so

fosc =1

4(d+ 1/2)fs (2.4)

For example a delay of one gives an fosc of fs6 . This simple result is still relevant for the

design of the higher order system. Although this will be a third order system, the loop

filter will predominantly behave as a first order filter for high frequencies so Equation 2.4

will hold approximately.

In the previous analyses the effect of sampling was ignored. This assumption has little

influence on the result, as will be illustrated later, apart from the fact that the period

of oscillation has to be an integer multiple of the sample period. For higher order loop

filters, the frequency at which the phase shift of the loop becomes 180 is not necessarily

an integer division of the sample frequency. So how is the exact oscillation frequency to

be determined?

As Figure 2.7 shows, the sampler will add extra delay and thus an extra amount of

phase, ∆φ. This means that the oscillation frequency will be the frequency at which the

phase of the loop becomes 180 −∆φ. However ∆φ is unknown. Only an interval can be

determined. The delay added by the sampler, ∆T , ranges from 0 to Ts. This means ∆φ

lies in [0, ωoscTs]. If ωosc = 2 ∗ pi ∗ fs/6 for example, than ∆φ = π/3 which is quite a large

phase shift. Often multiple oscillation frequencies will be possible. If this is the case, it

is best to choose the highest possible oscillation frequency. This choice is supported by

simulation. Multiple possible oscillations will be closer examined later in this thesis.

To optimize the loop filter and the delay, it is necessary to be able to predict the SNR

of the system. An estimation of the SNR can be obtained through linearisation of the

system. There are two non-linear elements in the modulator: the comparator and the

sampling. The latter will be ignored for now. The input of the comparator consists of

ΔT Ts

Figure 2.7: Delay caused by sampling


an oscillation component and a much slower signal related to the input of the system U.

Luckily a comparator with two sinusoids as input has been linearized in literature[2]. The

comparator can be considered as an amplifier with two different gains provided one input

has a much lower frequency than the other. The gain of the fast input can be approximated

as Gc = 4πA , with A the Amplitude of this signal, and the slow signal gain is:

Gs =2

πA(2.5)

Now the amplitude of the oscillating signal can easily be calculated. The output of the

comparator is a square wave with an amplitude of one which can be approximated by the

first term of its Fourier series 4πsin(ωosct). This means the amplitude of the oscillation at

the input of the comparator is 4π |H(ωoscj)| and Gc = 1

|H(ωoscj)| . If z is approximated as

esTs , the NTF of the system becomes:

NTF =1

1 +GsH(s)DAC(s)e−sdTs(2.6)

By combining this with the Expression for the variance of the quantization noise (Eq 2.2),

the SNR can be predicted. Figure 2.8 shows the linearized system.

Note that it was assumed that the oscillation was a sine while in reality it is more like a

triangle wave. The harmonics of the oscillation were neglected. Of course this linearizion

is an estimation of the behavior of the system.

Up until now the effect of sampling was neglected. To include this effect, a transfer

function is needed in the Z domain. Such a loop gain exists as can be seen by cutting

the loop before the DAC, where the signal is digital, and calculating the loop gain around

this cut. To calculate the transfer function of a mixed discrete continuous system, the

Invariant impulse response Transform[1] can be used. First the loop gain in the S domain

is calculated by neglecting the sampling. Afterwards this transfer function is transformed

to the Z domain: LGeq(z) = IirTLG(s).This transformation takes following steps. First the impulse response of the S domain

loop gain is calculated using the inverse Laplace transform. Then this impulse response is

Σ H(s)U V

G

e−dsTs1−esTs

sTs

Σ

E

Figure 2.8: Diagram of linearized first order SOSD-modulator


sampled. Eventually the z transform of this discreet impulse response is produced. This

will be illustrated for a first order loop filter: H(s) = cs and a half clock cycle delay: d = 1

2 .

Assume the DAC has a NRZ pulse: DAC(s) = 1−e−sTs

s . It can easily be seen that full

clock cycle delays are transformed by the IirT into z−1. They will be neglected for now

and added later. The loop gain in the S domain equals

LG′(s) = Gsc

s2e−

sTs2 (2.7)

Where the extra s in the denominator is all that remains of the DAC for now. Next, the

inverse Laplace transform is calculated and the result sampled.

h(t) = L−1LG(s) (2.8)

= Gsc(t−Ts2

)u(t− Ts2

) (2.9)

h(n) = GscTs(n− 1/2)u(n− 1) (2.10)

Note that a half clock cycle delay in a unit step, u(t− Ts2 ), gives rise to a full clock cycle

delay in the sampled step. Finally the Z transform is calculated and the delays are added:

LGeq(z) = Zh(n)(1− z−1) (2.11)

= GscTs

(z−2

(1− z−1)2+

1

2

z−1

1− z−1

)(1− z−1) (2.12)

Figure 2.9 shows the magnitude and the phase for the S and Z domain loop gain. As you

can see, the error made by neglecting the sampling is only relevant for frequencies close

to the sample frequency.

In Equation 2.5 it was assumed that the output of the comparator is plus or minus

one. If this output level is called D, Equation 2.5 changes to Gs = 2DπA . As A, the

oscillation amplitude, is proportional to D, the operation of the system does not depend

10−5

10−4

10−3

10−2

10−1

100

−350

−300

−250

−200

−150

−100

−50

0

50

100

f*Ts

Mag

nit

ud

e in

dB

10−5

10−4

10−3

10−2

10−1

100

−280

−260

−240

−220

−200

−180

−160

−140

−120

−100

−80

f*Ts

Ph

ase in

deg

rees

Figure 2.9: Plot of magnitude and phase of LG in Z domain(blue) and in the S domain(red)


on D. However simulation shows, that halving D doubles the SNR. The more exact formula

given by [2] is:

Gs =2D

πBsin−1

(B

A

)(2.13)

This equation holds for a comparator with two inputs with amplitudes A and B, with A

larger than B, and if signal B is much slower than signal A. In equation 2.5 sin−1(BA

)was

approximated as BA , but in the actual system, A is not necessarily much larger than B. In

this case, Gs and thus the noise suppression does depend on D. A smaller D also causes

the system to become unstable at smaller inputs since overloading happens if the input is

larger than D. Considering this, D is chosen as large as allowed, which is about half the

supply voltage of the 65nm technology that will be used or about 0.5V.

Chapter 3

System design

3.1 A third order SOSDM

Figure 3.1 shows the system diagram of a third order modulator. As you can see the loop

Σ

DAC

U Vfs

z−d

1 bit

c1s

c2s

c3sΣ

g

DAC

z−12

1 bit

Figure 3.1: Diagram of the third order SOSD-modulator

filter has been realized using two feedback paths. This forms two loops: The inner loop

containing the integrator c3/s, and the outer loop containing all three integrators. Because

of the triple integration, the oscillation will be very weak in the outer loop provided the in-

tegration coefficients are smaller than the oscillation frequency. This means the first order

inner loop chiefly determines the oscillation frequency and amplitude and Equation 2.4

still holds approximately. The reason for this lay-out is the power consumption of the

circuit. The integrators are realized using op-amps. By containing the oscillation to the

inner loop, the bandwidth of the first two op-amps can be reduced which leads to lower

power consumption.

There is also a half clock cycle delay in the outer loop. This lowers the settling time

requirements of the two first op-amps without affecting the loop filter and oscillation to a

great extent.

To linearize this system the comparator is replaced by a gain G and the sampling is

13

Chapter 3. System design 14

neglected. z is again approximated by esTs and a non return to zero pulse is assumed for

the DAC’s. This leads to the following loop gain:

LG =GC3

s

c1(c2 + s)e−sTs/2 + (s2 + c1c2g)e−dsTs

s2 + c1c2g

1− e−sTss

(3.1)

This illustrates that the local feedback with gain g causes a pole at ωz =√c1c2g. Because

of the noise shaping (see Figure 2.3), the quantization noise is highest at high frequencies.

By placing the pole in the LG close to the bandwidth, the total amount of quantization

noise in the signal band is strongly reduced. The trade-off is a lower noise suppression at

low frequencies. Because of the pole, the low frequent noise is only suppressed with one

integrator, which is still enough.

The feed forward from the input U to the second adder leads to a STF closer to one

and hence reduces the output swing of the first integrator. Figure 5.32 shows this output

with and without the feed forward path. It is clear to see that the first op-amp has to be

able to produce a very rapidly changing output. This means there could be slewing which

will be discussed later.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

x 10−6

−0.2

−0.15

−0.1

−0.05

0

0.05

0.1

0.15Output OA1

t0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

x 10−6

−0.2

−0.15

−0.1

−0.05

0

0.05

0.1

0.15Output OA1

t

Figure 3.2: Output of first integrator with(left) and without(right) FF

To determine the error made by neglecting the sampling, the invariant impulse response

transformation is used to determine the loop gain in the Z domain. The magnitude and

phase of the loop gain in the S and Z domain are depicted in Figure 3.3. As you can see,

the mistake made by neglecting the sampling is very small and only significant for high

frequencies. However it is best to use the Z domain expression to determine the oscillation

frequency since a small error in the phase can lead to a different frequency.

Now that the system is linearized, it is possible to predict a SNR which will be verified

using a simulink simulation. However one problem still needs to be solved. As can be seen

on Figure 3.3, there are three different frequencies at which the loop gain becomes 180.

Figure 3.4 depicts a part of the Nyquist plot. Because the magnitude of the loop gain

varies if the oscillation frequency changes, the Nyquist curve can be stretched, depending


10−5

10−4

10−3

10−2

10−1

100

−100

−50

0

50

100

150

200

f*Ts

Mag

nit

ud

e in

dB

10−5

10−4

10−3

10−2

10−1

100

−400

−350

−300

−250

−200

−150

−100

−50

f*Ts

Ph

ase in

deg

rees

Figure 3.3: Bode plots of the loop gain in the Z domain (blue) and S domain(red)

Figure 3.4: Unscaled sketch of a part of the Nyquist plot

on the gain of the comparator.There are three possible oscillation frequencies. If the

system oscillates at one of these frequencies, that crossing point will shift to the -1 point,

depicted by the red dot, to make the loop gain equal to minus one.

Not all three points represent stable oscillations. Assume that the gain of the com-

parator is such that the -1 point is at the left of point 2, as it is depicted now. In that case

the minus one point lies at the right of the curve, which means there is a pole in the right

half of the complex plane. This is an unstable system that oscillates with rising amplitude.

As the amplitude rises, the gain of the comparator decreases together with the magnitude

of the loop gain, so the Nyquist plot shrinks and point two moves away from the minus

one point. Now assume that point two lies at the left of the red dot. Now the system is

stable because minus one is at the left of the Nyquist curve. The oscillation-amplitude

decreases and the comparator gain increases which makes the Nyquist plot expand. Again

point two moves away from the red dot. Using a similar analysis, it can be concluded

that the other two points move towards minus one if they are disturbed. So point one

and three represent stable oscillations. It is clear however that point three oscillates at a

smaller amplitude than point one as it needs more gain. So if the system starts from a


zero condition, an oscillation will start up with a rising amplitude until the amplitude is

high enough to support oscillation three. As this is a stable oscillation, the amplitude will

not rise further and point one will never be reached.

3.2 Results of the linear approximation

Figure 3.5 shows the simulated spectrum together with the predicted NTF in black. the

red line depicts the NTF of a corrected linear model where the fosc and the oscillation

amplitude are determined after simulation. both lines lie close to the simulated spectrum.

The SNR of the linear model is about 1dB higher than the actual SNR and after correction

with the actual fosc and amplitude the SNR is 0.4dB lower. The model predicts a Gs of

9 and a fosc of fs/5 while the simulation shows a Gs of 13 and a fosc of fs/3. The low Gs

is a result of the wrong prediction of fosc. The simulated system without an input shows

a fosc of fs/4 which is closer to the result of the linear model. fosc is clearly influenced by

the input signal which was not predicted. But although the model has it shortcomings, it

still predicts the SNR fairly well.

10−4

10−3

10−2

10−1

−160

−140

−120

−100

−80

−60

−40

−20

0

f*Ts

FFT(dB)

Figure 3.5: Simulated spectrum together with linear model(red) and adjusted linear model(black)

If the comparator is overloaded with a high input signal the system starts to oscillate

at a much lower frequency ( fs128 =

√c1c2g2π ). This corresponds to point one on Figure 3.4.

The maximum input signal lies around 80% of the comparator output level. This can

easily be explained by examining the Nyquist curve. If the amplitude of oscillation is too

big, the minus point will be at the left of the unstable point two. As was already discussed

the amplitude will build up until it reaches point one. point three and two are very close to

each other, which means a big input signal can easily push the system over the edge, even

if the amplitude of oscillation of the first point is very high. If the integrating coefficients

c1 and c2 are increased, points two and three will come closer to each other and the system

will more easily jump past point two.


3.3 Optimization

At first it was tried to optimize the system using the linear model as it should be accurate

enough to at least form a starting point for further optimizations. There are five param-

eters that can be considered for optimization. The integrating coefficients: c1, c2 and c3,

the delay d and the feedback gain g.

For ease of implementation, the delay is lower bounded to half a clock cycle. A higher

delay means a lower fosc and thus less quantization noise. However it also leads to a higher

amplitude of oscillation which lowers the comparator gain and thus noise suppression.

Simulation showed that small delay gives better performance, so d was chosen to be 1/2.

The coefficient c3 does not have much influence. It only scales the input of the com-

parator but it does not change the zero crossings, which is the only thing that matters for

the comparator. So c3 does not have to be included in the optimization. It does however

have an influence on circuit level. A large c3 leads to a high output swing and bandwidth

of the third op-amp. If c3 is too small, errors could arise because of a non-perfect com-

parator. Therefore a value of c3 is chosen through simulation, that offers a reasonable

output swing.

The feedback gain g determines, together with c1 and c2, the position of the zero in

the NTF. Although an unstable system oscillates at the frequency of the pole in the loop

gain determined by g, g does not influence the stability of the system. Figure 3.6 shows

the Nyquist plot for a system with g = 0. This system does not have a pole but it still has

a point of unstable oscillation and if the gain of the comparator is too small, the system

will still become unstable, with or without the pole. Furthermore it was assumed that the

optimal values of c1 and c2 do not depend on g. This greatly simplifies the optimization

and seems a valid assumption.

Figure 3.6: Nyquist plot of the loop gain with g equal to 0

In the end only c1 and c2 needed to be optimized and afterwards g was chosen to place

the pole at an optimal position. As stated before the linear approximation of the system

performs reasonably well. However when the coefficients were optimized, the resulting

system was unstable, even without an input. Here as before unstable means it started


to oscillate at a much lower frequency than expected. As stated before, increasing the

coefficients moves points two and three on the Nyquist plot (3.4) closer to each other.

Because of nonlinear effects, the amplitude of oscillation is able to become bigger than

the amplitude of the highest frequency oscillation and the unstable point two pushes it

towards the low frequency oscillation.

To save the linear model for optimization purposes it could be demanded that point

two and three remain at a certain distance of each other. However because of limited

time this possibility has not been fully explored and a brute force approach was used to

optimize the design. c1, c2 and c3 where chosen to be 2π0.015fs, 2π0.045fs and 2π0.0225fs

respectively. For this values, the SNR is about 75dB for a -8dB input at 10MHz. If full

scale is defined as D, although we can only go up to 0.8D, this is a -2dBFS input.

3.4 Slewing

An op-amp forming an integrator can be represented as a voltage controlled current source

loaded by a capacitor C. This means the rate of change of the output voltage is equal to

the delivered current divided by the capacitance. A rapidly changing output voltage can

only be delivered by a large current. However the op-amp is not able to produce an infinite

amount of current and the maximum current it is able to deliver is directly related to the

amount of power it consumes. This means the rate of change of the output is limited, and

when the output is changing at this maximum rate, the op-amp is slewing. Slewing is a

non-linear effect which introduces distortion in the SDM and degrades performance.

The feedback signal at the input of the first op-amp is the pulse width modulated

version of the input U. This means it contains two components: the slowly varying input

signal and the oscillation. The oscillation signal is the source of the slewing, but as this is

a non-linear effect, superposition no longer holds and the integrator is also non linear for

the slowly varying component. If the current runs out, it runs out for all inputs.

But even when the current remains under its maximum level, performance is still

degraded. Figure 3.7 illustrates this. The output current of the op-amp is only a linear

magnification of the input voltage as long as it remains small. The higher the current, the

more non-linear the integrator becomes and the more the performance is degraded. This

could be called soft slewing.

This problem mainly presents itself at the first op-amp because the input of the second

integrator is already softened by the first integrator and the third op-amp is loaded with

a smaller capacitance. Non-linearities are also less suppressed by the loop filter if they are

introduced close to the input. So the problem is caused by the oscillating component of

the feedback signal at the first op-amp. It is not necessary for the outer loop to process

this oscillation. It would be better if the first op-amp processes only the slow signal U

because of slewing and bandwidth limitations.


Figure 3.7: Slewing

To reduce the oscillation, a low pass filter was introduced in the outer feedback path.

However this filter changes the loop gain leading to a more complicated design. It changes

the loop filter into a fourth order instead of a third order filter. This is compensated by

adding a second filter that bypasses the first integrator as can be seen on Figure 3.8.

Σ

DAC

U Vfs

z−d

1 bit

c1s

c2s

c3sΣ

g

DAC

z−12

1 bit

11+sτ c1τ

1+sτ

Σ

Hc

x

y

Figure 3.8: diagram of the third order SOSD-modulator with Low-Pass filter and compensation

If a first order low pass filter is used, 11+sτ , the compensation filter, Hc, can be cal-

culated by demanding that the transfer function of the path between x and y remains

unchanged. The system with the filters satisfies:

y = −c1

s(

1

1 + sτx+ g

c2

sy)− xHc (3.2)

y

x= −

c1s

11+sτ +Hc

1 + g c2c2s2

(3.3)

In the system without filters Hc and τ are zero which means that Hc is subject to:


Hc +c1

s

1

1 + sτ=c1

s(3.4)

so

Hc =c1

s(1− 1

1 + sτ) (3.5)

=c1τ

1 + sτ(3.6)

If the compensation filter is dimensioned right, the oscillation is suppressed without

changing the operation of the system. There is however a trade off. If τ becomes too

large, the low pass filter affects the input component of the PWM signal. Normally the

error signal at the input of the first integrator does not contain a large contribution of U.

However if the feedback signal is low pass filtered, the phase of the input component of

the feedback signal changes a little, and the input is not completely eliminated. The first

op-amp receives a larger input and its output swing increases. Because this SOSDM will

be implemented in a 65nM technology with a supply of only 1.2V, this could become a

problem. Therefore a trade off will have to be made. The cut off frequency was chosen

to be five times larger than the bandwidth as simulation showed this offered a reasonable

output swing.

3.5 Noise

A major factor in determining the power consumption of the system is the maximum

allowed noise level. The circuit will consist of several resistors and transistors that will

create thermal and other noise. To determine the noise contribution to the output, several

noise sources are added to the model(Figure 3.9). One at each integrator input, one in

the local feedback loop before g and one before the Low pass filter. This is an accurate

representation as most resistors are connected to the input of the op-amps forming the

integrators and the noise of the op-amp themselves can be referenced to their inputs. Since

the SNR is around 75dB with a -8dB input, the amount of quantization noise is around

-83dB. This means that to not degrade the performance, the noise contribution should be

lower than this level. Therefore it will be demanded that the noise contribution in the

pass band is lower than -90dB. It is assumed that all three noise-sources deliver white

noise, so shot noise and 1/f noise will be neglected.

The noise source at the first integrator, N1, can be added to the input signal. This

means that the NTF1 is equal to the STF if there is no feed forward path from the input

to the third integrator. It was already determined that this STF approximates one, so the

noise of N1 is not suppressed. This means that the noise contribution of this source has

to be lower than -90dB. If Ng is substituted by a noise source after the gain g, this noise

contribution can also be added to the input. The transfer function NTFg is approximately


ΣU V

fsc1s

c2s

c3sΣ

g

DAC z−121 bit

Σ

N1 N2 N3

11+sτ

c1τ1+sτ

Σ

Ng

Σ

NLP

Σ

NLP

Figure 3.9: Model with noise sources

equal to g which leads to around 20dB suppression. This means the contribution of Ng

has to be smaller than -70dB. The source before the low pass filter can be replaced by

three sources. One at the input of the system, one at the input of the second integrator

and one at the input of the third integrator. Since the low pass filter offers almost no

attenuation in the pass band, the first restriction on NLP is that it has to be lower than

-90dB. With this restriction, the attribution of NLP two the input of the second and third

integrator is negligible.

The transfer function from N2 to V is given by:

N2

V=

1

1 + LG

Gsc3

s

c2s− gc1c2

s2 + gc1c2(3.7)

where LG is the loop gain. Figure 3.10a shows the transfer function from N2 to the output.

This NTF2 suppresses the noise with 20dB, this means the noise power in the pass band

of the source N2 should be smaller than -70dB. To easily calculate the contribution of N3

to the output, this source is substituted by a source after the comparator. To deliver the

same contribution, this source has to be of the form:Gs∗N3c3s . As this new source is in

exact the same position as the quantization noise source its NTF is the same: 11+LG so

NTF3 is:N3

V=

1

1 + LG

Gsc3

s(3.8)

NTF3 is depicted at Figure 3.10b. NTF3 suppresses the noise with 40dB, the result is that

the noise delivered by N3 should be smaller than -50 dB. During simulation it became clear

that too much noise could make the loop unstable. However this was only a problem at


10−4

10−3

10−2

10−1

−25

−20

−15

−10

−5

0

5

10

15

20

f*Ts

NTF2(dB)

(a) Transfer function from N2 to V

10−4

10−3

10−2

10−1

−80

−70

−60

−50

−40

−30

−20

−10

0

10

20

30

f*Ts

NTF3(dB)

(b) Transfer function from N3 to V

unreasonable high noise levels. To conclude this section, Table 3.1 shows the parameters

of the designed system.

Table 3.1: Parameters of the optimized system

Parameter system value circuit value

c1 2π0.015fs 30MHz

c2 2π0.045fs 90MHz

c3 2π0.0225fs 45MHz

fs 1 2 GHz

foscfs3 667MHz

fbfs100 20MHz

fLPfs20 100MHz

d 12 0.25ns

g 0.0901

D 0.5V

Chapter 4

The circuit

4.1 Top level

As mentioned before, the integrators are implemented using op-amps. Figure 4.1 shows

the realization of an integrator and the low pass filter. Because of negative feedback, the

op-amp will act as a nullator and offer a virtual ground at its input for differential signals.

This means x1 and x2 do not influence each other. If the gain is not high enough to offer

a perfect ground, which it never is, the inputs will interact with each other and there will

be some distortion. The output of this simple circuit is:

y = − v

R1Cs− x2

R2Cs(4.1)

Because a non-inverting integrator is needed, the wires will be crossed at the output. The

Voltage v is given by

v = x1

R1R1+RLP

1 + s2CLPRLPR1

R1+RLP

(4.2)

X2+ Y+

X2- Y-

+

--+

X1+

X1-

V+

V-

C

C

R1RLP

R2

CLP

RLP R1

R2

Figure 4.1: Circuit of integral of a sum of two signals, one of which is low pass filtered.

23

Chapter 4. The circuit 24

To find the response of this filter to differential signals, the capacitor had to be split up

into two capacitors in series. That is why the capacitance is double in Equation 4.2.

With this basic integrator and summing circuit, the total circuit can now be built.

However an adjustment has to be made. In the diagram of Figure 3.7, the output of Hc

is added to the output of the first integrator. This is not possible as the used integrator

circuit is only able to add signals at its input, not at the output. Also, in order to simplify

the system, the low pass filter and Hc will be merged since they are very similar. Figure 4.2

shows the final diagram of the system. Figure 4.3 shows the circuit. The three integrators

ΣU V

fsc1s

c2s

c3sΣ

g

DAC z−121 bit

11+sτ

Σ

c1τ

Figure 4.2: Diagram of the SOSDM as it will be implemented

and the comparator are clearly visible. The comparator is followed by a flip flop to realize

the sampling. The half clock cycle delay is implemented with a flip flop clocked at the

inverse clock. This second flip flop also inverts the signal. There are inverters between the

flip flops and the resistors. They serve a double purpose. Firstly they drive the resistor

with a voltage Vref . Vref is the equivalent of D, the output voltage of the comparator

on the system level. This voltage does not necessarily correspond to the digital voltage

supplied by the flip flops. Secondly they act as buffers between the analog and the digital

parts of the circuit. If the flip flops are too heavily loaded, their output voltage lowers

and they become slow. The buffer offers a lower capacitance and a high resistance. If

the capacitive impedance difference between the analog and digital part is too big, it is

possible that multiple inverters are necessary to minimize the delay. Because the two

feedback paths have a different loading, they have different buffers.


CLKN

VDD!

CM

Vref+

Vref-

Vref+

Vref-

Vref-

Vref+

Vref+

Vref-

CM

CM

CLK

VDD!

Bias

in-

in+

out-

out+

in+

in-

ref

out+

out-

in

Vref-

Vref+

out

in

Vref-

Vref+

out

in+

in-

ref

out+

out-

in

Vref-

Vref+

out

in

Vref-

Vref+

out

D

Dn

vdd

clk

out+

out-

in+

in-

ref

out+

out-

Vbias

in+

in-

vdd

out+

out-

D Dn

vdd

clk

out+

out-

RLP_a

CFB3_a

FF2

FF1

RLP_b

CFB3_b

Rin_a

Rin_b

RLP1_aCLP

RLP1_b

Rg_b

Rg_a

CFB1_b

CFB1_a

R12_b

RLP2_a

R12_a

RLP2_b

CFB2_a

CFB2_b

RLP3_a

RLP3_b

R13_a

R23_b

R23_a

RFB_a

R13_b RFB_b

RinFF_a

RinFF_bFigure

4.3:

Th

eto

ple

vel

of

the

circ

uit

.


4.2 Dimensioning the Passive components

The next step is to dimension the resistors and capacitors. To start all equations that

have to be satisfied are given. Rpar is the equivalent parallel resistance of RLP1, RLP2 and

RLP3. Lets first look at the circuit around the first op-amp:

1

Rg ∗ CFB1= g ∗ c1 (4.3)

1

RinCFB1= c1 (4.4)

2CLPRLPRparRLPRpar

= τ (4.5)

Here τ is the time constant of the low pass filter

RparRLP +Rpar

1

CFB1RLP1= c1 (4.6)

The equations for the circuit around the second op-amp are:

1

R12CFB2= c2 (4.7)

RparRLP +Rpar

1

CFB2RLP2= c1τc2 (4.8)

In Equation 4.8 c1τ is the gain of Hc. And the the third op-amp:

1

R23CFB3= c3 (4.9)

1

RinFFCFB3= c3 (4.10)

1

R13CFB3= c3 (4.11)

RparRLP +Rpar

1

CFB3RLP3= c1τc3 (4.12)

1

RFBCFB3= c3 (4.13)

Before these equations are solved, lets first discuss the influence of the values on the

performance of the circuit. The first constraint is the noise generated by the resistors.

This sets a maximum value on each resistance. Lowering the resistance however will

increase the capacitance of the feedback capacitors. This increases the output capacitance

of the op-amps which is bad for bandwidth and slewing and thus for power consumption.

Another incentive for increasing the resistor values is the resistive loading of the op-amps.

The lower this is, the more current the op-amp has to deliver to obtain a certain output

voltage. If the maximum deliverable current is too small, the output voltage will saturate

and this will degrade performance. To prevent this the current and the power consumption

will have to be increased. Apart from noise, the only drawback to large resistors is that


they require a large surface on the chip. A 100kΩ resistor is more than 45µm long, and this

will be taken as a maximum. So the resistors will be made as large as is allowed for noise

performance while keeping them smaller than 100kΩ. This is of course an arbitrary choice

and increasing this maximum resistance will decrease the power consumption as it leads

to lower capacitive loading and smaller resistive dissipation. The size of the capacitors is

also quite large and this should also be considered when choosing the resistor values.

Resistors generate white noise with a root mean square voltage of√

4 ∗ k ∗ T ∗R V√Hz

.

Here k is the Boltzmann constant, k = 1.38∗10−23 JK , and T is the absolute temperature in

Kelvin, which will be assumed to be 300K. Only the noise in the pass band is considered.

If the mean square of the noise voltage has to be smaller than a value V 2max in dB, then

the resistor will have to satisfy:

R <10

V 2max

10

4 ∗ k ∗R ∗ fB= Rmax (4.14)

here fB is the bandwidth of the modulator. RLP1 and Rin both correspond to N1 on

Figure 3.9 so their contribution has to be smaller than -90dB which leads to a Rmax of

3kΩ. RLP corresponds to NLP , which means it also has the same Rmax. Equations 4.4

and 4.5 show that Rg = Ring . However its noise contribution is also scaled with g so Rg

has a Rmax ofRin,max

g , which means that the noise requirement for Rg is satisfied, if it is

satisfied for Rin.

R12 corresponds to N2 and its Rmax equals 302kΩ This is limited to 100kΩ. RLP2

also corresponds to N2 so its Rmax is also 100kΩ. In fact, every resistor that is not yet

discussed is bounded by 100kΩ as they are allowed to be noisier than N2.

As there are 11 equations and 15 unknowns, 4 values have to be assigned to solve the

equations. Table 4.1 shows all the resistors and capacitors together with their values and

the maximum values for the resistors. Rin, R12, R23 and CLP were assigned before solving

the equations.

Due to a miscalculation the maximal value of R12 was mistakenly defined as 31kΩ

during the design of the modulator. This error was corrected too late to redesign. This

led to a slightly increased Power consumption as the minimal noise and load capacitance

of the second op-amp were too big. More importantly the load resistor of the first op-amp

could have been larger. The result will be a somewhat larger power consumption of the

system.

4.3 Preamp, Flip Flops and Buffers

The system has been simulated using a verilog model for the comparator as it has not been

designed. The comparator is not a critical component for the operation and its design

is rather simple. A possible implementation of the comparator could be a preamplifier

followed by a flip flop. This flip flop is also used to implement the half clock cycle delay.


Table 4.1: Values of the resistors and capacitors in the system.

Resistor Value Rmax

Rin 3kΩ 3kΩ

Rg 33.3kΩ 33.3kΩ

RLP1 913.7Ω 3kΩ

RLP 2kΩ 3kΩ

R12 31kΩ 100kΩ

RLP2 31.5kΩ 100kΩ

R23 100kΩ 100kΩ

RinFF 100kΩ 100kΩ

R13 100kΩ 100kΩ

RFB 100kΩ 100kΩ

RLP3 101.5kΩ 100kΩ

Capacitor Value

CLP 1.3pF

CFB1 1.77pF

CFB2 57fF

CFB3 35.4fF

A design was handed to me for the preamplifier and the flip flop. They will be discussed

for completeness and to estimate a total power consumption of the modulator. Figure 4.4

shows the preamplifier. It is a standard differential pair loaded by diodes. The power

consumption will mainly be determined by its GBWP. A good GBWP would be ten

times the oscillation frequency. This comparator is loaded by the flip flops. This digital

component has a very small input capacitance in the order of a fF. Since the preamp

is loaded with a high impedance and the input signal is already integrated, the power

consumption will mainly be determined by the GBWP and not by slewing or the voltage

across the output resistance. The current is determined by I = gmgmID

and gm is the

product of the GBWP and the load capacitance, CL. With gmID

= 15 and CL = 1fF , ID

becomes 2.8µA and the dissipated power 3.4µW . As will become evident later, this is

negligible compared to the power dissipated in the op-amps.

The flip-flops are depicted in Figure 4.5. It is very important for this component to

have identical rise and fall times. Simulation shows that if the rise and fall time differ

too much, this has a dramatic impact on the SNR. A difference of only two pico seconds

reduced the SNR with 7dB. Figure 4.6 shows an equivalent schematic. The first two

vertical inverters(4) have to force the rise and fall times to be equal. The two transistors

force one input low if the other is high. This increases the fall time. The first two horizontal

inverters(1) only react while the clock is high. The second pair(2) only reacts while the

clock is low. This means this flip flop is triggered on the falling slope of the clock. The last

two inverters(3) preserve the output voltage when the clock is high. They are the memory

of the system. If the clock is low, they offer a high impedance, and the second pair of

inverters can easily change the internal state. The second pair of vertical inverters(5) act

as a buffer, offering a clean digital output.


vddvdd

gnd!

vddvdd

gnd!

vddvdd

vddvdd

gnd!

Vbias

out-

in+

vdd

in-

out+

M9

M7

M3

M4

M8

M5

Figure 4.4: A possible circuit for the preamp

The flip flop circuit has no static dissipation. If the input and clock do not change,

the power consumption will be next to nothing. The only dissipation results from loading

and unloading the capacitors. The amount of energy stored on a capacitor is equal toCV 2

2 . During unloading of the capacitor, this energy is dissipated in resistive elements. If

the voltage on a capacitor is switched from V to 0 with a frequency of f , the dissipated

power is CV 2

2 f . There are several capacitors in the flip flops. Most are very small. The

biggest capacitors are the gate capacitors and they have a value of around 0.5 fF. The

voltage on these capacitors changes twice per oscillation period. If the input of the flip

flops rises , half the capacitors will load from 0 to V volts, and the other half will unload.

There are about 22 transistors whose gate capacitor is loaded once per oscillation period.

There are also 16 transistors that are driven by the clock. This means the dissipation

can be estimated by 22CV2

2 fosc + 16CV2

2 fs = 17µW . Most of this power comes from the

faster switching, clock driven transistors. There are two flip flops but even 34µW is small

compared to the power dissipation of the op-amps.

Most of the power consumption of the system will be in the op-amps. The flip flops

and preamp account for a small part of the power budget. The power consumption of the

buffers however could be quite large. Their output can be considered the superposition

of a differential and common mode part. The common mode voltage is constant and the

same at every node. This means no common mode current flows in the circuit. The

dissipation of the differential part is determined by the load resistance. Most resistors are

quite large and most differential signals rather small. However this is not true in the first

part. Due to noise limitations the resistors are small there. The series resistance of RLP

and RLP1 is approximately 3kΩ. They are by far the smallest resistors. The input of the

first op-amp offers a virtual ground for differential signals. The buffers switch between


+0.6 and -0.6V. For DC this gives rise to a current of 0.2 mA. This current is delivered

half the time by the first op-amp and half the time by the buffer. This gives rise to a total

power consumption of 0.48mW because there are two buffers. This consumption is quite

a large part of the total power budget. The other resistors are at least ten times higher

than these resistors so the other buffers have no significant contribution. We only included

static consumption in this analysis. The extra consumption caused by the loading of the

capacitors is given by CV 2

2 fosc, Where C is the load capacitance and V the difference in

voltage before and after loading. C is approximately CLP=1.3pF. Using Equation 4.2

we find that V is 0.06. So the dynamic dissipation is 2 µW which is small enough to be

ignored. This also means that the low pass filter did not introduce a significant amount

of extra dynamic dissipation because of higher capacitive loading of the buffers.

clk-

clk+

clk-

clk+

vddvdd

vddvdd

vddvdd

vddvdd

gnd!

gnd!

gnd!

vdd

gnd!

gnd!

gnd!

vdd

gnd!

gnd!

vddvdd

vddvdd

gnd!

gnd!

clk-

vdd

vdd

vdd

vdd

vdd

vdd

vdd

vdd

clk+

gnd!

gnd!

vddvdd

vddvdd

gnd!

gnd!

clk-

clk+

clk-

clk+

vddvdd

vddvdd

vddvdd

vddvdd

gnd!

gnd!

gnd!

vdd

gnd!

gnd!

gnd!

vdd

vddvdd

vddvdd

gnd!

gnd!

gnd!

gnd!

gnd!gnd!

gnd!gnd!

vdd

vddvdd

vdd

clk+

clk-

clk+

clk-

vddvdd

vddvdd

vddvdd

vddvdd

vdd

gnd!

gnd!

gnd!

vdd

gnd!

gnd!

gnd!

D

Dn

vdd

clk

out-out+

M23

M24

M25

M26

M29

M30

M27

M28

M31

M4

M20

M32

M21

M22

M34

M33

M41

M42

M35

M40

M38

M39

M36

M37

M52

M51 M55 M57 M56

M58

M43

M44

M45

M50

M46

M47

M48

M49

Figure 4.5: A flip flop circuit

CLK

CLK

CLK

CLK

CLK

CLK

D

Out

D

Out

1 2 3

4

5

Figure 4.6: The equivalent diagram of the flip flop circuit

Chapter 5

Op-Amp Design

The most crucial parts of the Sigma Delta Self Oscillating modulator are the op-amps.

They implement the integration and summation of the signals. If the integration coeffi-

cients are changed, the operation of the system will change and the loop could even become

unstable. They are also the components that consume the lion’s share of the power. Most

components are standard building blocks that only require a rescaling for this circuit. The

op-amps however were completely designed for this modulator.

5.1 Specifications

The op-amps have to comply with several specifications which will be discussed here.

5.1.1 GBWP

When the transfer function of the integrator circuit was calculated, it was assumed that the

op-amps had an infinite speed. It was taken for granted that the differential input signal

of the op-amp was forced to zero by the negative feedback, even for unlimited frequencies.

A more exact expression is found by assuming that the op-amp acts as an integrator with

gain A = 1τas

. This means it has a gain bandwidth product of 12πτa

. Figure 5.1 again

shows the simple integrator circuit but with only one input. The following is derived:

Y = −Aε (5.1)

ε = YsRC

1 + sRC+X

1

1 +RSC(5.2)

With τi = RC this becomes

Y

X=

−A1 + (A+ 1)sτi

(5.3)

Which for this op-amp reduces to

Y

X=

−1

s(τi + τa)

1

1 + s τiτaτi+τa

(5.4)

31

Chapter 5. Op-Amp Design 32

X+ Y+

X- Y-

+

--+

ε

Figure 5.1: The integrator

This means that instead of an integrator coefficient equal to 1τi

, the coefficient becomes1

(τi+τa) . This effectively lowers the coefficients which in turn degrades the performance of

the system. To prevent this, τa is made ten times smaller than τi. This is a specification on

the Gain Bandwidth Product of the op-Amp. Even with this specification, the integrator

coefficient will still be changed slightly. This could be compensated for by changing the

feedback around the op-amp so τi changes to τ ′i . If τ ′i equals τi−τa, the unity gain frequency

of the integrator will be exactly correct. The GBWP of the op-amp could even be lowered

to save power. However it is to be taken into account that changing the feedback also

changes the loading of the op-amp which influences its GBWP. Furthermore τa is less

precise than τi so this compensation technique will not be relied on too hard.

Not only will the integrator have a lower unity gain frequency, for higher frequencies

it behaves as a second order integrator. If τa is much smaller than τi, this happens at the

GBWP of the op-amp. This should not be a problem for the first and second op-amp.

For those high frequencies the signals are already very small and the extra phase shift has

not a great influence. However this could be a problem for the third op-amp as the phase

shift of the third integrator is a determining factor for the oscillation frequency. During

the design of the third op-amp measures should be taken to prevent the phase of the third

integrator from drifting too far from π2 .

5.1.2 DC Gain

It was assumed that the op-amps behaved as integrators, which is a good assumption for

high frequencies. However it requires an infinite gain at DC which is clearly not realistic.

In reality the op-amp will behave more like a low pass filter with a finite DC gain ADC .

To determine the effect of a finite gain A is replaced by ADC in Equation 5.3.

Y

X≈ −ADC

1 +ADCτis(5.5)

Here ADC was assumed to be bigger than one. It is clear that the integrator is in fact a

low pass filter. There will be a finite suppression of the low frequent noise instead of an


infinite one. This is not a major problem as long as ADC is large enough. The effect will

be a lower bound on the transfer function of the quantization noise. The zero placed near

the bandwidth will no longer be a perfect zero. To determine the needed ADC the system

is integrated with low pass filters instead of integrators. If all op-amps have an ADC equal

to 200, the resulting SNR is degraded by less than 1dB. There is another effect of finite

ADC (and GBWP). If the ADC is too small, there will be distortion as multiple inputs of

an integrator start to interact. Therefore it is better to realize a higher ADC. With this

in mind the number of stages of the op-amps where chosen to be three. This offers more

than enough gain at almost no extra cost.

5.1.3 Slewing

DC-gain and GBWP are both linear specifications in that they both specify the linear

operation of the op-amp. To prevent the op-amp from operating as a non-linear component

a minimum current Imin will have to be delivered to prevent slewing. An approximate

result will now be derived for this Imin. Assume a sine input with frequency fin and

amplitude Ain. The amplitude at the output of an integrator cs , will be:

Aout = Ainc

2πfin(5.6)

so

Imin = CL

(dV

dt

)max

(5.7)

= CL2πAoutfin (5.8)

= CLAinc (5.9)

The result is that the current needed to prevent slewing does not depend on the rate of

change of the input. Although a faster changing signal will need more current to load the

capacitor to a certain voltage, this voltage will be lower because of harder suppression by

the integrator. Of course it was assumed that the circuit still operates as an integrator

at high frequencies, which would assume an infinite GBWP. However Equation 5.4 shows

that if the input is too fast for the integrator circuit, it will act as a double integrator

which would even lower the needed current further. It can be concluded that Equation 5.9

is a good upper boundary on the amount of current needed to prevent slewing.

5.1.4 Other Specifications

Another non-linear specification is the deliverable DC-current. Apart from CL, the op-amp

is also loaded by a resistor. This means the op-amp has to deliver a current to generate a

voltage. This leads to the following demand IDC >VDD2RL

where VDD is the supply voltage

which is 1.2V

Linked to the output swing is the common mode voltage. This voltage is taken to be

600mV both for the output as the input common mode voltage for all three op-amps and


the comparator input. This voltage is half the supply. For simplicity the input and output

common mode voltage were chosen the same. A lower input common mode voltage and

a higher output common mode voltage would have been better for output swing but it

would make the circuit more complicated.

Not only the resistors generate noise, also the transistors. Although every transistor

is noisy, most of the noise is determined by the first stage. This noise is amplified by all

following stages. This noise will be represented as a voltage source at the input of the

op-amps. If only white noise is included, the mean square voltage of this source is:

2

3

4kTα

gm(5.10)

α is the equivalent amount of noisy transistors in the first stage. For this design this

will be smaller than four for all op-amps. α will be determined more accurately during

the design of the first op-amp. It will be demanded that this noise is less than the noise

generated by the resistor at the input of the op-amp.

A last important specification is of course stability. A phase margin of 60 will be

demanded for each op-amp, which is a much used number.

The first and second op-amp have been designed and simulated. The design of the

third op-amp is very similar to the design of the other two op-amps but has not been

implemented.

5.2 General Feed Forward Op-Amp Design Flow

This design flow is largely based on an internal paper by Professor Rombouts. Because

the purpose of this thesis is to design a low power ADC, the Feed Forward architecture is

a good choice. To stabilize, it puts parasitics at frequencies lower than the dominant pole

instead of higher. As faster circuits use more power, this is a low power solution. The slow

impulse response of the FF op-amp is not a problem for this modulator. The behavior in

the frequency domain is what determines the performance of our modulator. As stated

before a three stage op-amp will be used because of DC gain considerations. A general

design flow will now be outlined for such op-amps. The goal is to determine the transistor

dimensions and the current source of the differential pairs. There are five differential pairs

to dimension: three stages and two feed forward stages.

Figure 5.2 shows the small signal circuit of the op-amp. The R’s and C’s are the total

output resistances and capacitances of the stages. This means the DC gain is given by

−gm1R1gm2R2gm3R3−gmFF2R2gm3R3−gmFF3R3. However the DC gain will not be used

as a specification anymore because it already determined the amount of stages. Therefore

from now on it will be assumed that the output resistances is infinite. To further simplify

the design, the two zeros are placed at the the same frequency. This means the following



V1 V2 Vuit

gmFF2Vin gmFF3Vin

Figure 5.2: The small signal circuit of a three stage FF op-amp

transfer function is targeted:

H = − 1

sτ1

(1 + sτ2

sτ2

)2

(5.11)

Clearly the op-amp behaves as a third order integrator at low frequencies, but as a first

order integrator near the unity gain frequency. The phase margin of this system rises if

this switch over point between third and first order lies further from the GBWP, 12πτ1

. To

have a phase margin of 60, τ2 should at least be 4 times higher than τ1. It will not be

made smaller either to offer enough gain. First the equations linking the time constants

to the circuit are written down :

−H =1

sτ1

(1 + sτ2

sτ2

)2

(5.12)

=1

sτ1+

2

s2τ1τ2+

1

s3τ1τ22

(5.13)

And from Figure 5.2:

=gmFF3

sC3+gmFF2gm3

s2C2C3+gm1gm2gm3

s3C1C2C3(5.14)

So:gmFF3

sC3=

1

sτ1(5.15)

gmFF2gm3

s2C2C3=

2

s2τ1τ2(5.16)

gm1gm2gm3

s3C1C2C3=

1

s2τ1(τ2)2(5.17)

The first and second stage can’t be dimensioned yet because C1 and C2 depend on the

dimensions of the third stage. That is why the design starts at the last stage and works

its way back.

step1: gmFF3

There are several restrictions on gmFF3. Firstly the GBWP specification, which together

with Equation 5.15 gives:gmFF3

2πC3> GBWP (5.18)

Note that C3 is not known exactly as it also contains some drain gate and drain source

capacitance from the transistors that still need to be dimensioned. But these capacitances


are lower than CL, the load capacitance of the op-amp. So CL is a good estimate for C3.

If capacitive sensing is used for the common mode feedback, than this contribution to C3

should not be forgotten.

To prevent slewing, the third stage has to be able to deliver a certain current Imin.

This gives us a second restriction:

gmFF3gmID

> Imin (5.19)

The value of gmID

is a design choice. A high gmID

offers low power in exchange for large

dimensions. A good value of gmID

depends on the technology that is used. Linearity of

the transistor should also be considered while choosing gmID

. Note that different stages can

have a different gmID

. Now gmFF3 is determined by the most demanding restriction.

step2: gm3

gm3 is chosen as follows:

gm3 =gmFF3

SF3(5.20)

Here SF3 is an arbitrary scale factor. It is better for power consumption to make SF3 big.

However gm3 must not become too small as not to violate the following specification:

gm3gmID

> Imin =VDD2R3

(5.21)

It must not be forgotten that R3 does not only include the external load resistance, but

also the resistors used for the common mode feedback. Note that it was assumed that the

third feed forward stage does not contribute to the DC current. Because of stability the

none-feed forward stages are made slower than the feed forward stages. However at low

frequency they have a much higher gain than the feed forward stages. This means that

because of feedback, the input voltage of the op-amp will be very low at DC and almost

no current will be delivered by the feed forward stages. That is why the third stage has

to deliver all the DC current.

gm3 is determined by the most stringent constraint and SF3 is updated. It is possible

that gm3 becomes bigger than gmFF3. This is not desired. If this is the case, gmFF3 will be

increased to the value of gm3. Now the input capacitance of the third stage is calculated.

This approximates C2.

step3: gmFF2

Equation 5.16 is rewritten using Equation 5.15 and Equation 5.20:

gmFF2 =2SF3C2

τ2(5.22)

step4: gm2

As before gm2 is a scaled version of gmFF2:

gm2 =gmFF2

SF2(5.23)


If the common mode feedback resistors are not negligible, enough current will have to be

delivered to produce a high enough output voltage. But in this design the common mode

feedback of the second stage is not implemented with resistors as this would eat away

the gain and ask a lot of space. Now the input capacitance of the second stage can be

determined. This will be the major part of C1.

step5: gm1

Equation 5.17 is rewritten :

gm1 =C1SF2

τ2(5.24)

step6: Noise

Use Equation 5.10 to check if gm1 is big enough for noise constraints. If gm1 is too small,

add an explicit capacitor C1e at the output of the first stage. Set gm1 to its minimal value

and size C1e as follows:

C1e =gm1τ2

SF2− C ′1 (5.25)

Where C1 = C ′1 + C1e

step 7: gm2 and gmFF2

If gm1 is very different from gm2, an explicit capacitor can be added to C2. Recalculate

gm2, gmFF2 and C1e.

During several steps approximations were made. This means this is an iterative pro-

cedure. All three output capacitors contain parasitics that are not known up front. If C3

contains a large parasitic contribution, the GBWP and the phase margin will be reduced.

An underestimation of C1 and C2 increases stability at the cost of some gain. Even if

the estimate of the output capacitances is correct, the phase margin will still be higher

than 60. It was assumed that the phase of the op-amp was −270 for low frequencies but

this phase is in fact higher because the output resistors were neglected. If the resulting

phase margin is much more than desired, it can be traded for a higher gain. Slewing was

only discussed at the output of the op-amp. But if the output stage is very large, C2 is

very big and there could be slewing at the second stage. Therefore it should be checked

through simulation that at no point during operation, the current delivered by any stage

approaches its maximum value too close.

5.3 Design

All three op-amps will have a very similar architecture: A three stage feed forward op-

amp. There will be differences concerning the common mode feedback of the last stage

and whether or not there is cascode in the first stage. The architecture will be discussed

while going over the first op-amp.

It was already decided to use three stages, however to boost the gain, the first stage will

be implemented with a telescopic cascode. Figure 5.3 shows a cadence plot of the first stage


together with the bias circuits and the common mode feedback. Names of components of

the circuit will be written in italics. The core of this stage is the differential pair: T1n a,

T1n b with cascode transistors: TCn a, TCn b. This is loaded with a current source:

T1p a, T1p b which is also cascoded: Tcp a, Tcp b.

5.3.1 CMFB

T1CM is a triode transistor. Its gate voltage is the output voltage. It implements the

common mode feedback. The gate voltage of T1p is given by VDD − RT1CMID1 where

ID1 is the current flowing through T1CM. If the output common mode voltage rises, the

resistance of T1CM becomes bigger and the gate voltage of T1p in turn falls. This lowers

ID1 and since TCp is a current buffer, this also lowers the output current which in turn

lowers the output common mode voltage. The bias circuit generates Vbias such that T1p

injects a current equal to half the current of Istaart1 if the output common mode voltage

is equal to the voltage generated by refintern.

A big advantage to this kind of common mode voltage feedback is that it doesn’t load

the output of this stage with a low resistance or a high capacitance. It only loads the

output with the gate capacitance of T1CM. This capacitive loading is not an issue as a

big capacitor already has been placed to preserve the stability. Resistive loading of this

stage however would lower the gain. The high output impedance created by the cascode

would be in parallel with the much lower resistance of the common mode feedback. This

common mode feedback resistance can’t be made very large because its dimensions would

be unreasonably high. The disadvantage of this implementation is that it is only accurate

for a low output swing. Since this is only the first stage, the output swing at this point

is rather small. For a reference voltage of 600mV, the output common mode becomes

643mV. As expected this is not very accurate but it will do.

5.3.2 Outputswing

The output swing of this stage is given by:

VCM,in − VGS,T1n + VDsat,T1n + VDsat,TCn < Vout < VDD − VDsat,T1p − VDsat,TCp (5.26)

This means a lower VCM,in offers a higher output swing. For minimal VCM,in this becomes:

VDsat,Tstaart1uit + VDsat,T1n + VDsat,TCn < Vout < VDD − VDsat,T1p − VDsat,TCp (5.27)

The voltage over T1CM was neglected. Since this transistor is in triode its VDS is rather

small. After the first stage is dimensioned the maximum output range can be put in

numbers: 0.2690 < Vout < 0.9540. This has a midpoint of 0.6115 and a total swing 0.6850.

However with an input common mode of 600mV this becomes: 0.3972 < Vout < 0.9540.

The middle point is now 0.6756 and the swing 0.5568. However simulation showed that


the needed output swing for this stage is not even 50mV so there is more than enough

swing and the input common mode voltage is not critical.

5.3.3 Cascode

Figure 5.4 shows the small signal equivalent for differential signals of the first stage. For

simplicity it is assumed that the n and corresponding p transistors have the same small

signal parameters. Lets first calculate the output impedance of the upper cascode:

R′out =Y

IL(5.28)

= (1 + gmcR1)Rc +R1 (5.29)

≈ gmcR1Rc (5.30)

This impedance is in parallel with the output impedance of the lower cascode. The cascode

transistor acts as a current buffer which means Iout approximates gm1Vin. This makes for

a DC gain of gm1R′out/2 = gm1Rout. There are two poles: a dominant pole caused by

the load capacitance of the stage, and a pole caused by the capacitance on point X. The

resistance at X is approximately 1gmc

because the cascode transistor offers a low input

resistance due to its operation as a current buffer. With these poles the total transfer

function becomes:Y

X=

gm1Rout

(1 + sC1Rout)(1 + s CXgmc

)(5.31)

The effect of C1 was included in the previous stability analyses, however CX was not

brought into account. This pole has to be at a higher frequency than the GBWP of the

op-amp to ensure stability. This should not be a problem because CX is much smaller

than CL but if it is a problem it can be solved by increasing gmc.

5.3.4 Biassing

Figure 5.3 shows four bias circuits. The biasing of the tail transistor is rather straight-

forward. It is more difficult to produce the biasing voltages of the cascode transistors.

VCBiasn has to be large enough to prevent the two lower transistors from going into

triode mode. It has to be equal to 2VDsat + VGS + margin. From this bias circuit it is

derived that VCBiasn = VDS,TCBiasnstaart +VDS,TCnBias triode +VGS,TCBiasnin. To ensure

that this is large enough, TCnBias triode is a downsized version of TCn. The smaller it

is made, the larger the voltage across it will be and the higher the margin will be. The

channel width of TCnBias triode is made five times smaller than the width of TCn. The

other bias circuits are similar. To reduce the power dissipated in the bias circuits, the

injected current and the width of the transistors are also scaled. Preferably the amount

of fingers is reduced so the width per finger remains the same. It is important that the

bias circuit of TCn is scaled. Not only because of power consumption, but because it is


out1+

gnd!

VDD!

VDD!

VDD!

Vref

VBias2

gnd!

gnd!

VBias2

VDD!

VDD!

VDD!

VDD!

Vref

Vbias

out1-

out1-

gnd!

VDD!

VDD!

Vbiasstaart1

gnd!

out1-

VDD!

Vbias

VCBiasn

gnd!

VBias2 VDD!

VDD!

gnd!

out1+

out1+

Vbiasstaart1

gnd!

gnd!

VDD!

gnd!

VCBiasn

in+ in-

TCp_scsc

TCpBias_triode

T1CM_scsc

Tstaart1in Tstaart1uitTCBiasnstaart

ICM1_sc

refintern

T1CM_sc

T1p_sc

Istaart1

ICM1

TCp_sc

TCn_a

TCp_a

T1p_a

Cint1_b

T1n_a

T1CM_a

T1n_b

T1CM_b

Cint1_a

T1p_b

TCp_b

TCn_b

ICBiasn

TCBiasnin

TCnBias_triode

Figure 5.3: The first stage of the first op-amp

Y

gm1Vin

-gmcX

gmcZ

R1

Rc

Rc

R1

X

Z

Figure 5.4: The small signal circuit of the first stage of the first op-amp


directly connected to the first stage and can introduce an error in the biasing current of

this stage.

5.3.5 Other Stages

The other stages and the feed forward stages are standard differential amplifiers without

cascode and are depicted in Figure 5.5 and Figure 5.6.

The second stage uses the same kind of common mode feedback as the first stage. The

output common mode voltage is 746.8mV. This is a large error because the reference was

also 600mV. It needs an output swing around 120mV. This stage doesn’t use cascode so

the output range is:

VCM,in − VGS,T2n + VDsat,T2n < Vout < VDD − VDsat,T2p (5.32)

0.3430 < Vout < 1.04 (5.33)

The swing is 0.697 and the midpoint 0.6915. Clearly the output swing is high enough.

The feed forward stage does not restrict the output swing as it has a lower input VCM,in.

Only the third stage uses common mode feedback with capacitive and resistive sensing.

The reason is that the output is already loaded with a large capacitor and a low resistor.

The extra loading from the common mode feedback doesn’t make a large difference here.

Furthermore, the output swing at this point is higher so the conventional common mode

feedback is more accurate here. The circuit is depicted at Figure 5.7.

The gain is gmn/gmp which is close to one. The total gain of the common mode

feedback is:gmngmp

gmT3pR3 (5.34)

Because the third stage needs a large bandwidth, it has large transistors.This means the

common mode feedback has a large load capacitance and so stability could become a

problem. The time constant of the output pole is CL,CM/gmp where CL,CM is mainly the

gate source capacitance of T3p. For the common mode feedback loop to be stable it is

needed that:CL,CMgmp

<C3

gmT3p(5.35)

with C3 the outpout capacitance of the third stage. This kind of common mode feedback

has clearly a high gain as the output common mode voltage is 602.3mV. This is a deviation

of only 2.3mV. The current source of the CMFB is a scaled version of the current flowing

through T3p. The pmos transistors of the CMFB are also scaled versions of this transistor.

Connecting them like diodes ensures that they are in saturation which is where T3p needs

to be. The same form of biasing is used for all the non-cascode transistors.

The third stage needs an output swing of 286mV. The expression of the output range

is the same as Equation 5.32. In numbers this is:

0.419 < Vout < 1.042 (5.36)


Figure 5.5: The second stage of the first op-amp

Figure 5.6: The third stage of the first op-amp


VDD!

gnd!in-

in+CMFB

CMref

R1

R0

C0

C1

Tn_a

Tp_a

I0

Tp_b

Tn_b

Figure 5.7: The common mode feedback circuit of the last stage of the first op-amp

which offers a swing of 623mV and the center point is 730.5mV. The output feed forward

stage also does not restrict the swing because of its lower VCM,in. There is enough swing

for this stage but the output voltage comes close to its minimal value during simulation

(466mV). So in further design it should be considered to lower the reference voltage of the

second stage so its output common mode is lower.

5.3.6 Noise

The equivalent noise source at the input of the op-amp needs to be determined. As

previously mentioned, only the noise of the first stage is significant. The mean square of

this voltage is given by Equation 5.10 so α, the equivalent amount of noisy transistors,

has to be found. It is clear that the transistors of the differential pair contribute directly

to the noise. The noise current of T1p, InT1p, is buffered by the cascode transistor TCp.

This means it contributes directly to the output voltage as Vout,nT1p = InT1p ∗Rout. If this

is divided by the gain the equivalent input noise is derived:

Vin,nT1P =Vout,nT1p

gm1Rout(5.37)

=InT1p

gm1(5.38)

The mean square of InT1p is 234kTgmT1p. This leads to a total contribution from T1p and

T1n to α as:

α = 2 ∗ (1 +gmT1p

gmT1n) (5.39)

However the cascode transistors are noisy too. Figure 5.8 shows the small signal

equivalent of the first stage. The loading of the cascoded differential pair is represented

as a resistance=R′out. The noise of the biasing and common mode feedback circuits is not


included. Their noise will only contribute to the common mode voltages of the circuit

which is not a problem for performance. There is one noise-current source representing

the noise produce by TCn. The analysis for TCp is similar. The input voltage is put to

zero as it is not relevant for this analysis. The contribution of In to I1 needs to be found

. The input voltage corresponding to I1 is I1gm1

. From this circuit the following equations

are derived:

X = I1R1 (5.40)

I1 = In − gmCX +Y −XRC

(5.41)

Y = −I1R′out (5.42)

After solving this becomes:

I1

In=

RCRC + gmCR1RC +R′out +R1

(5.43)

BecauseR′out and gmCR1RC are very large, the noise contribution of the cascode transistors

is negligible and Equation 5.39 holds. During the design α will still be assumed to be four

as a worst case scenario.

Y

-gmcX Rc

R1

X

R'out

In

I1

Figure 5.8: The small signal equivalent of the first stage of the first op-amp with added noise

source

5.3.7 Op-Amp1

The specifications of the first op-amp are summarized in table 5.1. CL and RL already

include the loading by the common mode feedback. To calculate Imin,slewing, Ain needs to

be known. The oscillation is suppressed by the low pass filter with a cut off frequency atfs20 = 100MHz. So a sine input with frequency fs

3 = 667MHz and an amplitude of 0.6V,

is suppressed to an amplitude of 90mV. This leads to a minimal needed current of 32µA.

Without the low pass filter, Imin would be 215µA. The maximum deliverable current of the


designed op-amp delivers 422µA. This means that in this design slewing was not the main

factor determining the power consumption. The low pass filter just increased linearity due

to soft slewing. Now that all the specifications are lined up the first op-amp can finally be

dimensioned. During the dimensioning the previously outlined steps were followed, but

because this is an iterative procedure, only the results will be given. Note that whenever

a certain current is given, this is the current flowing through one transistor. If the power

consumption needs to be calculated, these currents will have to be doubled.

The current flowing through the third feed forward stage is 211µA. This is much larger

than Imin,slewing so the power consumption of this stage is determined by the GBWP. In

fact the power consumption is really determined by noise specifications. Due to noise, Rin

needed to be small which in turn made CL large. there is a clear trade off here between

performance and power consumption. If more noise is allowed, the power consumption

will be lowered. A gmID

of 17 was used, and it will be used as a default without always

mentioning it. The length of the transistor is 180nm. This length was chosen larger than

the minimum allowed length of 60nm because it offers a larger gain.

The third stage has a current of 101µA. This is determined by the resistive loading of

the stage. This is also one of the largest power consumers of the circuit. The gmID

forT3p

is 10. This reduces the dimensions of this big transistor. The trade off is a smaller CMFB

gain. This also improves the stability of the common mode feedback as it reduces the

capacitive loading and shifts the dominant pole to lower frequencies.

IDFF2 is 6µA. There is an explicit capacitor of 22.5fF at the output of this stage. This

is the value of the differential capacitor. It is implemented with two capacitors in parallel

with each a fourth of this value. The reason for this capacitor is the high gm of the first

stage. The channel length of TFF2 is 240nm. This increases gain while this transistor

remains rather small.

The second stage has the same current as the second feed forward stage, SF2 = 1,

because this stage uses very little power and to keep it from getting much smaller than

the first stage. Even with this explicit capacitor and SF2 = 1 the ratio of gm1 over gm2 is

still 8. The length of the p and n transistors is 360nm. The gmID

of T2p is 10 to reduce its

surface-size.

Table 5.1: Specifications of the first op-amp

GBWP 300MHz

PM 60

RL 23.7kΩ

CL 1.87pF

Rin 3kΩ

Imin,slewing 32µA


The first stage has a current of 52µA. This is determined by noise requirements. It was

demanded that the equivalent input noise voltage was less than the noise voltage created

by the input resistor. α was assumed to be four. For T1p gmID

also was 10. This means the

actual α is 3.2. So we have some margin on our noise. Because of the noise requirement

an explicit capacitor of 1.88 pF had to be placed to keep the op-amp stable. This means

the first stage is as heavily loaded as the third one. The lengths of T1n and T1p were also

240nm. The cascode transistors were dimensioned with the same length and gmID

as T1n.

Simulation of the op-amp showed a GBWP of 288 MHz and a DC gain of 83dB. The

phase margin was 67 and the unity gain frequency of the integrator was 30.27MHz. This

could be compensated for by increasing CFB1 a little. Figure 5.9 shows the bode plot

of the op-amp and Figure 5.10 shows the bode plot of the integrator formed with this

op-amp. Table 5.2 shows the channel widths and lengths of the transistors of the first

op-amp together with the dimensions of the CMFB resistor. The biasing transistors were

not included since they are just scaled versions of the transistors they are biasing. Also

the tail transistors were not included. They have the same length and the double width

of the TXn transistors. The power consumption of this op-amp is 0.9mW. This does not

include the consumption of the biasing circuits and the common mode feedback circuit.

5.3.8 Op-Amp2

The architecture of the second op-amp is the same as the first one with one difference.

Because the output resistance of the second op-amp is higher than the first one, the same

kind of CMFB will be used as in the first and second stage of the first op-amp. If resistive

sensing of the common mode voltage would be used here, the gain would be halved.

Table 5.3 shows the specifications on the second op-amp. This op-amp needs a higher

GBWP than the first one, but its load capacitance is much smaller. Figure 4.2 shows that

the second op-amp has two inputs. One input is low pass filtered and integrated, the other

is only integrated. The amplitude of this second input signal is:

Ain = 0.6 ∗ c1

2πfosc= 27mV (5.44)

From Equation 5.9, with c= 0.0452πfs, Imin is 0.87µA. This means slewing will not be a

problem.

The design of this op-amp will not be discussed with as much detail as the the design

of the first op-amp. Table 5.4 shows the needed and available output swing for every stage.

It is clear that this is never a problem. Table 5.5 shows the dimensions of the transistors.

Figure 5.11 shows the bode plot of the op-amp and Figure 5.12 shows the bode plot of the

second integrator. The GBWP of the second op-amp is 854MHz, the DC gain 80dB, the

unity gain frequency of the integrator is 90.68MHz and the phase margin 73. The total

power consumption is 0.1mW. For this design, a gmID

of 15 was used. Because this op-amps

power consumption is almost a tenth of the previous one, a lower gmID

was used because


50.0

100.0

150.0

0.0

V (deg)

200.0

-50.0

-25.0

0.0

V (dB)

100

50.0

75.0

25.0

freq (Hz)10

210

810

610

710

110

-110

010

910

1010

410

510

3

Figure 5.9: The bode plot of the first op-amp

Phase (deg) 100.0

50.0

-50.0

0.0

150.0

-100.0

200.0-75.0

-50.0

-25.0

0.0

25.0

50.0

75.0

100

(dB)

103

freq (Hz)10

010

110

210

410

510

610

710

810

910

1010

11

Figure 5.10: The bode plot of the integrator formed by the first op-amp


Table 5.2: The channel widths and lengths of the transistors of the first op-amp

Name Width(µm) Length(um)

T1n 9.69 0.24

T1p 7.52 0.24

TCn 7.75 0.24

TCp 31.56 0.24

T1CM 3 0.06

T2n 1.45 0.36

T2p 2.3 0.36

TFF2n 0.93 0.24

T3n 11.55 0.18

T3p 28.51 0.18

TFF3n 24 0.18

RCM 0.4 45.2

power consumption was less critical. However, one could just as easily increase gmID

and

trade larger dimensions for lower power. The reason why the second op-amp uses less

power is mainly its low load capacitance and high load resistance. IDFF3 = 22.4µA is

determined by bandwidth requirements. ID3 = 12.1µA is determined by resistive loading.

There is no explicit capacitor at the second stage. To comply with noise requirements and

keep the system stable, there is an explicit capacitor of 51 fF at the output of the first

stage. The first stage dissipates approximately 11.3% of the total power of this op-amp.

However, as was already mentioned, the noise requirements for the second op-amp could

be relaxed.

5.3.9 Op-Amp3

The specifications of the third op-amp are similar to those of the previous two op-amps

with one exception. The phase shift of the third integrator determines the oscillation

frequency. On Figure 5.12 it is clear that for this op-amp the phase is much lower than

Table 5.3: Specifications of the second op-amp

GBWP 900MHz

PM 60

RL 100kΩ

CL 58fF

Rin 31kΩ

Imin,slewing 0.87µA


Table 5.4: The needed and available output swing of the stages of the second op-amp

Stage Vout,CM (V ) minimum(V) center(V) maximum(V) swing(mV) needed swing(V)

1 0.751 0.386 0.711 1.035 0.649 0.01

2 0.741 0.445 0.743 1.04 0.595 0.081

3 0.579 0.392 0.7134 1.035 0.643 0.167

Table 5.5: The channel widths and lengths of the transistors of the second op-amp

Name Width(µm) Length(nm)

T1n 0.94 240

T1p 3.98 240

TCn 0.75 240

TCp 3.05 240

T1CM 3 60

T2n 0.27 360

T2p 0.63 360

TFF2n 0.17 240

T3n 0.94 180

T3p 3.33 180

TFF3n 1.88 180

M26: 854.4241MHz, 0.0dB

0.0

V (dB)

-25.0

100

25.0

75.0

50.0

M27: 854.424MHz, 73.4045dM28: 854.424MHz, 73.4045d

0.0

50.0

150.0

100.0

V (deg)

200.0

106

freq (Hz)10

1010

110

510

810

-110

910

710

010

210

410

3

Figure 5.11: The bode plot of the second op-amp


100.0

150.0

200.0

Phase (deg)

-100.0

-50.0

0.0

50.0

50.0

75.0

100 (dB)

-50.0

-25.0

0.0

25.0

104

105

106

107

108

109

1010

freq (Hz)10

010

110

210

3

Figure 5.12: The bode plot of the integrator formed by the second op-amp

90 at the oscillation frequency. It was already determined that for frequencies higher

than the GBWP, the integrator is actually a second order integrator(Equation 5.4). This

means the bandwidth might need to be increased to even higher frequencies. A GBWP

of ten times the oscillation frequency is probably needed to guarantee that the oscillation

frequency doesn’t change. An estimate of the power consumption can be made for a

GBWP of 6GHz. The op-amp is loaded by the comparator which has a very high input

impedance. It can be assumed that SF3 is high and ID3 can be neglected. The noise

requirements for this op-amp are less stringent than they were for op-amp2 which means

that ID1 can also be neglected. This means only IDFF3 has to be taken in account. For

CL of 35.4fF and a bandwidth of 6GHz, gmFF3 has to be 1.3mΩ−1. If gmID is 17, this means

IDFF3 is 78.4µA. Equation 5.9 is used and the result is that Imin,slewing equals 6µA. This

means the power consumption is determined by the GBWP requirement and is 0.19 mW.

For this op-amp, it is probably best not to use cascode, as it introduces a parasitic pole

at a high frequency. It was already concluded that a low gain at this point does not make

much difference.

5.3.10 Results

Table 5.6 shows the power consumption of the three op-amps together with the total con-

sumption. This consumption could be reduced to 1mW if R 12 is increased to 100kΩ. It is

clear that most of the power is dissipated in the first op-amp due to GBWP specifications.


If the system is simulated with ideal components the SNDR is 76.5 for a 10MHz input

signal with an amplitude of 0.4V. An ideal buffer was used with an output voltage between

0 and 1.2v. If the first and second op-amp are replaced with the designed op-amps the

SNDR is 74dB. This loss in performance could be due to increased delay or the small error

on the integrator coefficients caused by the finite GBWP. The cascode is not really nec-

essary. Even 60dB DC gain would probably be enough. For A 1MHz input the SNDR is

71dB. Now several harmonics lie in the pass band. The even harmonics are negligible, the

third harmonic is 77dB lower than the fundamental signal. The seventh harmonic is 80dB

lower than the fundamental. The other harmonics are at least 10dB lower. Figure 5.13

shows the output spectrum for this input.

Table 5.6: The power consumption of the three op-amps

op-amp Power(mW)

op-amp 1 0.9

op-amp 2 0.1

op-amp 3 0.2

Total 1.2

10−5

10−4

10−3

10−2

10−1

100

−150

−100

−50

0

f*Ts

FFT(dB)

Figure 5.13: The outputspectrum for a 1MHz input with 0.4V amplitude

Chapter 6

Conclusion

In this thesis I designed a low power ADC with a bandwidth of 20 MHz and a sample

frequency of 2 GHz. The design is similar to a third order sigma delta modulator, however

it was modified to implement pulse width modulation. This was achieved by making the

sigma delta loop oscillate at 666MHz and using a 1 bit quantizer. The result is that the

loop filter does not have to operate at the sample frequency. The fastest signal it has to

process is the oscillation. This reduces the power consumption of the system.

The power consumption can be reduced even further by adding a low pass filter in the

loop. This effectively reduces the slew rate requirements of the first op-amp. By adding

a compensation filter bypassing the first integrator, the influence of this low pass filter on

the loop filter was eliminated. This new technique reduces power consumption without

introducing the need to redesign the loop filter on the system level. While implementing

this loop filter it has been found that the cut off frequency of this low pass filter should

not be too close to the bandwidth. If the cut off frequency is too low, the output swing

of the first integrator is increased. One should make a careful trade off between output

swing and oscillation suppression. The system was designed first on the system level, and

later implemented on the circuit level.

To optimize the performance, I derived a linear model of the modulator. This model

proved to be accurate enough if the integrator coefficients did not become to large. If the

coefficients do become too large, the system starts to oscillate at a very low frequency,

which is not adequately predicted by the linear model. It is possible that the linear model

can be used for optimization purposes by demanding that the difference in magnitude of

the loop filter at the two highest frequencies were the loop filter becomes 180, remains

large enough. This corresponds to demanding that point two and three on the Nyquist

plot(Fig 3.4) remain at a certain distance from each other. However for this design, the

integrator coefficients were determined using a brute force approach.

On the circuit level, the integrators of the loop filter were implemented using feed

forward op-amps with three stages. The first and second op-amp were designed. The

53

Chapter 6. Conclusion 54

most critical element of the system is the first op-amp as it consumes most of the power.

The third op-amp is very similar to the other two and its power consumption can be

estimated by extrapolation. The total estimated power consumption of the three op-amps

is 1.2 mW. This power consumption is mainly caused by the gain bandwidth specifications,

not by the slewing.

An existing design was reused for the comparator and the flip flops. During simulation

it became clear that the flip flops were the limiting factor on the performance and that

they should be rescaled to offer more equal rise and fall times. A simulation of the system

with ideal flip flops showed a SNR of 74dB.

Bibliography

[1] J. De Maeyer (2005-2006). Efficiente architecturen voor A/D-convertoren in discrete

en continue tijd. Ph.D. thesis, Universiteit Gent.

[2] A. Gelb & W. E. Vander Velde (1968). Multiple-input Describing Functions And

Nonlinear System Design. McGraw-Hill Book Company.

[3] P. Rombouts (2011-2012). Geavanceerd analoog ontwerp. Course notes.

[4] R. Schreier & G. C. Temes (2005). Understanding Delta-Sigma Data Converters. John

Wiley & Sons.

[5] B. D. Vuyst & P. Rombouts (2011). A 5-mhz 11-bit self oscilating Σ∆ modulator with

a delay-based phase shifter in 0.025 mm2. IEEE Journal of Solid-State Circuits, 46(8).

[6] P. Woestyn, P. Rombouts, X. Xing & G. Gielen (2012). A selectable-bandwidth

3.5 mw, 0.03 mm2 self-oscillating sigma delta modulator with 71 db dynamic range

at 5 mhz and 65 db at 10 mhz bandwidth. ANALOG INTEGRATED CIRCUITS

AND SIGNAL PROCESSING, 72(1):55–63. URL http://dx.doi.org/10.1007/

s10470-012-9835-6.

55

http://dx.doi.org/10.1007/s10470-012-9835-6

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