usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM...

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A A B B C C D D E E 1 1 2 2 3 3 4 4 LA-1911 REV1.0 Schematic Springdale(865PE)+ICH5+nVIDIA NV34M(64MB VRAM) Desktop Prescott/Northwood uFCPGA-478 CPU 2003-08-06 SAPPORO 150 (DAL00) 0.2 Cover Page B 1 57 Friday, August 08, 2003 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of

Transcript of usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM...

Page 1: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

LA-1911 REV1.0 Schematic

Springdale(865PE)+ICH5+nVIDIA NV34M(64MB VRAM)Desktop Prescott/Northwood uFCPGA-478 CPU

2003-08-06

SAPPORO 150 (DAL00)

0.2

Cover Page

B

1 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

Page 2: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

PAGE 37

EmbeddedController

PAGE 47

SO-DIMM x 2(DDR)

FSB

PAGE 7,8,9,10,11

PAGE 4,5,6

PAGE 16,17,18,19

PAGE 23,24,25

FCBGA-932

ICS952623

Primary

LPC BUS 33MHz (3.3V)

BATTERY

NS PC87591L

PAGE15

Charger

PAGE 43

Intel Springdale

Power Interface &TEMP. sensing circuit

Thermal Sensor

HU

BInterface

ICH5

AGPMemory Bus BANK 0,1,2,3

PAGE 5,16

Clock Generator

LPC47N227

(uFCBGA/uFCPGA-478)

PAGE 46-54

DC/DC Interface

RTC Battery

PAGE 12,13,14

480MHz

DAL00 LA-1911 BLOCK DIAGRAM

mBGA-460

PAGE 34

Super I/O

AGP Bus

PAGE 5

CPU VIDPAGE 40

MCH 865PENVIDIA-NV34M

PAGE 22

CRT&LVDSConnector

Desktop Northwood

800MHz

266/333/400MHz(2.55V)

266MHz(1.8V)

FANController

PAGE 26RJ-45

PAGE 31

AC97 CODEC

PAGE 29Mini PCI

TSB43AB21APAGE 30

PAGE 35

PAGE 33IDE HDD

CD-ROM/DVD

USB 2.0 Port *3

33MHz (3.3V)PCI BUS

RTL8101LLAN

PAGE 26

MDCPAGE 36

A C-LINK

ParallelPAGE 37

BIOS(1M) Scan KB

PAGE 38

ALC 202

Connector

PAGE 36

REV B

RJ-11PAGE 26

PAGE 33

ADM1032

4 Pin-ConnectorTV-OUT

PAGE 22

Secondary

PAGE 32

Audio Amplifier

Desktop Prescott

& I/O PORTFIR(BTO)PAGE 35

PAGE 28Slot 0

PAGE 27,28T7L65XBCARDBAY

IEEE1394(BTO )

PAGE 28SD Conn

AGP 8X

TPA6011A4

BluetoothPAGE 36

DIRECT BOARD

VR/CIR BOARD

SW BOARD

PAGE 38

PAGE 38

PAGE 38

VRAM

PAGE 20,212 Channel and 4 sets

PAGE 39

LID/Kill Switch Power Buttom

PAGE 41

CIRCIRController

0.2

Block Digram

Custom

2 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

Page 3: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Voltage Rails

VIN

B+

+CPU_CORE

+CPU_VID

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

1.2V switched power rail for CPU AGTL Bus

External PCI DevicesDevice IDSEL# REQ#/GNT# Interrupts

CardBus

Mini-PCI

LAN

AD20

AD18

AD17

EC SM Bus1 addressDevice

ADM1032

S1 S3 S5

ON OFF

ON OFF

N/A N/A N/A

N/AN/AN/A

Power Plane Description

OFF

OFF

+5V

ON

OFF

+3V

OFF

OFF

5V power rail

ON

OFF

3.3V power rail

+RTCVCC

OFF

ON

+12VALW

ON

+5VALW ON

ON

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

+3VALW

12V always on power rail

ON

ON*

5V always on power rail

ON

OFF

3.3V always on power rail

ON

ON

ON

ON

ON

+2.5V

5V switched power rail

OFF

ON*

2.5V power rail

3.3V switched power rail

RTC power

OFF

ON

OFFON

EC SM Bus2 addressDevice

Smart Battery

2

1/4

PIRQA/PIRQB/PIRQC/PIRQD

PIRQG/PIRQH

VGA

ON

EEPROM(24C16/02)

1001 110X b0001 011X b

1010 000X b

AGP 4X/8X

ON OFF OFF

+1.5VS

+3VS

+5VS

3 PIRQF

PIRQA

(24C04) 1011 000Xb

ICH5 SM Bus addressDevice

Clock Generator( ICS 952623)

Address

Address Address

1101 001Xb

+1.25VS 1.25V switched power rail

+2.5VS 2.5V switched power rail

ON ON*

ON OFF OFF

1394 AD16 0 PIRQE

STATESIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON

ON

ON

ON

ON

ON ON

ON

ON

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

LOW

LOW LOW LOW LOW

LOWLOWLOW

LOW

LOW

LOW

HIGH HIGH HIGH HIGH

HIGHHIGHHIGH

HIGH

HIGH

HIGH

Board ID Table for AD channel

ON OFF OFF

DDR DIMM0 1010 000Xb

DDR DIMM2 1010 010Xb

Vcc 3.3V +/- 5%100K +/- 5%Ra

Board ID Rb V min0123

08.2K +/- 5%

0 V0.216 V 0.250 V 0.289 V0.436 V0.712 V

0.503 V0.819 V

0.538 V0.875 V

AD_BID V typAD_BID VAD_BID max

18K +/- 5%33K +/- 5%56K +/- 5%100K +/- 5%200K +/- 5%

3.300 V

0 V 0 V

4567 NC

1.036 V1.453 V 1.650 V 1.759 V1.935 V2.500 V

2.200 V3.300 V

2.341 V

1.185 V 1.264 V

Board ID01234567

PCB Revision0.1

+VTT_GMCH +1.225V (Prescott) / +1.45V (Northwood)

+VGA_CORE ON OFF OFF1.2V/1.5V switched power rail for VGA chip

SD AD22

ON

AD16

PIRQA/PIRQB/PIRQC/PIRQD

LA-1911 0.2

Notes

B

3 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

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5

5

4

4

3

3

2

2

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1

D D

C C

B B

A A

Compal Electronics, Inc.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Pin number NorthwoodPin name

PrescottPin name

Commend Commend

AA20 ITPCLKOUT0 Pull-up56ohmto +VCC_CORE

TESTHI6 Pull-up 62ohmto +VCC_CORE

AB22 ITPCLKOUT1 Pull-up 56ohmto +VCC_CORE

TESTHI7 Pull-up 62ohmto +VCC_CORE

AD2 NC VIDPWRGD Pull-up 8.2Kohmto +VCCVID

float

AD3 NC float VID5 Pull-up1Kohm to+3VRUN & connectto PWRIC

AF3 NC float VCCVIDLB Connect to +VCCVID

AD20 VCCA VCCIOPLLConnect to CPUFilter

Connect to CPUFilter

AF23 Connect to CPUFilter

Connect to CPUFilter

VCCIOPLL VCCA

AD1 VSS BOOTSELECTConnect to GND CPU determine

AE26 VSS Connect to GND OPTIMIZED/COMPAT#

float

B6 FERR# FERR#/PBE# Pull-up 62ohmto +VCC_CORE

Pull-up 62ohmto +VCC_CORE

Reference Intel documentDesktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0

Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5

Pop: NorthwoodDepop: Prescott

R_C

Northwood Prescott

Pop Pop

Pop Pop

Pop Pop

PopDepop

Depop

Depop

Pop

Pop

Pop Depop

Pop Depop

LA-19110.2

Prescott Processor in uFCPGA478 (1/2)C

4 57Friday, August 08, 2003

Title

Size Document Number R e v

Date: Sheet o f

CLK_BCLK#

H_A#3H_A#4H_A#5H_A#6H_A#7H_A#8H_A#9H_A#10H_A#11H_A#12H_A#13H_A#14H_A#15H_A#16H_A#17H_A#18H_A#19H_A#20H_A#21H_A#22H_A#23H_A#24H_A#25H_A#26H_A#27H_A#28

H_A#31

H_A#29H_A#30

H_D#0H_D#1H_D#2H_D#3H_D#4H_D#5H_D#6H_D#7H_D#8H_D#9H_D#10H_D#11H_D#12H_D#13H_D#14H_D#15H_D#16H_D#17H_D#18H_D#19H_D#20H_D#21H_D#22H_D#23H_D#24H_D#25H_D#26H_D#27H_D#28H_D#29H_D#30H_D#31H_D#32H_D#33H_D#34H_D#35H_D#36H_D#37H_D#38H_D#39H_D#40H_D#41H_D#42H_D#43H_D#44H_D#45H_D#46H_D#47H_D#48H_D#49H_D#50H_D#51H_D#52H_D#53H_D#54H_D#55H_D#56H_D#57H_D#58H_D#59H_D#60H_D#61H_D#62H_D#63

H_IERR#

H_REQ#0H_REQ#1H_REQ#2H_REQ#3H_REQ#4

CLK_BCLK

BOOTSEL

+CPU_CORE

+CPU_CORE

+CPU_CORE+CPU_CORE

Prescott

JCPU1A

AMP_3-1565030-1_Prescott

K2K4L6K1L3M6L2M3M4N1M1N2N4N5T1R2P3P4R3T2U1P6U3T4V2R6W1T5U4V3

W2Y1

AB1

J1K5J4J3H3G1

AC1V5

AA3AC3

G2D2H6

G4

E2E3F3

B21B22A23A25C21D22B24C23C24B25G22H21C26D23J21D25H22E24G23F23F24E25F26D26L21G26H24M21L22J24K23H25M23N22P21M24N23M26N26N25R21P24R25R24T26T25T22T23U26U24U23V25U21V22V24W26Y26W25Y23Y24Y21AA25AA22AA24

A10

A12

A14

A16

A18

A20

A8 AA

10A

A12

AA

14A

A16

AA

18AA

8A

B11

AB

13A

B15

AB

17A

B19

AB7

AB9

AC

10A

C12

AC

14A

C16

AC

18AC

8A

D11

AD

13A

D15

AD

17A

D19

AD7

AD9

AE

10A

E12

AE

14A

E16

AE

18A

E20

AE6

AE8

AF

11A

F13

AF

15A

F17

AF

19A

F2A

F21

AF5

AF7

AF9

B11

B13

B15

B17

B19

B7 B9 C10

C12

C14

C16

C18

C20

C8 D11

D13

D15

D17

D19

D7 D9E

12E

14E

16E

18E

20E8F

11

H1 H4 H23

H26

A11

A13

A15

A17

A19

A21

A24

A26

A3 A9 AA1

AA

11A

A13

AA

15A

A17

AA

19A

A23

AA

26AA

4AA

7AA

9A

B10

AB

12A

B14

AB

16A

B18

AB

20A

B21

AB

24AB

3AB

6AB

8A

C11

AC

13A

C15

AC

17A

C19

AC2

AC

22A

C25

AC5

AC7

AC9

AD1

AD

10A

D12

AD

14A

D16

AD

18A

D21

AD

23AD

4AD

8

AF22AF23

F13

F15

F17

F19

F9

E10

A#3A#4A#5A#6A#7A#8A#9A#10A#11A#12A#13A#14A#15A#16A#17A#18A#19A#20A#21A#22A#23A#24A#25A#26A#27A#28A#29A#30A#31A#32A#33A#34A#35

REQ#0REQ#1REQ#2REQ#3REQ#4ADS#

AP#0AP#1BINIT#IERR#

BNR#BPRI#BR0#

LOCK#

DEFER#HITM#HIT#

D#0D#1D#2D#3D#4D#5D#6D#7D#8D#9

D#10D#11D#12D#13D#14D#15D#16D#17D#18D#19D#20D#21D#22D#23D#24D#25D#26D#27D#28D#29D#30D#31D#32D#33D#34D#35D#36D#37D#38D#39D#40D#41D#42D#43D#44D#45D#46D#47D#48D#49D#50D#51D#52D#53D#54D#55D#56D#57D#58D#59D#60D#61D#62D#63

VC

C_0

VC

C_1

VC

C_2

VC

C_3

VC

C_4

VC

C_5

VC

C_6

VC

C_7

VC

C_8

VC

C_9

VC

C_1

0V

CC

_11

VC

C_1

2V

CC

_13

VC

C_1

4V

CC

_15

VC

C_1

6V

CC

_17

VC

C_1

8V

CC

_19

VC

C_2

0V

CC

_21

VC

C_2

2V

CC

_23

VC

C_2

4V

CC

_25

VC

C_2

6V

CC

_27

VC

C_2

8V

CC

_29

VC

C_3

0V

CC

_31

VC

C_3

2V

CC

_33

VC

C_3

4V

CC

_35

VC

C_3

6V

CC

_37

VC

C_3

8V

CC

_39

VC

C_4

0V

CC

_41

VC

C_4

2V

CC

_43

VC

C_4

4V

CC

_45

VC

C_4

6V

CC

_47

VC

C_4

8V

CC

_49

VC

C_5

0V

CC

_51

VC

C_5

2V

CC

_53

VC

C_5

4V

CC

_55

VC

C_5

6V

CC

_57

VC

C_5

8V

CC

_59

VC

C_6

1V

CC

_62

VC

C_6

3V

CC

_64

VC

C_6

5V

CC

_66

VC

C_6

7V

CC

_68

VC

C_6

9V

CC

_70

VC

C_7

1V

CC

_72

VC

C_7

4V

CC

_75

VC

C_7

6V

CC

_77

VC

C_7

8V

CC

_79

VC

C_8

0

VS

S_0

VS

S_1

VS

S_2

VS

S_3

VS

S_4

VS

S_5

VS

S_6

VS

S_7

VS

S_8

VS

S_9

VS

S_1

0V

SS

_11

VS

S_1

2V

SS

_13

VS

S_1

4V

SS

_15

VS

S_1

6V

SS

_17

VS

S_1

8V

SS

_19

VS

S_2

0V

SS

_21

VS

S_2

2V

SS

_23

VS

S_2

4V

SS

_25

VS

S_2

6V

SS

_27

VS

S_2

8V

SS

_29

VS

S_3

0V

SS

_31

VS

S_3

2V

SS

_33

VS

S_3

4V

SS

_35

VS

S_3

6V

SS

_37

VS

S_3

8V

SS

_39

VS

S_4

0V

SS

_41

VS

S_4

2V

SS

_43

VS

S_4

4V

SS

_45

VS

S_4

6

BO

OTS

ELE

CT

VS

S_4

7V

SS

_48

VS

S_4

9V

SS

_50

VS

S_5

1V

SS

_52

VS

S_5

3V

SS

_54

VS

S_5

5

BCLK0BCLK1

VC

C_8

1V

CC

_82

VC

C_8

3V

CC

_84

VC

C_8

5

VC

C_7

3

R25 62_0402_5% 1 2

R35 200_0402_5%1 2

R120_0402_5%

1 2R150_0402_5%

1 2

H_A#[3..31]7

H_REQ#[0..4]7

H_ADS#7

H_HIT#7H_HITM#7H_DEFER#7

H_D#[0..63] 7

H_BR0#7

H_LOCK#7

H_BPRI#7H_BNR#7

H_BOOTSELECT52

CLK_BCLK15CLK_BCLK#15

Page 5: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Compal Electronics, Inc.

Place near ICH

Place near CPU

Close to the CPU

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1. +CPU_GTLREF Trace wide12mils(min),Space 15mils

3. Place decoupling cap 220PF near CPU.2. Place R_A and R_B near CPU.

Layout note :

R_A

R_B

+3V POWER

R_G

Pop: NorthwoodDepop: Prescott

Pop: PrescottDepop: Northwood

Trace >= 25mils

Trace >= 25mils

R_E

REPop: PrescottDepop: Northwood

1.Place cap within 600 mils ofthe VCCA and VSSA pins.

Note: Please change to 10uH, DC currentof 100mA parts and close to cap

PLL Layout note :

2.H_VCCIOPLL,HVCCA,HVSSA trace wide12 mils(min)

Asynch GTL+ PULL HIGH

JTAG PULL DOWN

VID PULL HIGH VID PWRGD Circuit Thermal SensorGTL Reference Voltage

**

**

LA-1911 0.2

Prescott Processor in uFCPGA478 (2/2)C

5 57Friday, August 08, 2003

Title

Size Document Number R e v

Date: Sheet o f

H_FERR#

H_RESET#

H_PROCHOT#

H_PWRGOOD

H_VID0

H_VID3

H_VID4

H_VID5

H_VID2H_VID1

H_THERMDA

H_THERMDC

ITP_TMSITP_TRST#ITP_TCKITP_TDI

H_VID_PWRGD

H_VCCA

H_RESET#

H_VID0H_VID1

H_PWRGOOD

H_VID2H_VID3

COMP0

H_TESTHI1

COMP1

H_VID4H_VID5

H_TESTHI2_7

H_THERMDCH_THERMDA

VCCVIDLB

H_TESTHI8H_TESTHI9

H_VID_PWRGD

H_TESTHI10H_TESTHI11H_TESTHI12

H_FERR#

H_RS#0H_RS#1H_RS#2

CLK_ITPCLK_ITP#

H_TESTHI0

ITP_BPM#0ITP_BPM#1ITP_BPM#2ITP_BPM#3ITP_BPM#4

H_PROCHOT#

ITP_BPM#5

ITP_TCKITP_TDI

ITP_TMS

H_VSSA

ITP_TRST#

+CPU_CORE

+3VS

+3VS+3V

+CPU_CORE

+CPU_GTLREF

+CPU_GMCH_GTLREF

+CPU_CORE

+CPU_CORE

+CPU_GTLREF

+CPU_CORE

+CPUVID

+CPUVID

+CPUVID

+CPU_CORE

R60

169_0603_1%

12

R27 130_0402_5%1 2

R518 62_0402_5%1 2

C780

0.1U_0402_16V4Z

1

2

R33 62_0402_5%1 2

R64 62_0402_5%1 2

R78 62_0402_5%1 2

U 4 A

SN74LVC125APWLE_TSSOP14

23

1 147

IO OE#

PG

+

C80

33U_D2_8M_R35

1 2

R30 62_0402_5%1 2

R26 @0_0402_5%1 2

R84

0_0402_5%

1 2

R32 62_0402_5%1 2

L5 LQG21F4R7N00_08051 2

R74 300_0402_5%1 2

R17 1K_0402_5%1 2

R37 62_0402_5%1 2

R59

200_0603_1%

12

C78220P_0402_50V8K

1

2

R83 0_0402_5% 1 2

R18 1K_0402_5%1 2

R79 62_0402_5%1 2

R8262_0402_5%

1 2

RP3

1K_8P4R_1206_5%

18273645

R6561.9_0603_1%

12

L6 LQG21F4R7N00_08051 2

R28 62_0402_5%1 2

R20 62_0402_5%1 2

R38 62_0402_5%1 2

C48

0.1U_0402_16V4Z

1

2

[email protected]_0603_1%

1 2

R29 62_0402_5%1 2

R36 62_0402_5%1 2

C68

0.1U_0402_10V6K 1

2

R7010K_0402_5%

12

R1461.9_0603_1%

12

C390.1U_0402_10V6K

1

2

R630_0603_5%

12

R41@10K_0402_5%

12

RP4

1K_8P4R_1206_5%

1 82 73 64 5

R66 0_0402_5%1 2

R75 62_0402_5%1 2

C47

2200P_0402_50V7K

1

2

R19 62_0402_5%1 2

U3

ADM1032ARM_RM8

1

6

4

5

2

3

8

7

VDD1

ALERT#

THERM#

G N D

D+

D-

SCLK

SDATA

R34 62_0402_5%1 2

Prescott

JCPU1B

AMP_3-1565030-1_Prescott

F1G5F4

AB2J6

C6B6B2B5

AB23Y4

AD25

D1E5

W5AB25

H2H5

C4B3

C1D4

D5F7E6

P1L24

J26K25K26L25

AE

11A

E13

AE

15A

E17

AE

19A

E22

AE

24

AE26

AE7

AE9

AF1

AF

10A

F12

AF

14A

F16

AF

18A

F20

AF

26

AF6

AF8

B10

B12

B14

B16

B18

B20

B23

B26

B4 B8 C11

C13

C15

C17

C19

C2 C22

C25

C5 C7 C9 D10

D12

D14

D16

D18

D20

D21

D24

D3 D6 D8 E1 E11

E13

E15

E17

E19

E23

E26

E4 E7 E9 F10

F12

F14

F16

F18

F2

F22

F25

F5

AE5

AE4

AE3

AE2

AE1

AA21AA6F20F6

A22A7

AD24AA2AC21AC20AC24AC23AA20AB22U6W4Y3A6

F8

G21

G24

G3

G6

J2 J22

J25

J5 K21

K24

K3 K6 L1 L23

L26

L4 M2

M22

M25

M5

N21

N24

N3 N6 P2 P22

P25

P5 R1 R23

R26

R4 T21

T24

T3

T6

U2 U22

U25

U5 V1 V23

V26

V4 W21

W24

W3

W6

Y2 Y22

Y25

Y5

AD6AD5

AC6AB5AC4

Y6AA5AB4

E22K22R22W22

F21J23P23W23

AC26AD26

L5R5

E21G25P26V21

AE25

AD20

A5

AE23

AF4

A2

C3V6AB26

AD22

A4

AD2

AD3

AE21AF24AF25

AF3

RS#0RS#1RS#2RSP#TRDY#

A20M#FERR#IGNNE#SMI#PWRGOODSTPCLK#

TESTHI12

LINT0LINT1INIT#RESET#

DRDY#DBSY#

THERMDCTHERMDA

TDIT C K

TDOTMSTRST#

COMP1COMP0

DP#0DP#1DP#2DP#3

VS

S_5

7V

SS

_58

VS

S_5

9V

SS

_60

VS

S_6

1V

SS

_62

VS

S_6

3

OPTIMIZED/COMPAT#

VS

S_6

5V

SS

_66

VS

S_6

7V

SS

_68

VS

S_6

9V

SS

_70

VS

S_7

1V

SS

_72

VS

S_7

3

SKTO

CC

#

VS

S_7

5V

SS

_76

VS

S_7

7V

SS

_78

VS

S_7

9V

SS

_80

VS

S_8

1V

SS

_82

VS

S_8

3V

SS

_84

VS

S_8

5V

SS

_86

VS

S_8

7V

SS

_88

VS

S_8

9V

SS

_90

VS

S_9

1V

SS

_92

VS

S_9

3V

SS

_94

VS

S_9

5V

SS

_96

VS

S_9

7V

SS

_98

VS

S_9

9V

SS

_100

VS

S_1

01V

SS

_102

VS

S_1

03V

SS

_104

VS

S_1

05V

SS

_106

VS

S_1

07V

SS

_108

VS

S_1

09V

SS

_110

VS

S_1

11V

SS

_112

VS

S_1

13V

SS

_114

VS

S_1

15V

SS

_116

VS

S_1

17V

SS

_118

VS

S_1

19V

SS

_120

VS

S_1

21V

SS

_122

VS

S_1

23V

SS

_124

VS

S_1

25V

SS

_126

VS

S_1

27V

SS

_128

VID0

VID1

VID2

VID3

VID4

GTLREF0GTLREF1GTLREF2GTLREF3

N C 1N C 2

TESTHI0TESTHI1TESTHI2TESTHI3TESTHI4TESTHI5TESTHI6TESTHI7TESTHI8TESTHI9

TESTHI10TESTHI11

VS

S_1

29V

SS

_130

VS

S_1

31V

SS

_132

VS

S_1

33V

SS

_134

VS

S_1

35V

SS

_136

VS

S_1

37V

SS

_138

VS

S_1

39V

SS

_140

VS

S_1

41V

SS

_142

VS

S_1

43V

SS

_144

VS

S_1

45V

SS

_146

VS

S_1

47V

SS

_148

VS

S_1

49V

SS

_150

VS

S_1

51V

SS

_152

VS

S_1

53V

SS

_154

VS

S_1

55V

SS

_156

VS

S_1

57V

SS

_158

VS

S_1

59V

SS

_160

VS

S_1

61V

SS

_162

VS

S_1

63V

SS

_164

VS

S_1

65V

SS

_166

VS

S_1

67V

SS

_168

VS

S_1

69V

SS

_170

VS

S_1

71V

SS

_172

VS

S_1

73V

SS

_174

VS

S_1

75V

SS

_176

VS

S_1

77V

SS

_178

VS

S_1

79V

SS

_180

VS

S_1

81

BSEL0BSEL1

BPM#0BPM#1BPM#2BPM#3BPM#4BPM#5

DSTBN#0DSTBN#1DSTBN#2DSTBN#3

DSTBP#0DSTBP#1DSTBP#2DSTBP#3

ITP_CLK0ITP_CLK1

ADSTB#0ADSTB#1

DBI#0DBI#1DBI#2DBI#3

DBR#

VCCIOPLL

VCCSENSE

VCCA

VCC

VID

THERMTRIP#

PROCHOT#MCERR#

SLP#VSSA

VSSSENSE

VID

PW

RG

D

VID5

N C 5N C 4N C 3

VCCVIDLB

EC_SMB_DA237

VID_PWRGD 52

EC_SMB_CK237

CPU_CLKSEL015CPU_CLKSEL115

H_SMI#23

H_INTR23H_NMI23H_INIT#23

H_PROCHOT# 7,51

H_DSTBN#0 7H_DSTBN#1 7H_DSTBN#2 7H_DSTBN#3 7

H_DSTBP#0 7H_DSTBP#1 7H_DSTBP#2 7H_DSTBP#3 7

H_STPCLK#23

H_THERMTRIP#24

H_PWRGOOD23

H_FERR#23

VCCSENSE52VSSSENSE52

H_DRDY#7H_DBSY#7

H_VID552H_VID452H_VID352H_VID252H_VID152H_VID052

CLK_ITP15CLK_ITP#15

H_CPUSLP# 23

H_RS#[0..2]7

H_RESET#7

H_ADSTB#0 7H_ADSTB#1 7

H_IGNNE#23

H_DINV#0 7H_DINV#1 7H_DINV#2 7H_DINV#3 7

H_A20M#23

H_TRDY#7

VCORE_ENLL 49,52

Page 6: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Place 11 North of Socket(Stuff 8)

Place 12 Inside Socket(Stuff all)

Place 9 South of Socket(Unstuff all)

Compal Electronics, Inc.

Decoupling Reference Requirement:560uF Polymer, ESR:5m ohm(each) * 1022uF X5R * 32

Decoupling Reference Document:Springdale Chipset Platform Design guide Rev1.11(12474)page239

22uF depop reference Springdale Customer Schematic R1.2 page82

470uF _ERS10m ohm* 15, ESR=0.5m ohm

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

**

**

LA-1911 0.2

CPU DecouplingC

6 57Friday, August 08, 2003

Title

Size Document Number R e v

Date: Sheet o f

+CPU_CORE

+CPU_CORE

+CPU_CORE

+CPU_CORE

+CPU_CORE

+CPU_CORE

+CPU_CORE

+ C119470U_D4_2.5VM

1

2

C1422U_1206_6.3V6M

1

2

C1322U_1206_6.3V6M

1

2

+ C33470U_D4_2.5VM

1

2

+ C8470U_D4_2.5VM

1

2

+ C85470U_D4_2.5VM

1

2

C56022U_1206_6.3V6M

1

2

C51422U_1206_6.3V6M

1

2

C1622U_1206_6.3V6M

1

2

C40822U_1206_6.3V6M

1

2

+ C28@470U_D4_2.5VM

1

2

C42122U_1206_6.3V6M

1

2

C53622U_1206_6.3V6M

1

2

+ C29470U_D4_2.5VM

1

2

C44022U_1206_6.3V6M

1

2

C55822U_1206_6.3V6M

1

2

+ C75@470U_D4_2.5VM

1

2

C45522U_1206_6.3V6M

1

2

C49122U_1206_6.3V6M

1

2

C57122U_1206_6.3V6M

1

2

C50822U_1206_6.3V6M

1

2

C52322U_1206_6.3V6M

1

2

C51822U_1206_6.3V6M

1

2

C46822U_1206_6.3V6M

1

2

C53522U_1206_6.3V6M

1

2

C54522U_1206_6.3V6M

1

2

+ C67470U_D4_2.5VM

1

2

+ C44470U_D4_2.5VM

1

2

C1222U_1206_6.3V6M

1

2

+ C61470U_D4_2.5VM

1

2

C1922U_1206_6.3V6M

1

2

C55722U_1206_6.3V6M

1

2

+ C53470U_D4_2.5VM

1

2

C1822U_1206_6.3V6M

1

2

C57022U_1206_6.3V6M

1

2

C6022U_1206_6.3V6M

1

2

C1722U_1206_6.3V6M

1

2

C5222U_1206_6.3V6M

1

2

C5922U_1206_6.3V6M

1

2

+ C51470U_D4_2.5VM

1

2

C7022U_1206_6.3V6M

1

2

C1522U_1206_6.3V6M

1

2

+ C63470U_D4_2.5VM

1

2

+ C95470U_D4_2.5VM

1

2

Page 7: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Trace width 10mils,Space7mils

2. Place decoupling cap 220PF near GMCH.

Layout note :GTL Reference Voltage

1. +GMCH_GTLREF Trace wide12mils(min),Space 15mils.

LA-1911 0.2

Springdale-Host/GND (1/4)B

7 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

H_REQ#0

H_REQ#2H_REQ#1

H_D#11

H_D#23

H_D#46

H_D#21

H_D#2

H_D#50

H_D#31

H_D#37

H_D#58

H_D#35

H_D#39

H_D#27

H_D#5

H_D#52

H_D#30

H_D#8

H_D#10

H_D#51

H_D#44

H_D#60

H_D#18

H_D#4

H_D#43

H_D#56

H_D#59

H_D#14

H_D#63

H_D#28

H_D#48

H_D#3

H_D#62

H_D#34

H_D#36

H_D#24

H_D#13

H_D#55

H_D#57

H_D#22

H_D#20

H_D#16

H_D#29

H_D#9

H_D#1H_D#0

H_D#53

H_D#17

H_D#26

H_D#45

H_D#33

H_D#40

H_D#7

H_D#47

H_D#41

H_D#25

H_D#38

H_D#15

H_D#54

H_D#61

H_D#49

H_D#42

H_D#6

H_D#32

H_D#12

H_D#19

H_A#26

H_A#19

H_A#11

H_A#25

H_A#22

H_A#18

H_A#7

H_A#20

H_A#14

H_A#21

H_A#27

H_A#23

H_A#12

H_A#30H_A#29

H_A#16

H_A#4

H_A#6

H_A#10H_A#9

H_A#28

H_A#5

H_A#31

H_A#15

H_A#24

H_A#3

H_A#17

H_A#8

H_A#13

H_PROCHOT#

HD_SWINGHDRCOMP

H_REQ#4H_REQ#3

HD_SWING

HDRCOMP

H_RS#2

H_RS#0H_RS#1

+VTT_GMCH

+CPU_GMCH_GTLREF

+VTT_GMC H

+GMCH_GTLREF

+GMCH_GTLREF

R511

200_0603_1%

12

R522 0_0603_5%

1 2

R535102_0603_1%

12

FSB

U43A

SPRINGDALE_UFCBGA932

D26D30L23E29B32K23C30C31J25B31E30B33J24F25D34C32F28C34J27G27F29E28H27K24E32F31G30J26G26

B29J23L22C29J21B30D28

B7C7

B19C19C17L19K19L17G9F9

L14D12E12C15

F27D24G24L21E23K21E25B24B28B26E27G22C27B27

E8AE14

E24C25F23

B23E22B21D20B22D22B20C21E18E20B16D16B18B17E16D18G20F17E19F19J17L18G16G18F21F15E15E21J19G14E17K17J15L16J13F13F11E13K15G12G10L15E11K13J11H10G8E9B13E14B14B12B15D14C13B11D10C11E10B10C9B9D8B8

L20

L13L12

HA3#HA4#HA5#HA6#HA7#HA8#HA9#HA10#HA11#HA12#HA13#HA14#HA15#HA16#HA17#HA18#HA19#HA20#HA21#HA22#HA23#HA24#HA25#HA26#HA27#HA28#HA29#HA30#HA31#

HREQ0#HREQ1#HREQ2#HREQ3#HREQ4#HADSTB0#HADSTB1#

HCLKPHCLKN

HDSTBP0#HDSTBN0#DINV0#HDSTBP1#HDSTBN1#DINV1#HDSTBP2#HDSTBN2#DINV2#HDSTBP3#HDSTBN3#DINV3#

ADS#HTRDY#DRDY#DEFER#HITM#HIT#HLOCK#BREQ0#BNR#BPRI#DBSY#RS0#RS1#RS2#CPURST#PWROK#

HDRCOMPHDSWINGHDVREF

HD0#HD1#HD2#HD3#HD4#HD5#HD6#HD7#HD8#HD9#

HD10#HD11#HD12#HD13#HD14#HD15#HD16#HD17#HD18#HD19#HD20#HD21#HD22#HD23#HD24#HD25#HD26#HD27#HD28#HD29#HD30#HD31#HD32#HD33#HD34#HD35#HD36#HD37#HD38#HD39#HD40#HD41#HD42#HD43#HD44#HD45#HD46#HD47#HD48#HD49#HD50#HD51#HD52#HD53#HD54#HD55#HD56#HD57#HD58#HD59#HD60#HD61#HD62#HD63#

PROCHOT#

BSEL0BSEL1

GND

U43G

SPRINGDALE_UFCBGA932

L31L26L25L24K33K29K27K25K22K20K18K16K14K12K11J35J32J28J22J20J18J16J14J12J10H33H30H26H24H22H20H18H16H14H12

H9H8H5H2

G35G31G28F26F24F22F20F18

F16F14F12F10F8F5F3F1E3E1D35D33D31D29D27D25D23D21D19D17D15D13D11D9D1C28C26C24C22C20C18C16C14C12C10C8C4A32A29A27A25A23A20A16A13A11A9A7

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

R531301_0603_1%

12

C286220P_0402_50V8K

1

2

C301

0.01U_0402_16V7K

1

2

R52524.9_0603_1%

12

GND

U43F

SPRINGDALE_UFCBGA932

AR32AR29AR27AR25AR23AR20AR16AR13AR11

AR9AN32AN30AN28AN26AN24AN22AN20AN18AN16AN14AN12AN10AM35AM29AM27AM25AM23AM21AM19AM17AM15AM13AM11

AM9AL32

AL1AK28AK26AK24AK22AK20AK18AK16AK14AK12AK10

AK8AK3

AJ35AJ32

AJ9AJ4AJ1

AH33AH30AH24AH22AH20AH18AH16AH14AH12AH10

AH6AH3

AG35AG32AG28AG26AG24AG22AG20AG18AG16AG14

AG8AG4

AF33AF30AF25AF24AF22AF20AF18AF16AF14AF11

AF9AF6AF3

AE35AE32AE26AE25AE13AE12

AE11AE10AE4AE1AD33AD30AD28AD10AD9AD8AD6AD3AC35AC32AC4AC1AB33AB30AB28AB27AB26AB10AB9AB8AB6AB3AA32AA4AA1Y35Y33Y30Y28Y27Y26Y10Y9Y8Y6Y3W32W18W17W4V33V30V28V27V26V19V17V10V9V8V6V3U32U19U18U4T35T33T30T28T27T26T10T 9T 8T 6T 3T 1R32R4R1P33P30P28P27P26P9P8P6P3N35N32N4N1M33M30M28M27M26M6M3L35

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

H_A#[3..31]4

H_REQ#[0..4]4

H_ADS#4

CLK_HCLK15CLK_HCLK#15

H_D#[0..63] 4

H_RS#[0..2]5

H_DRDY#5

H_DBSY#5

H_DINV#35

H_DINV#15

H_DINV#25

H_DINV#05

H_DSTBP#05H_DSTBN#05

H_DSTBP#15H_DSTBN#15

H_DSTBP#25H_DSTBN#25

H_DSTBP#35H_DSTBN#35

H_ADSTB#05H_ADSTB#15

H_RESET#5 MCH_CLKSEL0 15MCH_CLKSEL1 15

H_PROCHOT# 5,51

H_TRDY#5

SYS_PWROK24,27,40

H_BR0#4

H_BPRI#4

H_HIT#4H_LOCK#4

H_HITM#4H_DEFER#4

H_BNR#4

Page 8: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Compal Electronics, Inc.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Trace width of 12mils and space10mils(min)

Trace width of 12mils and space10mils(min)

Trace width of 12mils and space10mils(min)

Close to GMCH <1"

Close to GMCH <1"

Close to GMCH(E34)

+SM_VREF_A trace width of 12mils and space12mils(min) *

*

*

Follow Intel design guideR1.11(12474) page124,125

Place resistors within1.0 inch of GMCH (AK9)

Close to Pin AN9

Close to Pin AL9

R391 Change to 31.12K is real

R153 Change to 31.12K is real

DDR Resistive Compensation

DDR RCOMP VOH Circuitry

DDR RCOMP VOL Circuitry*

LA-1911 0.2

Springdale-DDR Interface-A(2/5)B

8 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

DDRA_SMA[0..12]

DDRA_SDQ[0..63]

SMXRCOMPVOL

DDRA_SDQ61

DDRA_SDQ27

DDRA_SDQ20

DDRA_SDQ12

DDRA_SDQ9

DDRA_SDQ5

DDRA_SMA12

DDRA_SMA8

DDRA_SDQ45

DDRA_SDQ42

DDRA_SDQ23

DDRA_SDQ6

DDRA_SDQ35

DDRA_SDQ17

DDRA_SDQ14

SMXRCOMPVOH

DDRA_SDQ51

DDRA_SDQ43

DDRA_SDQ39

DDRA_SDQ34

DDRA_SDQ3

SMXRCOMPVOL

DDRA_SDQ58

DDRA_SDQ22

DDRA_SDQ10

DDRA_CKE1

DDRA_SDQ54

DDRA_SDQ47

DDRA_SDQ60

DDRA_SDQ44

DDRA_SDQ8

DDRA_SDQ2

DDRA_SDQ57DDRA_SDQ56

DDRA_SDQ52

DDRA_SDQ30

SMXRCOMPVOH

DDRA_SDQ59

DDRA_SDQ37

DDRA_SDQ1

DDRA_SDQ26DDRA_SDQ25

DDRA_SDQ16

DDRA_SDQ13

DDRA_SMA6

DDRA_SMA1DDRA_SMA0

DDRA_SDQ15

DDRA_SMA2

SMXRCOMP

DDRA_SDQ21DDRA_CKE0

DDRA_SDQ46

DDRA_SDQ33

DDRA_SMA5

DDRA_SDQ50DDRA_SDQ49

DDRA_SDQ41

DDRA_SDQ62

DDRA_SDQ29

DDRA_SDQ19

DDRA_SMA3

DDRA_SDQ63

DDRA_SDQ55

DDRA_SDQ53

DDRA_SMA7

DDRA_SDQ48

DDRA_SDQ40

DDRA_SMA4

SMXRCOMP

DDRA_SDQ11

DDRA_SCS#1 DDRA_SDQ18

DDRA_SMA11

DDRA_SCS#0

DDRA_SDQ4

DDRA_SDQ38

DDRA_SMA9DDRA_SMA10

DDRA_SDQ36

DDRA_SDQ31

DDRA_SDQ28

DDRA_SDQ0

DDRA_SDQ32

DDRA_SDQ7

DDRA_SDQ24

+2.5V

+2.5V

+SM_VREF_A

+2.5V

R9442.2_0603_1%

12

R43630.9K_0603_1%

12

C5951U_0603_10V6K

1

2

C110

2.2U_0805_16V4Z 1

2

C1670.01U_0402_16V7K

1

2

C1520.01U_0402_16V7K

1

2

C92

2.2U_0805_16V4Z 1

2

R43410K_0603_1%

12

R9842.2_0603_1%

12

C7770.01U_0402_16V7K

1

2

C730

2.2U_0805_16V4Z 1

2DDR Channel A

U43B

SPRINGDALE_UFCBGA932

AJ34AL33AK29AN31AL30AL26AL28AN25AP26AP24AJ33AN23AN21

AL34AM34AP32AP31AM26

AB34Y34

AC33

AE33AH34

AA34Y31Y32

W34

AL20AN19AM20AP20

AK32AK31AP17AN17

N33N34

AK33AK34AM16AL16

P31P32

E34

AK9

AN9

AL9

AN11AP12AP10AP11AM12AN13AM10AL10AL12AP13

AP15AP16

AP14AM14AL18AP19AL14AN15AP18AM18

AP23AM24

AP22AM22AL24AN27AP21AL22AP25AP27

AM30AP30

AP28AP29AP33AM33AM28AN29AM31AN34

AF34AF31

AH32AG34AF32AD32AH31AG33AE34AD34

V34W33

AC34AB31V32V31AD31AB32U34U33

M32M34

T34T32K34K32T31P34L34L33

H31H32

J33H34E33F33K31J34G34F34

SMAA_A0SMAA_A1SMAA_A2SMAA_A3SMAA_A4SMAA_A5SMAA_A6SMAA_A7SMAA_A8SMAA_A9SMAA_A10SMAA_A11SMAA_A12

SMAB_A1SMAB_A2SMAB_A3SMAB_A4SMAB_A5

SWE_A#SCAS_A#SRAS_A#

SBA_A0SBA_A1

SCS_A0#SCS_A1#SCS_A2#SCS_A3#

SCKE_A0SCKE_A1SCKE_A2SCKE_A3

SCMDCLK_A0SCMDCLK_A0#SCMDCLK_A1SCMDCLK_A1#SCMDCLK_A2SCMDCLK_A2#SCMDCLK_A3SCMDCLK_A3#SCMDCLK_A4SCMDCLK_A4#SCMDCLK_A5SCMDCLK_A5#

SMVREF_A

SMXRCOMP

SMXRCOMPVOH

SMXRCOMPVOL

SDQS_A0SDM_A0SDQ_A0SDQ_A1SDQ_A2SDQ_A3SDQ_A4SDQ_A5SDQ_A6SDQ_A7

SDQS_A1SDM_A1

SDQ_A8SDQ_A9

SDQ_A10SDQ_A11SDQ_A12SDQ_A13SDQ_A14SDQ_A15

SDQS_A2SDM_A2

SDQ_A16SDQ_A17SDQ_A18SDQ_A19SDQ_A20SDQ_A21SDQ_A22SDQ_A23

SDQS_A3SDM_A3

SDQ_A24SDQ_A25SDQ_A26SDQ_A27SDQ_A28SDQ_A29SDQ_A30SDQ_A31

SDQS_A4SDM_A4

SDQ_A32SDQ_A33SDQ_A34SDQ_A35SDQ_A36SDQ_A37SDQ_A38SDQ_A39

SDQS_A5SDM_A5

SDQ_A40SDQ_A41SDQ_A42SDQ_A43SDQ_A44SDQ_A45SDQ_A46SDQ_A47

SDQS_A6SDM_A6

SDQ_A48SDQ_A49SDQ_A50SDQ_A51SDQ_A52SDQ_A53SDQ_A54SDQ_A55

SDQS_A7SDM_A7

SDQ_A56SDQ_A57SDQ_A58SDQ_A59SDQ_A60SDQ_A61SDQ_A62SDQ_A63

C1461U_0603_10V6K

1

2

C590

2.2U_0805_16V4Z 1

2

R10630.9K_0603_1%

12

R11010K_0603_1%

12

C731

0.1U_0402_16V4Z 1

2

DDRA_SDQ[0..63] 12,14

DDRA_SMA[0..12]12,14

DDRA_SBS012,14DDRA_SBS112,14

DDRA_CLK212DDRA_CLK2#12

DDRA_SWE#12,14DDRA_SCAS#12,14DDRA_SRAS#12,14

DDRA_CKE012,14

DDRA_SDQS6 12,14

DDRA_SDQS3 12,14

DDRA_SDM2 12,14

DDRA_SDM5 12,14

DDRA_CLK1#12

DDRA_SDQS5 12,14

DDRA_SDQS2 12,14

DDRA_SCS#112,14

DDRA_SDM1 12,14

DDRA_SDM4 12,14

DDRA_CLK112

DDRA_SDQS1 12,14

DDRA_SCS#012,14

DDRA_SDM0 12,14

DDRA_SDM7 12,14

DDRA_SDQS0 12,14

DDRA_SDQS7 12,14

DDRA_SDQS4 12,14

DDRA_CKE112,14

DDRA_SDM6 12,14

DDRA_SDM3 12,14

Page 9: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Compal Electronics, Inc.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Trace width of 12milsand space 10mils(min)

Trace width of 12mils and space10mils(min)

Close to GMCH <1"

Close to GMCH <1"

Close to GMCH(AP9)

+SM_VREF_B trace width of12mils and space12mils(min)

SM_VREF_B and SM_VREF_Aare connected inside GMCH.

Place resistors within1.0 inch of GMCH (AA33)

Close to Pin R14

Close to Pin R33

Trace width of 12mils and space10mils(min)

DDR Resistive Compensation

R398 Change to 31.12K is real*DDR RCOMP VOH Circuitry

DDR RCOMP VOL Circuitry

R163 Change to 31.12K is real*

LA-1911 0.2

Springdale-DDR Interface-B(3/5)B

9 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

DDRB_SDQ52

DDRB_SDQ48

DDRB_SDQ45

DDRB_SDQ25

DDRB_SDQ1

DDRB_SMA1

DDRB_SDQ43

DDRB_SDQ28

DDRB_SDQ16

DDRB_SDQ15

DDRB_SDQ7

DDRB_SDQ31

DDRB_SDQ26

DDRB_SDQ13DDRB_SDQ12

DDRB_SDQ10

DDRB_SMA4

DDRB_SDQ60

DDRB_SDQ50

DDRB_SDQ46

DDRB_SDQ39

DDRB_SMA6

DDRB_SDQ[0..63]

DDRB_SDQ18

DDRB_SDQ6

DDRB_SDQ4

DDRB_SMA12

DDRB_SCS#0

DDRB_SDQ55

DDRB_SDQ49

DDRB_SDQ38

DDRB_SDQ27

DDRB_SMA10DDRB_SMA11

DDRB_SDQ51

DDRB_SDQ44

DDRB_SDQ35

DDRB_SDQ30

DDRB_SDQ22

DDRB_SDQ17

DDRB_SDQ0

DDRB_SMA7

DDRB_SMA5

DDRB_SDQ62

DDRB_SDQ14

DDRB_SDQ3DDRB_SDQ2

DDRB_SMA2

DDRB_SMA9

DDRB_SCS#1

DDRB_SDQ58

DDRB_SDQ24

DDRB_SDQ54

DDRB_SDQ47

DDRB_SDQ19

DDRB_SMA0

DDRB_SDQ42

DDRB_SDQ40

DDRB_SMA[0..12]

DDRB_SDQ36

DDRB_SDQ29

DDRB_SMA3

DDRB_SDQ63

DDRB_SDQ34

DDRB_SDQ21

DDRB_SMA8

DDRB_SDQ61

DDRB_SDQ59

DDRB_SDQ56

DDRB_SDQ33

DDRB_SDQ20

DDRB_SDQ53

DDRB_SDQ41

DDRB_SDQ32

DDRB_SDQ23

DDRB_SDQ9DDRB_SDQ8

DDRB_SDQ57

DDRB_SDQ37

DDRB_SDQ11

DDRB_SDQ5

DDRB_CKE0DDRB_CKE1

SMYRCOMPVOH

SMYRCOMPVOH

SMYRCOMPVOL

SMYRCOMPVOL

SMYRCOMP

SMYRCOMP

+2.5V +SM_VREF_B

+2.5V

+2.5V

+2.5V

DDR Channel B

U43C

SPRINGDALE_UFCBGA932

AG31AJ31AD27AE24AK27AG25AL25AF21AL23AJ22AF29AL21AJ20

AE27AD26AL29AL27AE23

W27W31W26

Y25AA25

U26T29V25

W25

AK19AF19AG19AE18

AG29AG30AF17AG17

N27N26

AJ30AH29AK15AL15

N31N30

AP9

AA33

R34

R33

AF15AG11AJ10AE15AL11AE16AL8AF12AK11AG12

AG13AG15

AE17AL13AK17AL17AK13AJ14AJ16AJ18

AG21AE21

AE19AE20AG23AK23AL19AK21AJ24AE22

AH27AJ28

AK25AH26AG27AF27AJ26AJ27AD25AF28

AD29AC31

AE30AC27AC30Y29AE31AB29AA26AA27

U30U31

AA30W30U27T25AA31V29U25R27

L27M29

P29R30K28L30R31R26P25L32

J30J31

K30H29F32G33N25M25J29G32

SMAA_B0SMAA_B1SMAA_B2SMAA_B3SMAA_B4SMAA_B5SMAA_B6SMAA_B7SMAA_B8SMAA_B9SMAA_B10SMAA_B11SMAA_B12

SMAB_B1SMAB_B2SMAB_B3SMAB_B4SMAB_B5

SWE_B#SCAS_B#SRAS_B#

SBA_B0SBA_B1

SCS_B0#SCS_B1#SCS_B2#SCS_B3#

SCKE_B0SCKE_B1SCKE_B2SCKE_B3

SCMDCLK_B0SCMDCLK_B0#SCMDCLK_B1SCMDCLK_B1#SCMDCLK_B2SCMDCLK_B2#SCMDCLK_B3SCMDCLK_B3#SCMDCLK_B4SCMDCLK_B4#SCMDCLK_B5SCMDCLK_B5#

SMVREF_B

SMYRCOMP

SMYRCOMPVOH

SMYRCOMPVOL

SDQS_B0SDM_B0SDQ_B0SDQ_B1SDQ_B2SDQ_B3SDQ_B4SDQ_B5SDQ_B6SDQ_B7

SDQS_B1SDM_B1

SDQ_B8SDQ_B9

SDQ_B10SDQ_B11SDQ_B12SDQ_B13SDQ_B14SDQ_B15

SDQS_B2SDM_B2

SDQ_B16SDQ_B17SDQ_B18SDQ_B19SDQ_B20SDQ_B21SDQ_B22SDQ_B23

SDQS_B3SDM_B3

SDQ_B24SDQ_B25SDQ_B26SDQ_B27SDQ_B28SDQ_B29SDQ_B30SDQ_B31

SDQS_B4SDM_B4

SDQ_B32SDQ_B33SDQ_B34SDQ_B35SDQ_B36SDQ_B37SDQ_B38SDQ_B39

SDQS_B5SDM_B5

SDQ_B40SDQ_B41SDQ_B42SDQ_B43SDQ_B44SDQ_B45SDQ_B46SDQ_B47

SDQS_B6SDM_B6

SDQ_B48SDQ_B49SDQ_B50SDQ_B51SDQ_B52SDQ_B53SDQ_B54SDQ_B55

SDQS_B7SDM_B7

SDQ_B56SDQ_B57SDQ_B58SDQ_B59SDQ_B60SDQ_B61SDQ_B62SDQ_B63

R444

150_0603_1%

12

C612

2.2U_0805_16V4Z 1

2

R49442.2_0603_1%

12

R442

150_0603_1%

12

C3001U_0603_10V6K

1

2

R49642.2_0603_1%

12

R22310K_0603_1%

12

R51010K_0603_1%

12

C685

2.2U_0805_16V4Z 1

2

C296

0.01U_0402_16V7K

1

2

C598

2.2U_0805_16V4Z 1

2

R22430.9K_0603_1%

12

C6911U_0603_10V6K

1

2

C709

2.2U_0805_16V4Z 1

2

C316

2.2U_0805_16V4Z 1

2

C778

0.01U_0402_16V7K

1

2

C292

0.01U_0402_16V7K

1

2

R50630.9K_0603_1%

12

C138

0.1U_0402_16V4Z 1

2

DDRB_SMA[0..12]13,14

DDRB_SDQ[0..63] 13,14

DDRB_SDQS0 13,14

DDRB_SDQS1 13,14

DDRB_SDQS2 13,14

DDRB_SDQS3 13,14

DDRB_SDQS4 13,14

DDRB_SDQS5 13,14

DDRB_SDQS6 13,14

DDRB_SDQS7 13,14

DDRB_SDM0 13,14

DDRB_SDM1 13,14

DDRB_SDM2 13,14

DDRB_SDM3 13,14

DDRB_SDM4 13,14

DDRB_SDM5 13,14

DDRB_SDM6 13,14

DDRB_SDM7 13,14

DDRB_CLK113DDRB_CLK1#13DDRB_CLK213DDRB_CLK2#13

DDRB_SCS#013,14DDRB_SCS#113,14

DDRB_SBS013,14DDRB_SBS113,14

DDRB_CKE013,14DDRB_CKE113,14

DDRB_SWE#13,14DDRB_SCAS#13,14DDRB_SRAS#13,14

Page 10: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Close to GMCH ball <250mils

Close to GMCH ball <250mils

Note:HI_SWING_MCH, HI_VREF_MCHtrace width of 10mils andspace 7mils

Note:CI_SWING_MCH, CI_VREF_MCHtrace width of 10mils andspace 20mils

Note:Springdale Customer Schematic R1.2 page18AGP_SWING only had 0.1u cap ; But SpringdaleChipset Platform Design guide Rev1.11(12474)page138 had a 0.01uf cap. need confirm withIntel.

Close GMCH ball (AC3) less than 250mils

Follow Springdale Chipset Platform Design guide Rev1.11(12474)

Close GMCH ball (AD2)less than 250mils

0.35V

Analog RGB/CRT guidelinesfor Springdale-P

Close to GMCH(AE3)

Close to GMCH(AE2)

Close to GMCH ball <250mils

Close to GMCH(AF2)

Close to GMCH ball <250mils

Close to GMCH(AF4)

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

+AGP_VREF = 0.3535

GMCH-HUB Reference Circuit

GMCH-CSA Reference Circuit

GMCH-AGP Reference Circuit

LA-1911 0.2

Springdale-AGP/HUB/VGA/CSA (4/5)B

10 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

AGP_AD4

AGP_SBA2

AGP_SBA7

AGP_C/BE#3

AGP_PAR

CLK_MCH_66M AGP_AD3

AGP_AD13

AGP_AD22

AGP_SBA1

AGP_ST1

HUB_HL10

AGP_SBA0

AGP_SBA3

AGP_SBA6

AGP_AD0AGP_AD1

AGP_AD28

AGP_AD30

HUB_HL5

HUB_HL9

AGP_AD27

AGP_ST2

HUB_HL1

AGP_AD8

AGP_AD17

AGP_AD11AGP_AD12

AGP_AD16

AGP_AD24

AGP_C/BE#1

AGP_AD5AGP_AD6

HUB_HL6

AGP_AD15

AGP_AD29

AGP_C/BE#2

HUB_HL3

HUB_HL8

AGP_AD2

AGP_AD7

AGP_AD20

AGP_AD26

AGP_ST0

HUB_HL4

AGP_AD18

AGP_AD23

AGP_SBA5

AGP_AD14

HUB_HL0

HUB_HL2

AGP_AD25

AGP_C/BE#0

AGP_AD19

AGP_AD31

AGP_SBA4

HUB_HL7

AGP_AD9AGP_AD10

AGP_AD21

GRCOMP

GRCOMP

AGP_SWING+AGP_VREF

HI_RCOMP_MCH

HI_RCOMP_MCHHI_SWING_MCHHI_VREF_MCH

HI_SWING_MCH

CI_SWING_GMCHCI_VREF_GMCH

CI_SWING_GMCH

CI_VREF_GMCH

+AGP_VREF

CLK_MCH_66M

HI_VREF_MCH

AGP_SWING

+1.5VS

+1.5VS

+1.5VS

+1.5VS

+1.5VS

+1.5VS

+AGP_VREF

+3VS

C175

0.1U_0402_16V4Z

1

2

R99

147_0603_1%

12

R170 0_0402_5%12

R435 52.3_0603_1%1 2

C151

0.1U_0402_16V4Z

1

2

R460 0_0402_5%12

C171

0.01U_0402_16V7K

1

2

R128 0_0402_5%12

R163

226_0603_1%

12

R165 0_0402_5%12

R596@0_0402_5%12

C624@10P_0402_50V8K

1

2

R11243.2_0402_1%

12

R14339.2_0603_1%

12

R590@1K_0402_5%1 2

R100

226_0603_1%

12

C149

0.1U_0402_16V4Z

1

2

C1600.01U_0402_16V7K

1

2

R439

147_0603_1%

12

R14444.2_0603_1%

1 2

C6030.01U_0402_16V7K

1

2

C1700.01U_0402_16V7K

1

2

R149 0_0402_5%12

R169 0_0402_5%12

R172 0_0402_5%12

R437

113_0603_1%

12

VGA

AGP

HUB

CSA

U43D

SPRINGDALE_UFCBGA932

Y7W5

AA3U2

U6H4

AB4V11AB5W11AB2

N6M7

AC2AC3AD2

R10R9M4M5

N3N5N2

AF5AG3AK2AG5AK5AL3AL2AL4AJ2AH2AJ3AH5AH4

AD4AE3AE2

AK7AH7

AD11AF7AD7

AC10AF8AG7AE9AH9AG6AJ6AJ5

AG2AF2AF4

G4AP8AJ8AK4

AG10AG9

AN35AP34

AR1

AC6AC5

AE6AC11AD5AE5AA10AC9AB11AB7AA9AA6AA5W10AA11W6W9V7

V4V5

AA2Y4Y2W2Y5V2W3U3T 2T 4T 5R2P2P5P4M2

U11T11

R6P7R3R5U9U10U5T 7

H3F2

F4E4H6G5H7G6

G3E2

D2

A3A33A35AF13AF23AJ12AN1AP2AR3AR33AR35B2B25B34C1C23C35E26M31R25

GCBE0GCBE1GCBE2GCBE3

GFRAMEGCLKINGDEVSELGIRDYGTRDYGSTOPGPAR/ADD_DETECTGREQGGNT

GRCOMP/DVOBCGCOMPGVSWINGGVREF

GRBFGWBFDBI_HIDBI_LO

GST0GST1GST2

HI0HI1HI2HI3HI4HI5HI6HI7HI8HI9HI10HISTRFHISTRS

HI_RCOMPHI_SWINGHI_VREF

CI0CI1CI2CI3CI4CI5CI6CI7CI8CI9CI10CISTRFCISTRS

CI_RCOMPCI_SWINGCI_VREF

DREFCLKEXTTS#ICH_SYNC#RSTIN#

RESERVED_1RESERVED_2RESERVED_3RESERVED_4RESERVED_5

GADSTBF0GADSTBS0#

GAD0GAD1GAD2GAD3GAD4GAD5GAD6GAD7GAD8GAD9

GAD10GAD11GAD12GAD13GAD14GAD15

GADSTBF1GADSTBS1#

GAD16GAD17GAD18GAD19GAD20GAD21GAD22GAD23GAD24GAD25GAD26GAD27GAD28GAD29GAD30GAD31

GSBSTBFGSBSTBS#

GSBA0#GSBA1#GSBA2#GSBA3#GSBA4#GSBA5#GSBA6#GSBA7#

DDCA_DATADDCA_CLK

REDRED#

GREENGREEN#

BLUEBLUE#

HSYNCVSYNC

REFSET

NC_1NC_2NC_3NC_4NC_5NC_6NC_7NC_8NC_9

NC_10NC_11NC_12NC_13NC_14NC_15NC_16NC_17NC_18NC_19NC_20

C1370.01U_0402_16V7K

1

2

R453@10_0402_5%

12

C605

0.1U_0402_16V4Z

1

2

R150

60.4_0603_1%

12

C1580.01U_0402_16V7K

1

2

R108

113_0603_1%

12

C164

0.1U_0402_16V4Z

1

2

R166 0_0402_5%12

R151

100_0603_1%

12

R103

52.3_0603_1%

12

AGP_SB_STBF 16AGP_SB_STBS 16AGP_SBA[0..7] 16

AGP_AD_STBS0 16

AGP_AD_STBF1 16AGP_AD_STBS1 16

AGP_C/BE#[0..3]16

CLK_MCH_66M15AGP_FRAME #16

AGP_IRDY#16AGP_TRDY#16

AGP_DEVSEL#16

AGP_STOP#16

AGP_REQ#16AGP_GNT #16

AGP_PAR16

AGP_ST[0..2]16

AGP_WBF#16AGP_RBF#16

AGP_DBIHI16AGP_DBILO16

HUB_HL[0..10]23

HUB_HLSTRF23HUB_HLSTRS23

AGP_AD[0..31] 16

PCIRST#16,22,23,26,27,29,30,33,34,37

AGP_AD_STBF0 16

Page 11: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Trace 14mils

Trace 14milsTrace 14mils

Close to GMCH

Note: Please change to 0.82uH, DC currentof 30mA parts and close to cap

Note:Placed less than 100 mils from ball

Note:Placed less than 100 mils from ball

Decoupling Reference Document:Springdale Chipset Platform Design guide Rev1.11(12474)page246,248

Place at the output of the 1.5V VR

Decoupling Reference Document:Springdale Customer Schematic R1.2 page84

*

Route to GMCH ball without via

Route to GMCH ball without via

(1A)

Close to GMCH

(1A)(1A)

Note: Please change to 1uH(0.54uH-D-IN), DC currentof 1000mA parts and close to capTrace 50milsTrace 35mils (under GMCH ball field)

Trace 35mils

Place near GMCHPlace near ballY11,routing tracefrom cap to ballPlace near GMCH

Compal Electronics, Inc.

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

**

**

LA-1911 0.2

Springdale-Decoupling (5/5)B

11 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

VTT_DCAP2

VTT_DCAP3

VCC_AGP_DCAP2

VCC_DDR_DCAP5VCC_DDR_DCAP4

VCC_DDR_DCAP1

VCC_DDR_DCAP2 VCCA_FSB1 VCCA_FSB

VCCA_FSB

VCCA1P5_DDR_SM

VCCA_DPLLVCCA_DAC

VCCA_DDR VCCA1P5_DDR_SM

VCC_AGP_DCAP1

VTT_DCAP1

+2.5V

+VTT_GMCH

+1.5VS

+3VS

+1.5VS

+1.5VS

+1.5VS

+1.5VS

+1.5VS

+VTT_GMC H

+1.5VS+VTT_GMCH +2.5V

+2.5V

+2.5V

+1.5VS

C201

0.1U_0402_10V6K

1

2

C243

10U_1206_10V4Z

C105

0.1U_0402_10V6K

1

2

+C266

470U_D4_2.5VM

1

2

C248 0.1U_0402_10V6K

1 2

C98

0.1U_0402_10V6K

1

2

R467 0_0402_5%12

C240

0.1U_0402_16V4Z 1

2

C2420.1U_0402_10V6K

1

2

C6180.1U_0402_10V6K

12

C1660.1U_0402_10V6K

1 2

C1280.1U_0402_10V6K

12

L18

0_0805_5%

1 2

C7360.47U_0603_16V7K

12

C117

0.1U_0402_10V6K

1

2

C234

0.1U_0402_10V6K

1

2

C681

0.47U_0603_16V7K

1

2

C103

0.1U_0402_10V6K

1

2

C231

0.1U_0402_10V6K

1

2

C22222U_1206_6.3V6M

1

2

C719 0.22U_0603_10V7K

12

C224

4.7U_0805_6.3V6K

1

2

C229

0.1U_0402_10V6K

1

2

C246

0.1U_0402_10V6K

1

2

C220

0.1U_0402_10V6K

1

2

C114

0.1U_0402_10V6K

1

2

C283

0.1U_0402_10V6K

1

2

C1480.1U_0402_10V6K

1

2

C258

4.7U_0805_6.3V6K

1

2

C217

0.1U_0402_10V6K

1

2

C150

0.1U_0402_10V6K

1

2

C91

4.7U_0805_6.3V6K

1

2C90

22U_1206_10V4Z

1

2

C2330.1U_0402_10V6K

1

2

C216

0.1U_0402_10V6K

1

2

R1830_0603_5%

12

POWER

U43E

SPRINGDALE_UFCBGA932

F7E7E6D7D6D5C6C5B6B5

A31

A21A15

AA35

AL35

AL6AL7AM1AM2AM3AM5AM6AM7AM8AN2AN4AN5AN6AN7AN8AP3AP4AP5AP6AP7

AR15AR21AR31

AR4AR5AR7E35R35

G1G2

Y11

B4B3C2

AB25AC25AC26

J6J7J8J9K6K7K8K9L6L7L9L10L11M8M9M10M11N9N10N11P10P11R11T16T17T18T19T20U16U17U20V16V18V20W16W19W20Y16Y17Y18Y19Y20

AG1

J1J2J3J4J5K2K3K4K5L1L2L3L4L5Y1

D3

A4

A6A5

VTTVTTVTTVTTVTTVTTVTTVTTVTTVTT

VCCA_FSB

VTTVTT

VCC_DDR

VCCA_DDR

VCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDRVCC_DDR

VCC_DACVCC_DAC

VCCA_AGP

VCCA_FSBVCCA_DPLLVCCA_DAC

VCCA_DDRVCCA_DDRVCCA_DDR

VCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCC

VCCA_AGP

VCC_AGPVCC_AGPVCC_AGPVCC_AGPVCC_AGPVCC_AGPVCC_AGPVCC_AGPVCC_AGPVCC_AGPVCC_AGPVCC_AGPVCC_AGPVCC_AGPVCC_AGP

VSSA_DAC

VTT

VTTVTT

C329 0.1U_0402_10V6K12

C244

0.47U_0603_16V7K

1

2

L15

LQG21F4R7N00_0805

1 2

C123

0.1U_0402_10V6K

1

2

R1410_0603_5%

12

C213

0.1U_0402_10V6K

1

2

C207

0.1U_0402_10V6K

1

2

C241

0.1U_0402_16V4Z 1

2

C620 0.22U_0603_10V7K

12

+C198

470U_D4_2.5VM

1

2

C197

0.1U_0402_10V6K

1

2C7130.1U_0402_10V6K1

2

C2491U_0603_10V6K

1

2

C699

0.47U_0603_16V7K

1

2

R462 0_0402_5%12

C235

0.1U_0402_16V4Z 1

2

C109

0.1U_0402_10V6K

1

2

C208

0.1U_0402_10V6K

1

2

C253

4.7U_0805_6.3V6K

1

2

+ C214

150U_D2_6.3VM

12

Page 12: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SO-DIMM 0REVERSE

DDRA_VREF trace width of12mils and space 12mils(min)

Decoupling Reference Document:Springdale Chipset Platform Design guide Rev1.11(12474)pag 271 each DIMM(two) requirement 0.1uF*42

Decoupling Reference Document:Springdale Customer Schematic R1.2 page22each Channel(two DIMMs) requirement 22uF*1 ; 0.1uF*14

Close to SO-DIMM

H = 5.2mmTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

System Memory Decoupling caps

LA-1911 0.2

12 57Friday, August 08, 2003

Compal Electronics, Inc.

DDR-SODIMM SLOT1Title

Size Document Number Rev

Date: Sheet of

DDRA_SDQ31

DDRA_SDQ4

DDRA_SMA6

DDRA_SMA8

DDRA_SDQS[0..7]

DDRA_SDQ26

DDRA_SDM[0..7]

DDRA_SDQ14

DDRA_SDM4

DDRA_SDM5

DDRA_SMA4

DDRA_SBS1

DDRA_SMA[0..12]

DDRA_SDQ56

DDRA_SMA0

DDRA_SDQ24

DDRA_SMA2

DDRA_SDM0

DDRA_SDQ11

DDRA_SCS#1

DDRA_SDM1

DDRA_SDQ58

DDRA_SDQ25

DDRA_SCAS#

DDRA_SDM3

DDRA_SDQ38

DDRA_SDM7

DDRA_SDQ40

DDRA_SDQ63

DDRA_CKE0

DDRA_SDQ9

DDRA_SDM2

DDRA_SDQ12

DDRA_SRAS#

DDRA_SDQ57

DDRA_SDQ47

DDRA_SMA11

DDRA_SDQ[0..63]

DDRA_VREF

DDRA_CKE1

DDRA_SCS#0

DDRA_SDQ19

DDRA_SMA10

DDRA_SMA9DDRA_SMA12

DDRA_SMA5

DDRA_SMA1DDRA_SMA3

DDRA_SMA7

DDRA_SDQ29

DDRA_SWE#DDRA_SBS0

DDRA_SDQ27

DDRA_SDQ13

DDRA_SDQ30

DDRA_SDQ0

DDRA_SDQ20

DDRA_SDQS3

DDRA_SDQ61

DDRA_SDQ43

DDRA_SDQS0

DDRA_SDQS1

DDRA_SDQS2

DDRA_SDQS4

DDRA_SDQS5

DDRA_SDQS7

DDRA_SDQS6

DDRA_SDQ15

DDRA_SDQ36

DDRA_SDQ10

DDRA_SDQ62DDRA_SDQ59

DDRA_SDQ35

DDRA_SDQ3

DDRA_SDQ8

DDRA_SDQ28DDRA_SDQ23

DDRA_SDQ44DDRA_SDQ39

DDRA_SDQ5

DDRA_SDQ6 DDRA_SDQ7

DDRA_SDQ1

DDRA_SDQ2

DDRA_SDQ18

DDRA_SDQ16DDRA_SDQ21DDRA_SDQ17

DDRA_SDQ22

DDRA_SDQ37

DDRA_SDQ34

DDRA_SDQ32DDRA_SDQ33

DDRA_SDQ46

DDRA_SDQ41 DDRA_SDQ45

DDRA_SDQ42

DDRA_SDQ50DDRA_SDQ60

DDRA_SDQ53DDRA_SDQ48

DDRA_SDQ51

DDRA_SDQ52DDRA_SDQ49

DDRA_SDM6

DDRA_SDQ55

DDRA_SDQ54

+2.5V

+2.5V

+2.5V

+3VS

+2.5V

+2.5V

C247

0.1U_0402_10V6K

1

2

R92

75_0603_1%

12

C276

0.1U_0402_10V6K

1

2

C341

0.1U_0402_10V6K

1

2

C116

22U_1206_10V4Z

1

2

C204

0.1U_0402_10V6K

1

2

C134

0.1U_0402_10V6K

1

2

C255

0.1U_0402_10V6K

1

2

C354

0.1U_0402_10V6K

1

2

C319

0.1U_0402_10V6K

1

2

C227

0.1U_0402_10V6K

1

2

JP22

KEYLINK_5762-3-111

13579

111315171921232527293133353739

414345474951535557596163656769717375777981838587899193959799

101103105107109111113115117119121123125127129131133135137139141143

246810121416182022242628303234363840

4244464850525456586062646668707274767880828486889092949698100102104106108110112114116118120122124126128130132134136138140142144

145147149151153155157159161163165167169171173175177179181183185187189191193195197199

146148150152154156158160162164166168170172174176178180182184186188190192194196198200

VREFVSSDQ0DQ1VDDDQS0DQ2VSSDQ3DQ8VDDDQ9DQS1VSSDQ10DQ11VDDCK0CK0#VSS

DQ16DQ17VDDDQS2DQ18VSSDQ19DQ24VDDDQ25DQS3VSSDQ26DQ27VDDCB0CB1VSSDQS8CB2VDDCB3DUVSSCK2CK2#VDDCKE1DU/A13A12A9VSSA7A5A3A1VDDA10/APBA0WE#S0#DUVSSDQ32DQ33VDDDQS4DQ34VSSDQ35DQ40VDD

VREFVSSDQ4DQ5VDDDM0DQ6VSSDQ7

DQ12VDD

DQ13DM1VSS

DQ14DQ15VDDVDDVSSVSS

DQ20DQ21VDDDM2

DQ22VSS

DQ23DQ28VDD

DQ29DM3VSS

DQ30DQ31VDDCB4CB5VSSDM8CB6VDDCB7

DU/RESET#VSSVSSVDDVDD

CKE0DU/BA2

A11A8

VSSA6A4A2A0

VDDBA1

RAS#CAS#

S1#DU

VSSDQ36DQ37VDDDM4

DQ38VSS

DQ39DQ44VDD

DQ41DQS5VSSDQ42DQ43VDDVDDVSSVSSDQ48DQ49VDDDQS6DQ50VSSDQ51DQ56VDDDQ57DQS7VSSDQ58DQ59VDDSDASCLVDD_SPDVDD_ID

DQ45DM5VSS

DQ46DQ47VDD

CK1#CK1VSS

DQ52DQ53VDDDM6

DQ54VSS

DQ55DQ60VDD

DQ61DM7VSS

DQ62DQ63VDDSA0SA1SA2

DU

C347

0.1U_0402_10V6K

1

2

C192

0.1U_0402_10V6K

1

2

C161

0.1U_0402_10V6K

1

2

C330

0.1U_0402_10V6K

1

2

C302

0.1U_0402_10V6K

1

2

R87

75_0603_1%

12

C100

0.1U_0402_16V4Z

1

2

DDRA_SDQ[0..63]8,14

DDRA_SDQS[0..7]8,14

DDRA_SDM[0..7]8,14

DDRA_SMA[0..12]8,14

DDRA_SBS1 8,14

DDRA_CLK2 8DDRA_CLK2# 8

DDRA_SRAS# 8,14DDRA_SCAS# 8,14DDRA_SCS#1 8,14

DDRA_CKE0 8,14DDRA_CKE18,14

ICH_SMB_DATA13,15,23ICH_SMB_CLK13,15,23

DDRA_SCS#08,14

DDRA_SBS08,14DDRA_SWE#8,14

DDRA_CLK18DDRA_CLK1#8

Page 13: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

REVERSESO-DIMM 2

System Memory Decoupling caps

DDRB_VREF trace width of12mils and space 12mils(min)

Decoupling Reference Document:Springdale Customer Schematic R1.2 page26each Channel(two DIMMs) requirement 0.1uF*24

H= 9.2mmMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-1911 0.2

13 57Friday, August 08, 2003

Compal Electronics, Inc.

DDR-SODIMM SLOT2Title

Size Document Number Rev

Date: Sheet of

DDRB_SMA4

DDRB_SDM7

DDRB_SDQ47

DDRB_SDQ[0..63]

DDRB_SMA[0..12]

DDRB_SDM3

DDRB_SMA6

DDRB_SMA2

DDRB_SDQ2

DDRB_SMA8

DDRB_SDM2

DDRB_SDQS[0..7]

DDRB_SDM[0..7]DDRB_SDM0

DDRB_SRAS#

DDRB_SDM5

DDRB_SDM4

DDRB_SDM6

DDRB_SCAS#

DDRB_SDQ31DDRB_SDQ27

DDRB_SMA11

DDRB_SDQ28

DDRB_SDM1

DDRB_SMA0

DDRB_SDQ0

DDRB_SCS#1

DDRB_SDQ29

DDRB_SBS1

DDRB_CKE0

DDRB_SDQ7

DDRB_VREF

DDRB_SDQ21

DDRB_SDQS3

DDRB_SDQ52

DDRB_SDQS0

DDRB_SDQS2

DDRB_SDQS1

DDRB_SDQS4

DDRB_SDQS6

DDRB_SDQS5

DDRB_SDQS7

DDRB_SCS#0

DDRB_SMA12DDRB_SMA9

DDRB_CKE1

DDRB_SMA3

DDRB_SMA7

DDRB_SMA10

DDRB_SMA1

DDRB_SMA5

DDRB_SBS0DDRB_SWE#

DDRB_SDQ5

DDRB_SDQ25

DDRB_SDQ44

DDRB_SDQ20

DDRB_SDQ49

DDRB_SDQ6

DDRB_SDQ1

DDRB_SDQ24

DDRB_SDQ60

DDRB_SDQ4

DDRB_SDQ9

DDRB_SDQ14DDRB_SDQ10

DDRB_SDQ12

DDRB_SDQ15DDRB_SDQ8

DDRB_SDQ11

DDRB_SDQ3DDRB_SDQ13

DDRB_SDQ32DDRB_SDQ34

DDRB_SDQ35

DDRB_SDQ36DDRB_SDQ33

DDRB_SDQ37

DDRB_SDQ38

DDRB_SDQ39

DDRB_SDQ42

DDRB_SDQ40

DDRB_SDQ43 DDRB_SDQ41

DDRB_SDQ45

DDRB_SDQ46

DDRB_SDQ51

DDRB_SDQ54DDRB_SDQ50

DDRB_SDQ55

DDRB_SDQ53DDRB_SDQ48

DDRB_SDQ58

DDRB_SDQ62

DDRB_SDQ63

DDRB_SDQ61

DDRB_SDQ59DDRB_SDQ57

DDRB_SDQ56

DDRB_SDQ23

DDRB_SDQ18

DDRB_SDQ16

DDRB_SDQ17

DDRB_SDQ19

DDRB_SDQ22

DDRB_SDQ26DDRB_SDQ30

+2.5V

+2.5V

+2.5V

+2.5V+2.5V

+3VS

+2.5V

+3VS

C256

0.1U_0402_10V6K

1

2

C165

0.1U_0402_10V6K

1

2

C346

0.1U_0402_10V6K

1

2

C190

0.1U_0402_10V6K

1

2

C113

0.1U_0402_10V6K

1

2

C318

0.1U_0402_10V6K

1

2

C353

0.1U_0402_10V6K

1

2

C223

0.1U_0402_10V6K

1

2

C309

0.1U_0402_10V6K

1

2

C162

0.1U_0402_10V6K

1

2

C355

0.1U_0402_10V6K

1

2

C254

0.1U_0402_10V6K

1

2

C118

0.1U_0402_10V6K

1

2

C225

0.1U_0402_10V6K

1

2

C312

0.1U_0402_10V6K

1

2

C193

0.1U_0402_10V6K

1

2

C333

0.1U_0402_10V6K

1

2

R86

75_0603_1%

12

C1010.1U_0402_16V4Z

1

2

C289

0.1U_0402_10V6K

1

2

C189

0.1U_0402_10V6K

1

2

C281

0.1U_0402_10V6K

1

2

R90

75_0603_1%

12

JP23

KLINK_5746-3-111

13579

111315171921232527293133353739

414345474951535557596163656769717375777981838587899193959799

101103105107109111113115117119121123125127129131133135137139141143

246810121416182022242628303234363840

4244464850525456586062646668707274767880828486889092949698100102104106108110112114116118120122124126128130132134136138140142144

145147149151153155157159161163165167169171173175177179181183185187189191193195197199

146148150152154156158160162164166168170172174176178180182184186188190192194196198200

VREFVSSDQ0DQ1VDDDQS0DQ2VSSDQ3DQ8VDDDQ9DQS1VSSDQ10DQ11VDDCK0CK0#VSS

DQ16DQ17VDDDQS2DQ18VSSDQ19DQ24VDDDQ25DQS3VSSDQ26DQ27VDDCB0CB1VSSDQS8CB2VDDCB3DUVSSCK2CK2#VDDCKE1DU/A13A12A9VSSA7A5A3A1VDDA10/APBA0WE#S0#DUVSSDQ32DQ33VDDDQS4DQ34VSSDQ35DQ40VDD

VREFVSSDQ4DQ5VDDDM0DQ6VSSDQ7

DQ12VDD

DQ13DM1VSS

DQ14DQ15VDDVDDVSSVSS

DQ20DQ21VDDDM2

DQ22VSS

DQ23DQ28VDD

DQ29DM3VSS

DQ30DQ31VDDCB4CB5VSSDM8CB6VDDCB7

DU/RESET#VSSVSSVDDVDD

CKE0DU/BA2

A11A8

VSSA6A4A2A0

VDDBA1

RAS#CAS#

S1#DU

VSSDQ36DQ37VDDDM4

DQ38VSS

DQ39DQ44VDD

DQ41DQS5VSSDQ42DQ43VDDVDDVSSVSSDQ48DQ49VDDDQS6DQ50VSSDQ51DQ56VDDDQ57DQS7VSSDQ58DQ59VDDSDASCLVDD_SPDVDD_ID

DQ45DM5VSS

DQ46DQ47VDD

CK1#CK1VSS

DQ52DQ53VDDDM6

DQ54VSS

DQ55DQ60VDD

DQ61DM7VSS

DQ62DQ63VDDSA0SA1SA2

DU

C168

0.1U_0402_10V6K

1

2

C331

0.1U_0402_10V6K

1

2

C305

0.1U_0402_10V6K

1

2

C139

0.1U_0402_10V6K

1

2

DDRB_SMA[0..12]9,14

DDRB_SDQ[0..63]9,14

DDRB_SDQS[0..7]9,14

DDRB_SDM[0..7]9,14

DDRB_CLK2 9DDRB_CLK2# 9

DDRB_SBS1 9,14

DDRB_CKE0 9,14

DDRB_SRAS# 9,14DDRB_SCAS# 9,14DDRB_SCS#1 9,14

DDRB_CLK19DDRB_CLK1#9

DDRB_CKE19,14

DDRB_SCS#09,14

DDRB_SBS09,14DDRB_SWE#9,14

ICH_SMB_DATA12,15,23ICH_SMB_CLK12,15,23

Page 14: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Channel A(DIMM0) Termination resistors & Decoupling caps

Decoupling Reference Document:Springdale Customer Schematic R1.2 page22each Channel(two DIMMs) requirement 4.7u*2 ; 0.1uF*28

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Channel B(DIMM2) Termination resistors & Decoupling caps

Decoupling Reference Document:Springdale Customer Schematic R1.2 page26each Channel(two DIMMs) requirement 4.7u*2 ; 0.1uF*26

LA-1911 0.2

DDR Termination ResistorsCustom

14 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

DDRA_SDM[0..7]

DDRA_SDQ[0..63]

DDRA_SMA[0..12]

DDRA_SDQS[0..7]

DDRB_SMA[0..12]

DDRB_SDQS[0..7]

DDRB_SDM[0..7]

DDRB_SDQ[0..63]

DDRB_SDQ63DDRB_SDQ59

DDRA_SDQ0DDRA_SDQ1

DDRA_SDQS0DDRA_SDQ6

DDRA_SDQ12DDRA_SDQ2

DDRA_SDQS1DDRA_SDQ8

DDRA_SDQ15DDRA_SDQ10

DDRA_SDQ16DDRA_SDQ20

DDRA_SDQ18DDRA_SDQS2

DDRA_SDQ28DDRA_SDQ19

DDRA_SDQ29DDRA_SDQS3

DDRA_SDQ27DDRA_SDQ30

DDRA_SMA9DDRA_SMA12

DDRA_SMA5DDRA_SMA7

DDRA_SMA1DDRA_SMA3

DDRA_SBS0DDRA_SMA10

DDRA_SCS#0DDRA_SWE#

DDRA_SDQ36DDRA_SDQ37

DDRA_SDQS4DDRA_SDQ34

DDRA_SDQ44DDRA_SDQ35

DDRA_SDQS5DDRA_SDQ41

DDRA_SDQ43DDRA_SDQ46

DDRA_SDQ53DDRA_SDQ48

DDRA_SDQS6DDRA_SDQ54

DDRA_SDQ60DDRA_SDQ55

DDRA_SDQ61DDRA_SDQS7

DDRA_SDQ62DDRA_SDQ59

DDRA_SDQ5DDRA_SDQ4

DDRA_SDQ7DDRA_SDM0

DDRA_SDQ9DDRA_SDQ3

DDRA_SDQ13DDRA_SDM1

DDRA_SDQ11DDRA_SDQ14

DDRA_SDQ21DDRA_SDQ17

DDRA_SDQ22DDRA_SDM2

DDRA_SDQ23DDRA_SDQ24

DDRA_SDQ25DDRA_SDM3

DDRA_SDQ26DDRA_SDQ31

DDRA_SMA11DDRA_SMA8

DDRA_SMA6DDRA_SMA4

DDRA_SMA2DDRA_SMA0

DDRA_SBS1DDRA_SRAS#

DDRA_SDQ32DDRA_SDQ33

DDRA_SDQ38DDRA_SDM4

DDRA_SDQ39DDRA_SDQ40

DDRA_SDM5DDRA_SDQ45

DDRA_SDQ47DDRA_SDQ42

DDRA_SDQ49DDRA_SDQ52

DDRA_SDQ51DDRA_SDM6

DDRA_SDQ50DDRA_SDQ56

DDRA_SDQ57DDRA_SDM7

DDRA_SDQ63DDRA_SDQ58

DDRB_SDQ4DDRB_SDQ0

DDRB_SDQS0DDRB_SDQ7

DDRB_SDQ9DDRB_SDQ5

DDRB_SDQS1DDRB_SDQ12

DDRB_SDQ14DDRB_SDQ10

DDRB_SDQ21DDRB_SDQ20

DDRB_SDQS2DDRB_SDQ22

DDRB_SDQ24DDRB_SDQ17

DDRB_SDQS3DDRB_SDQ25

DDRB_SDQ30DDRB_SDQ26

DDRB_CKE0DDRB_CKE1

DDRB_SMA9DDRB_SMA12

DDRB_SMA5DDRB_SMA7

DDRB_SMA1DDRB_SMA3

DDRB_SMA10DDRB_SBS0

DDRB_SCS#0DDRB_SWE#

DDRB_SDQ34DDRB_SDQ33

DDRB_SDQS4DDRB_SDQ37

DDRB_SDQ40DDRB_SDQ38

DDRB_SDQ44DDRB_SDQS5

DDRB_SDQ43DDRB_SDQ42

DDRB_SDQ52DDRB_SDQ49

DDRB_SDQS6DDRB_SDQ55

DDRB_SDQ50DDRB_SDQ60

DDRB_SDQ56DDRB_SDQS7

DDRB_SDQ57DDRB_SDQ58

DDRB_SDQ6DDRB_SDQ2

DDRB_SDM0DDRB_SDQ1

DDRB_SDQ13DDRB_SDQ3

DDRB_SDQ11DDRB_SDM1

DDRB_SDQ15DDRB_SDQ8

DDRB_SDQ16DDRB_SDQ19

DDRB_SDM2DDRB_SDQ18

DDRB_SDQ23DDRB_SDQ28

DDRB_SDM3DDRB_SDQ29

DDRB_SDQ27DDRB_SDQ31

DDRB_SMA8DDRB_SMA11

DDRB_SMA6DDRB_SMA4

DDRB_SMA0DDRB_SMA2

DDRB_SBS1DDRB_SRAS#

DDRB_SCS#1DDRB_SCAS#

DDRB_SDQ32DDRB_SDQ36

DDRB_SDM4DDRB_SDQ39

DDRB_SDQ46DDRB_SDQ35

DDRB_SDQ45DDRB_SDM5

DDRB_SDQ47DDRB_SDQ41

DDRB_SDQ53DDRB_SDQ48

DDRB_SDM6DDRB_SDQ51

DDRB_SDQ54DDRB_SDQ62

DDRB_SDQ61DDRB_SDM7

DDRA_SCAS#DDRA_SCS#1

DDRA_CKE1DDRA_CKE0

+1.25VS +1.25VS

+1.25VS

+1.25VS

+1.25VS

+1.25VS

+1.25VS

+1.25VS

+1.25VS+1.25VS

+1.25VS

+1.25VS

+1.25VS

C690

0.1U_0402_10V6K

1

2

RP43

56_0404_4P2R_5%

1423

RP98

56_0404_4P2R_5%

1423

RP20

56_0404_4P2R_5%

1 42 3

C313

0.1U_0402_10V6K

1

2

C746

0.1U_0402_10V6K

1

2

RP127

56_0404_4P2R_5%

1 42 3

RP78

56_0404_4P2R_5%

1423

C734

0.1U_0402_10V6K

1

2

RP58

56_0404_4P2R_5%

1 42 3

C348

0.1U_0402_10V6K

1

2RP61

56_0404_4P2R_5%

1423

C111

0.1U_0402_10V6K

1

2

RP56

56_0404_4P2R_5%

1 42 3

RP40

56_0404_4P2R_5%

1423

C608

0.1U_0402_10V6K

1

2

C706

0.1U_0402_10V6K

1

2

C163

0.1U_0402_10V6K

1

2

C263

0.1U_0402_10V6K

1

2

C669

0.1U_0402_10V6K

1

2

RP101

56_0404_4P2R_5%

1423

RP19

56_0404_4P2R_5%

1423

RP122

56_0404_4P2R_5%

1423

C749

0.1U_0402_10V6K

1

2

C614

0.1U_0402_10V6K

1

2

RP100

56_0404_4P2R_5%

1423

RP21

56_0404_4P2R_5%

1423

RP32

56_0404_4P2R_5%

1423

RP24

56_0404_4P2R_5%

1 42 3

RP130

56_0404_4P2R_5%

1423

C129

0.1U_0402_10V6K

1

2RP62

56_0404_4P2R_5%

1 42 3

C202

0.1U_0402_10V6K

1

2

RP72

56_0404_4P2R_5%

1 42 3

RP42

56_0404_4P2R_5%

1423

C655

4.7U_1206_16V6K

1

2

RP6

56_0404_4P2R_5%

1423

RP57

56_0404_4P2R_5%

1423

C298

0.1U_0402_10V6K

1

2

RP45

56_0404_4P2R_5%

1423

RP87

56_0404_4P2R_5%

1 42 3

RP114

56_0404_4P2R_5%

1 42 3

C639

0.1U_0402_10V6K

1

2

RP60

56_0404_4P2R_5%

1 42 3

RP109

56_0404_4P2R_5%

1 42 3

C185

0.1U_0402_10V6K

1

2

C200

0.1U_0402_10V6K

1

2

C606

0.1U_0402_10V6K

1

2

C649

4.7U_0805_10V4Z

12

C720

0.1U_0402_10V6K

1

2

RP116

56_0404_4P2R_5%

1 42 3

RP124

56_0404_4P2R_5%

1423

RP73

56_0404_4P2R_5%

1423

RP91

56_0404_4P2R_5%

1 42 3

C673

0.1U_0402_10V6K

1

2

RP63

56_0404_4P2R_5%

1423

RP52

56_0404_4P2R_5%

1 42 3

RP71

56_0404_4P2R_5%

1423

RP84

56_0404_4P2R_5%

1423

RP11

56_0404_4P2R_5%

1 42 3

RP123

56_0404_4P2R_5%

1 42 3

RP85

56_0404_4P2R_5%

1 42 3

C343

0.1U_0402_10V6K

1

2

C294

0.1U_0402_10V6K

1

2

RP120

56_0404_4P2R_5%

1 42 3 C628

0.1U_0402_10V6K

1

2

RP23

56_0404_4P2R_5%

1423

RP99

56_0404_4P2R_5%

1423

RP121

56_0404_4P2R_5%

1 42 3

C622

4.7U_1206_16V6K

1

2

RP75

56_0404_4P2R_5%

1423

RP27

56_0404_4P2R_5%

1 42 3

C594

0.1U_0402_10V6K

1

2

RP112

56_0404_4P2R_5%

1 42 3

C107

0.1U_0402_10V6K

1

2

RP15

56_0404_4P2R_5%

1423

RP36

56_0404_4P2R_5%

1423

RP53

56_0404_4P2R_5%

1423

RP8

56_0404_4P2R_5%

1423

RP102

56_0404_4P2R_5%

1423

C627

0.1U_0402_10V6K

1

2

RP31

56_0404_4P2R_5%

1423

RP18

56_0404_4P2R_5%

1 42 3

RP117

56_0404_4P2R_5%

1423

RP108

56_0404_4P2R_5%

1423

RP79

56_0404_4P2R_5%

1 42 3

RP10

56_0404_4P2R_5%

1423

C632

0.1U_0402_10V6K

1

2

RP77

56_0404_4P2R_5%

1 42 3

RP107

56_0404_4P2R_5%

1423

RP111

56_0404_4P2R_5%

1423

RP113

56_0404_4P2R_5%

1423

RP50

56_0404_4P2R_5%

1 42 3

RP33

56_0404_4P2R_5%

1423

C638

0.1U_0402_10V6K

1

2

RP35

56_0404_4P2R_5%

1423

RP64

56_0404_4P2R_5%

1 42 3

RP51

56_0404_4P2R_5%

1423

RP129

56_0404_4P2R_5%

1 42 3

RP12

56_0404_4P2R_5%

1423

C187

0.1U_0402_10V6K

1

2

C221

0.1U_0402_10V6K

1

2

RP128

56_0404_4P2R_5%

1423

RP105

56_0404_4P2R_5%

1423

C742

0.1U_0402_10V6K

1

2

RP55

56_0404_4P2R_5%

1423

RP9

56_0404_4P2R_5%

1 42 3

RP44

56_0404_4P2R_5%

1 42 3

C704

0.1U_0402_10V6K

1

2

C349

0.1U_0402_10V6K

1

2

RP74

56_0404_4P2R_5%

1 42 3

C671

0.1U_0402_10V6K

1

2

C279

0.1U_0402_10V6K

1

2

C677

0.1U_0402_10V6K

1

2

RP29

56_0404_4P2R_5%

1423

C172

4.7U_1206_16V6K

1

2

C740

0.1U_0402_10V6K

1

2

C156

0.1U_0402_10V6K

1

2

RP26

56_0404_4P2R_5%

1423

RP59

56_0404_4P2R_5%

1423

RP103

56_0404_4P2R_5%

1423

RP86

56_0404_4P2R_5%

1423

RP106

56_0404_4P2R_5%

1423

C315

0.1U_0402_10V6K

1

2

C338

0.1U_0402_10V6K

1

2

C218

0.1U_0402_10V6K

1

2

C324

0.1U_0402_10V6K

1

2

C260

0.1U_0402_10V6K

1

2

C616

0.1U_0402_10V6K

1

2

C631

0.1U_0402_10V6K

1

2

RP96

56_0404_4P2R_5%

1423

RP76

56_0404_4P2R_5%

1 42 3

RP118

56_0404_4P2R_5%

1 42 3

RP89

56_0404_4P2R_5%

1 42 3

RP119

56_0404_4P2R_5%

1423

RP41

56_0404_4P2R_5%

1423

RP54

56_0404_4P2R_5%

1 42 3

RP115

56_0404_4P2R_5%

1423

RP47

56_0404_4P2R_5%

1 42 3

RP7

56_0404_4P2R_5%

1 42 3

RP34

56_0404_4P2R_5%

1423

RP17

56_0404_4P2R_5%

1423

RP104

56_0404_4P2R_5%

1423

C322

0.1U_0402_10V6K

1

2

C716

0.1U_0402_10V6K

1

2

RP13

56_0404_4P2R_5%

1 42 3

RP88

56_0404_4P2R_5%

1423

C344

0.1U_0402_10V6K

1

2

RP49

56_0404_4P2R_5%

1423

RP22

56_0404_4P2R_5%

1 42 3

RP39

56_0404_4P2R_5%

1423

C593

0.1U_0402_10V6K

1

2

RP16

56_0404_4P2R_5%

1 42 3

C271

0.1U_0402_10V6K

1

2

RP80

56_0404_4P2R_5%

1423

RP97

56_0404_4P2R_5%

1 42 3

C682

0.1U_0402_10V6K

1

2

RP90

56_0404_4P2R_5%

1423

RP38

56_0404_4P2R_5%

1423

DDRA_SDQ[0..63]8,12

DDRA_SDQS[0..7]8,12

DDRA_SDM[0..7]8,12

DDRA_SMA[0..12]8,12

DDRB_SDQ[0..63]9,13

DDRB_SMA[0..12]9,13

DDRB_SDQS[0..7]9,13

DDRB_SDM[0..7]9,13

DDRA_SBS0 8,12

DDRA_SCS#0 8,12DDRA_SWE# 8,12

DDRA_SBS1 8,12DDRA_SRAS# 8,12

DDRA_SCAS# 8,12DDRA_SCS#1 8,12

DDRB_CKE0 9,13DDRB_CKE1 9,13

DDRB_SBS0 9,13

DDRB_SCS#0 9,13DDRB_SWE# 9,13

DDRB_SBS1 9,13DDRB_SRAS# 9,13

DDRB_SCS#1 9,13DDRB_SCAS# 9,13

DDRA_CKE1 8,12DDRA_CKE0 8,12

Page 15: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Place near each pinW>40 mil

Place near CK409

SEL0 SEL1 CPU 3V66[0..3] REF0 REF1 SRC USB/Dot

Trace wide=40 mils

CK409Place crystal within500 mils of CK409

0 0 100 66 14.3 14.3 100/200

0 MID REF REF REF REF REF

0 1 200

48

REF

66 14.3 100/200 48

1 0 133 66 14.3

1 1 166

1 MID Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

66 14.3

100/200

100/200

48

48

Check SPEC (250mA,300 ohm)

14.3

14.3

14.3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

The host clocks to the Processor must be 165 mil longer than thehost clocks to the GMCH

LA-19110.2

15 57Friday, August 08, 2003

Compal Electronics, Inc.Clock Generator

Title

Size Document Number Rev

Date: Sheet of

CLK_HCLK

CLK_BCLK#

CLK_IT P

CLK_HCLK#

CLK66M_OUT 1

PCICLK6

CLK_CPU1

PCICLK5

PCICLK1

CLK_CPU2#

PCICLK_F2

CLK_CPU1#

CLK66M_OUT 3

CLK66M_OUT 0

CLK_CPU2

CLK_CPU0#

PCICLK2

CLK_CPU0

CK_SCLKCK_SDATA

CLK_XTAL_IN

CLK_XTAL_OUT

CLKSEL0CLKSEL1

CLK_VDD_PLL

CLK48M_OUT 0

CLKREF0CLKREF1

CLK_BCLKSLP_S1#STPPCI#STPCPU#

CLK_VTT_PG#

CLKSEL1

CLKSEL0

PCICLK4

PCICLK3

CLK_ITP#

CLK_VDD_PLL

+3VS_CLK+3VS

+3VS

+3VS

+3VS

R198 33_0402_5%

1 2

R207 33_0402_5%

1 2

C212

0.1U_0402_10V6K

1

2

R205 33_0402_5%

1 2

R153

1K_0603_1%

12

R152

2.49K_0603_1%

12

R191 33_0402_5%

1 2

R160 33_0402_5%

1 2

R196 33_0402_5%

12

R200 33_0402_5%

1 2

C23210U_1206_6.3V7K

1

2

R156 33_0402_5%

1 2

L17

BLM21A601SPT_08051 2

R206 33_0402_5%

1 2

R1811K_0603_1%

12

R202 33_0402_5%

1 2

R145

2K_0603_1%

12

R1802K_0603_1%

12

R158 33_0402_5%

1 2R13349.9_0402_1%

1 2

C277@10P_0402_50V8K

12

C211

0.1U_0402_10V6K

1

2

L19

BLM21A601SPT_08051 2

C210

0.1U_0402_10V6K

1

2

R164 475_0603_1%1 2

X2

14.31818MHz_20P_1BX14318CC1A~L

12

R139 1K_0402_5%1 2

R199 33_0402_5%

1 2

R13149.9_0402_1%

1 2

C274

0.1U_0402_10V6K

1

2

C239

0.1U_0402_16V4Z

1

2

C230

10U_1206_6.3V7K

1

2

R155 33_0402_5%

1 2

L16BLM11A601S_06031 2

R201 33_0402_5%

1 2

C261

0.1U_0402_16V4Z

1

2

R182 0_0402_5%12

R1792.49K_0603_1%

12

C273

0.1U_0402_10V6K

1

2

C272

0.1U_0402_10V6K

1

2

R208 33_0402_5%

1 2R137 @0_0402_5%

12

R13249.9_0402_1%

1 2

C215

0.1U_0402_10V6K

1

2

C278@10P_0402_50V8K

12

U11

ICS952623BG_TSSOP56

1

10 16 24 34

63

2

47

46

44

43

41

40

29

26

23

22

9

8

7

20

19

18

15

14

13

12

4

5

11 17

21

25

27

2830

31

32

33

35

36

37

38

3942

45

48

4950

51

52

53

54

56

55

REF_0

VD

D_P

CI

VD

D_P

CI

VD

D_3

V66

VD

D_4

8

VS

S_R

EF

VD

D_R

EF

REF_1

CPUCLKT2

CPU_CLKC2

CPUCLKT1

CPUCLKC1

CPUCLKT0

CPUCLKC0

48/66MHZ_OUT/3V66_4

66MHZ_OUT2/3V66_2

66MHZ_OUT1/3V66_1

66MHZ_OUT0/3V66_0

PCICLK_F2

PCICLK_F1

PCICLK_F0

PCICLK6

PCICLK5

PCICLK4

PCICLK3

PCICLK2

PCICLK1

PCICLK0

XTAL_IN

XTAL_OUT

VS

S_P

CI

VS

S_P

CI

PWRDWN#

VS

S_3

V66

66MHZ_OUT3/3V66_3

SCLKSDATA

USB_48MHZ

DOT_48MHZ

VS

S_4

8

VTT_PWRGD#

VD

D_S

RC

SRCLKN_100MHZ

SRCLKP_100MHZ

VS

S_S

RC

VD

D_C

PU

VSS_CPU

VD

D_C

PU

PCI_STP#CPU_STP#

SEL0

IREF

VS

S_I

RE

F

VSS_PLL

SEL1

VDD_PLL

R197 33_0402_5%

12

R148 1K_0402_5%1 2

R13049.9_0402_1%

1 2

R138 0_0402_5%12

R161 33_0402_5%

12

C275

0.1U_0402_10V6K

1

2

R157 33_0402_5%

1 2

R159 33_0402_5%

1 2

R13449.9_0402_1%

1 2

R214 1K_0402_5%1 2

R13549.9_0402_1%

1 2

R175 @0_0402_5%

12

CLK_14M_SIO34CLK_ICH_14M24

CLK_ICH_48M24

CPU_CLKSEL0 5

CPU_CLKSEL1 5

MCH_CLKSEL0 7MCH_CLKSEL1 7

CLK_HCLK# 7

CLK_HCLK 7

CLK_IT P 5

CLK_ITP# 5

CLK_BCLK 4

CLK_BCLK# 4

CLK_AGP_66M 16

CLK_MCH_66M 10

CLK_ICH_66M 23

CLK_PCI_ICH 23

CLK_PCI_MINI 29

CLK_PCI_CB 27

CLK_PCI_LPC 37

CLK_PCI_1394 30

CLK_PCI_LAN 26

CLK_PCI_SIO 34

ICH_SMB_DATA12,13,23ICH_SMB_CLK12,13,23

CK409_PWRGD#40

Page 16: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PROPRIETARY NOTE

Place closeto pin D+ & D-

PLACE COLSE TO VGAPin AJ5, AJ7,

Selection Table For W180

1.25%

SSTRatio

ModulationSetting

10

SS%

3.75%

Close VGA ball (AK29)less than 250mils-->350mV

SWAPRDY_ANV31,NV34 use.NV18 not use.

(SUS_STAT#)

3

2

1

0

0

1

TVMODE: (01)-NTSC

SUB_VENDOR: 0-SYSTEM BIOS 1-ADAPTER BIOS

PCI_AD_SWAP: 0-RVSERSED 1-NORMAL

CRYSTAL: (10)-27MHz

12

11

10

9

8

1

0

AGP8X/4X: (0)-8X / (1)-4X

AGP_SIDEBAND: (0)-ENABLE

AGP_FASTWRITE: (0)-ENABLE

BUS_TYPE: (1)-AGP3

2

1

0

NV31M:NV34M

NV18M

NV31M:NV34M

NV18M

RAM_CFG[3:0]

PCI_DEVID[3:0] 0100-NV34M

High

High

High

Low

Low

Low

Low

High

(1101 = 4Mx32 DDR, DQS per byte)

ROM TYPE: (00)-PARALLEL

1

0High

Low

7

6

5

4

3

2

1

**

1010-NV31M1101-NV33M 0101-NV34M-U

LA-1911 0.2

nVIDIA NV34M (AGP BUS)

16 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

AGP_SBA1AGP_SBA2AGP_SBA3AGP_SBA4AGP_SBA5AGP_SBA6AGP_SBA7

AGP_ST2AGP_ST1AGP_ST0

AGP_AD0

NV_THERMD A

NV_THERMDC

I2CC_SDA

I2CC_SCL

NV_THERCT L#

AGP_AD1AGP_AD2AGP_AD3AGP_AD4AGP_AD5AGP_AD6AGP_AD7AGP_AD8

AGP_AD13AGP_AD14AGP_AD15AGP_AD16AGP_AD17AGP_AD18AGP_AD19AGP_AD20AGP_AD21AGP_AD22AGP_AD23AGP_AD24AGP_AD25AGP_AD26AGP_AD27AGP_AD28AGP_AD29AGP_AD30AGP_AD31

AGP_AD9AGP_AD10AGP_AD11AGP_AD12

AGP_C/BE#0

AGP_AD[0..31]

AGP_C/BE#1AGP_C/BE#2AGP_C/BE#3

AGP_SBA[0..7]

AGP_ST[0..2]

AGP_C/BE#[0..3]

XTALOUTBUFF

SPREAD_RATE

XTALSSIN

STP_AGP#AGP_BUSY#

DACB_RSET

+AGP_REF

STP_AGP#AGP_BUSY#

CRMALUMACOMPS

DACB_HSYNCDACB_VSYNC

BDACA_HSYNC

NV_THERMDCNV_THERMD A

DACA_VSYNC

DDC_CLKDDC_DATA

RG

TZOUT2-TZOUT2+

TZCLK-

TXOUT 1-TXOUT1+

TZOUT0+

TXOUT 0-

TXOUT2+TXOUT 2-

TXOUT0+

TXCLK+TXCLK-

TZOUT1-

TZOUT0-

TZOUT1+

TZCLK+

STRAP0STRAP1STRAP2STRAP3

DVO_HSYNC

VGA_GPIO0 SPREAD_RATE

VAG_GPIO6

ENVDD

NV_THERCT L#

ROMA14ROMA15

VIPD7

VIPHCT L

VIPD2

VIPD6

VIPD4VIPD5

VIPD3

DVOD9

DVOD3

DVOD8

DVOD2

DVOD9

DVOD3

DVO_HSYNC

STRAP3

STRAP1

STRAP0

STRAP2

VIPD2

VIPD6

VIPD7

DVOD8

VIPHCT L

ROMA14

ROMA15

VIPD4

DACB_VSYNC

DACB_HSYNC

DVOD2

VIPD5

VIPD3

DACA_VSYNC

DACA_HSYNC

XTALOUT

XTALIN

CLK_AGP_66M

AGP_IRDY#

AGP_STOP#

AGP_TRDY#AGP_DEVSEL#

AGP_FRAME#

AGP_PAR

PCIRST#

AGP_GNT #AGP_REQ#

PCI_PIRQA#

AGP_WBF#AGP_RBF#

AGP_SB_STBS

AGP_AD_STBS1

AGP_AD_STBS0AGP_AD_STBF0

AGP_AD_STBF1

AGP_SB_STBF

AGP_SBA0

POWER_SEL

XTALSSINXTALOUTBUFF

XTALOUT

AGP_AD_STBS1

AGP_AD_STBS0

I2CC_SDAI2CC_SCL

DACA_RSET

ENBKL

XTALIN

TXOUT 3-TXOUT3+

TZOUT3-TZOUT3+

+3VS

+3VS+3VS

+SVDD +3VS

+SVDD

+3VS

+SVDD

+3VS

+AGP_VREF

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

R304 10K_0402_5%12

R296 @10K_0402_5%12

R351 10K_0402_5%12

R294 @10K_0402_5%12

R362

@2.2K_0402_5%

12

R309 10K_0402_5%12

R322 @10K_0402_5%12

R311 10K_0402_5%12

R300 @10K_0402_5%12

C451

4.7U_0805_10V4Z

12

R591 @10K_0402_5%12

R405 220K_0402_5%1 2

R290 @10K_0402_5%12

nVIDIANV31/34

PCI/AGP

AGP4X/8X

ZV P

ORT

/ EX

T TM

DS /

GPIO / ROM

LVDS

TMDS

DAC1

SSC CLK

DAC2

U1A

NV34M_EPBGA701

AJ28AK28AH27AK27AJ27AH26AJ26AH25AH23AJ23AH22AJ22AJ21AK21AH20AJ20AG26AE24AG25AG24AF24AG23AE22AF22AE21AG20AG19AF19AE19AF18AG18AE18

AJ24AH19AF25AG22

AG12AF15AF13AE15AK18AH17AJ16AJ17AG16AK16AG15AE10

AG17AG14AJ18AJ19

AK13AJ13AK24AJ25AG21AF21

AJ11AH11AJ12AH12AJ14AH14AJ15AH15AG13AE16AE13

AK29AF16AF12AG11

AE2AD2AD1AF3AE3AD3AE7AF6AD4

Y5AC4

AJ7AJ5

AJ6AH6

H2H3C2C1D1E2D2

G5F4G4H5H4J4J5J6K4K6

M2M3

L4M4M5

P3P2

J3J2K2K1L3L2N2N1

AG2AH1AG3AJ1AH2AK1AJ3AK3AH4AK4AJ4AH5

AD5AD6AE4AJ2AK2AG6AG7B1AG1

G1G2F2F3

R2R1AF2

T 4U4AA1Y2W3V3V4U5V1W2V5W4AB2AB3W6Y6AC2AC3Y3AA2

AK10AJ10AJ9AH9AJ8

AG8

AG5AF7AF9AG10

T 2R3T 3U2V2U3P4P5

AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31

C/BE#0C/BE#1C/BE#2C/BE#3

PCICLKPCIRST#PCIREQ#PCIGNT#PCIPARPCISTOP#PCIDEVSEL#PCITRDY#PCIIRDY#PCIFRAME#PCIINTA#NC

AGPWBF#AGPRBF#AGPPIPE/ DBI_HINC/ DBI_LO

AGPSB_STB/ ADSTBFAGPSB_STB#/ ADSTBSAGPADSTB0/ ADSTBF0AGPADSTB0#/ADSTBS0AGPADSTB1/ ADSTBF1AGPADSTB1#/ADSTBS1

AGPSBA0AGPSBA1AGPSBA2AGPSBA3AGPSBA4AGPSBA5AGPSBA6AGPSBA7AGPST0AGPST1AGPST2

AGPVREFNC/AGPMBDET#AGP_BUSY#STP_AGP#

DACB_RED/CHROMADACB_GREEN/LUMADACB_BLUE/COMPOSITEDACB_HSYNCDACB_VSYNCDACB_RSETI2CB_SCLI2CB_SDASWAPRDY_BSTEREODACB_IDUMP

XTALSSINXTALOUTBUFF

XTALINXTALOUT

THERMDATHERMDCJTAG[0]JTAG[1]JTAG[2]JTAG[3]JTAG[4]

GPIO0GPIO1GPIO2GPIO3GPIO4GPIO5GPIO6GPIO7GPIO8GPIO9

FPBCLKOUT#FPBCLKOUT

VIPPCLKVIPHCTLVIPHCLK

VIPHAD0VIPHAD1

VIPD0VIPD1VIPD2VIPD3VIPD4VIPD5VIPD6VIPD7

DVOD0DVOD1DVOD2DVOD3DVOD4DVOD5DVOD6DVOD7DVOD8DVOD9

DVOD10DVOD11

DVOHSYNCDVOVSYNC

DVODEDVOCLKOUT

DVOCLKOUT#I2CC_SCLI2CC_SDABUFRST#

DVOCLKIN

STRAP0STRAP1STRAP2STRAP3

ROMA14ROMA15ROMCS#

IFPATXDO#IFPATXDO

IFPATXD1#IFPATXD1

IFPATXD2#IFPATXD2

IFPATXD3#IFPATXD3IFPATXC#

IFPATXCIFPBTXD4#

IFPBTXD4IFPBTXD5#

IFPBTXD5IFPBTXD6#

IFPBTXD6IFPBTXD7#

IFPBTXD7IFPBTXC#

IFPBTXC

DACA_REDDACA_GREEN

DACA_BLUEDACA_HSYNCDACA_VSYNC

DACA_RSET

I2CA_SCLI2CA_SDA

SWAPRDY_ADACA_IDUMP

IFPCTXD0#IFPCTXD0

IFPCTXD1#IFPCTXD1

IFPCTXD2#IFPCTXD2IFPCTXC#

IFPCTXC

R339 10K_0402_5%12

R313 10K_0402_5%12

C462

@0.1U_0402_16V4Z

1

2

R305 10K_0402_5%12

C9

22P_0402_50V8J

1

2

R302 10K_0402_5%12

C479

@10P_0402_50V8K

1 2

R360 10K_0402_5%12

R387 220K_0402_5%1 2

R284 10K_0402_5%12

R321 10K_0402_5%12

R361 10K_0402_5%1 2

R314 10K_0402_5%12

C441

0.1U_0402_10V6K

12

R352 10K_0402_5%12

U28

@ADM1032ARM_RM8

1

6

4

5

2

3

8

7

VDD1

ALERT#

THERM#

GND

D+

D-

SCLK

SDATA

R333 10K_0402_5%12

R369

@10_0402_5%

1 2

R303 @10K_0402_5%12

R35410K_0402_5%

1 2

C434

0.1U_0402_10V6K

12

C461

4.7U_0805_10V4Z

12

R3151K_0402_5%

1 2

R363 0_0402_5%12

R371 @10K_0402_5%12

R350@1K_0402_5%

1 2

R8 @2M_0402_5%1 2

R323 @10K_0402_5%12

R310

@2.2K_0402_5%

12

R297 10K_0402_5%12

R341 @10K_0402_5%12

R3191K_0402_5%1 2

R370 130_0603_1%1 2

R308

10K_0402_5%

12

R282 @10K_0402_5%12

R331 10K_0402_5%1 2

C27

22P_0402_50V8J

1

2

L30

FCM2012C-800_08051 2

R330 @10K_0402_5%12

R286 @10K_0402_5%12

R295 @10K_0402_5%12

R326 10K_0402_5%12

C5690.1U_0402_10V6K

1

2

Y1

27MHz_16PF_6P27000019

4

1

3

2

GND

IN

OUT

GND

R312 10K_0402_5%12

U27

W180-01GT_SO8

1

27

8

6

5

4

3

X1/CLK

X2FS1

FS2

VD

D

CLKOUT

SS%

GN

D

R285 10K_0402_5%12

R592 @10K_0402_5%12

R299 63.4_0603_1%1 2

R291 @10K_0402_5%12

R346

10K_0402_5%

12

R11 22_0402_5%1 2

C419

@2200P_0402_50V7K1

2

R317 10K_0402_5%12

R318 10K_0402_5%12

R601 10_0402_5%

1 2

R292 10K_0402_5%12

R283 @10K_0402_5%12

R356 10K_0402_5%1 2

R293 10K_0402_5%12

R377 10K_0402_5%12

R306 10K_0402_5%12

R367 10K_0402_5%12

R301 @10K_0402_5%12

R353 @10K_0402_5%12

AGP_C/BE#[0..3]10

AGP_AD[0..31]10

AGP_SBA[0..7]10

AGP_ST[0..2]10

CRMA22

COMPS22LUMA22

B 22DACA_HSYNC 22

R 22

DACA_VSYNC 22

G 22

DDC_CLK 22DDC_DATA 22

TXOUT 1- 22

TZCLK- 22

TXOUT0+ 22

TZOUT1+ 22

TXOUT 0- 22

TZOUT0- 22

TZCLK+ 22

TZOUT1- 22

TXOUT2+ 22TXOUT 2- 22TXOUT1+ 22

TZOUT0+ 22

TXCLK+ 22TXCLK- 22

TZOUT2+ 22TZOUT2- 22

ENVDD 22ENBKL 37

POWER_SEL 50

PCI_PIRQA#23,27

AGP_REQ#10AGP_GNT #10

PCIRST#10,22,23,26,27,29,30,33,34,37

AGP_TRDY#10AGP_DEVSEL#10

AGP_STOP#10AGP_PAR10

CLK_AGP_66M15

AGP_FRAME #10AGP_IRDY#10

AGP_RBF#10AGP_WBF#10

AGP_DBIHI10AGP_DBILO10

AGP_AD_STBF010

AGP_AD_STBF110

AGP_SB_STBF10

AGP_AD_STBS010

AGP_AD_STBS110

AGP_SB_STBS10

TXOUT 3- 22TXOUT3+ 22

TZOUT3- 22TZOUT3+ 22

Page 17: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

(10 mil)

32M VRAM-->Channel A only-->2 sets64M VRAM-->Channel A and B-->4 sets

LA-1911 0.2

nVIDIA NV34M (DDR)

17 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

NMRASA#

NMWEA#

NMCSA0#

NMDA63

NMDA48

NMDA31

NMDA25

NMDA18

NMDA11NMAA10

NMDA56

NMDA52

A_REF

NMDA55

NMDA40

NMDA36

NMDA21

NMDA17

NMAA6

NMDA60

NMDA24

NMDA57

NMDA46

NMDA44

NMDA19

NMDA10

NMCASA#

NMAA9

NMAA3

NMDA37

NMDA61

NMDA50

NMDA26

NMDA20

NMDA14NMDA13

NMDA3

NMDA32

NMDA30

NMDA16

NMAA0

NMAA5

NMDA29

NMAA2

NMDA53

NMDA45

NMDA43

NMDA41

NMDA39

NMDA33

NMDA23

NMAA8

NMDA12

NMDA0

NMDA58

NMDA49

NMDA27

NMDA8

NMDA62

NMDA35

NMAA4

NMDA59

NMDA54

NMDA15

NMDA9

NMAA1

NMDA51

NMDA47

NMDA42

NMDA38

NMDA22

NMDA5

NMDA2

NMAA7

NMDA28

NMDA6

NMAA11

NDQSA[0..7]

NDQMA[0..7]

NMDA[0..63]

NMAA[0..11]

NMA_BA0NMA_BA1

NMDB53

NMDB45

NMDB42NMDB43

NMDB26

NMDB37

NMDB54

NMDB12

NMDB63

NMDB34

NMDB32

NMDB5

NMDB14

NMDB31

NMDB4

NMDB55

NMDB60

NMDB33

NMDB29NMDB30

NMDB2

NMDB23

NMDB58

NMDB61

NMDB18

NMDB59

NMDB16

NMDB47NMDB46

NMDB24

NMDB3

NMDB11

NMDB56

NMDB20

NMDB52

NMDB35

NMDB15

NMDB10

NMDB17

NMDB57

NMDB9

NMDB22

NMDB[0..63]

NDQMB[0..7]

NMAB[0..11]

NDQSB[0..7]

NMAB0NMAB1NMAB2NMAB3NMAB4NMAB5NMAB6NMAB7NMAB8NMAB9NMAB10NMAB11

NMCLKB0

NMDB21

NMDB50NMDB51

NMDB6

NMDB48

NMDB1

NMDB27

NMDB8

NMDB40

NMDB38

NMDB41

NMDB49

NMDB13

NMDB62

NMDB25

NMDB44

NMDB0

NMDB39

NMDB7

NMDB36

NMDB28NDQSA0NDQSA1

NDQSA3NDQSA4

NDQSA6NDQSA7

NDQMA3NDQMA2NDQMA1NDQMA0

NDQMA5NDQMA4

NDQMA7NDQMA6

NDQSA2

NDQSA5

NDQMB1

NDQMB3

NDQMB0

NDQMB6NDQMB7

NDQMB2

NDQMB5NDQMB4

NDQSB1

NDQSB3NDQSB4

NDQSB6NDQSB7

NDQSB0

NDQSB2

NDQSB5

NMRASB#

NMCASB#

NMCSB0#

NMCKEB

NMWEB#

NMB_BA0NMB_BA1

NMCKEA

NMCLKA0

NMCLKA1#

NMCLKA0#

NMCLKA1 NMCLKB1#NMCLKB1

NMCLKB0#

NMCKEB

NMCKEA

NMDA1

NMDA4

NMDA7

NMDA34

NMDB19

+2.5VS

C563

0.1U_0402_10V6K

1

2

R381@120_0402_5%

12

R390@120_0402_5%

12

R389@120_0402_5%

12

R417 10K_0402_5%1 2

ME

MO

RY

INT

ER

FA

CE

A

U1B

NV34M_EPBGA701

N25N27N26M25K26K27J27H27N29M29M28L29J29J28H29G30K25J26J25G26F28F26E27D27H28G29F29E29C30C29B30A30

AJ29AJ30AH29AH30AF29AE29AD29AC28AG28AF27AE26AE28AD25AB25AB26AA25AD30AC29AB28AB29

Y29W28W29V29

AC27AB27AA27AA26W25V26V27V25

V30U28U29T28T29T27T30T26T25R27R25R30U24

L27K29G25E28AF28AD27AA30Y27

M27K30G27D30AG30AD26AA29W27

P28

P29

R28

U27

P27

N30

U21V21

N21P21

R26R29

C28

FBAD0FBAD1FBAD2FBAD3FBAD4FBAD5FBAD6FBAD7FBAD8FBAD9FBAD10FBAD11FBAD12FBAD13FBAD14FBAD15FBAD16FBAD17FBAD18FBAD19FBAD20FBAD21FBAD22FBAD23FBAD24FBAD25FBAD26FBAD27FBAD28FBAD29FBAD30FBAD31FBAD32FBAD33FBAD34FBAD35FBAD36FBAD37FBAD38FBAD39FBAD40FBAD41FBAD42FBAD43FBAD44FBAD45FBAD46FBAD47FBAD48FBAD49FBAD50FBAD51FBAD52FBAD53FBAD54FBAD55FBAD56FBAD57FBAD58FBAD59FBAD60FBAD61FBAD62FBAD63

FBAA0FBAA1FBAA2FBAA3FBAA4FBAA5FBAA6FBAA7FBAA8FBAA9

FBAA10FBAA11FBAA12

FBADQM0FBADQM1FBADQM2FBADQM3FBADQM4FBADQM5FBADQM6FBADQM7

FBADQS0FBADQS1FBADQS2FBADQS3FBADQS4FBADQS5FBADQS6FBADQS7

FBARAS#

FBACAS#

FBAWE#

FBACS0#

FBACS1#

FBACKE

FBACLK0FBACLK0#

FBACLK1FBACLK1#

FBABA0FBABA1

FB_VREF

R396

1K_0402_1%

12

R368 10K_0402_5%1 2

ME

MO

RY

IN

TE

RF

AC

EB

U1C

NV34M_EPBGA701

F13D13E13F12E10D10

D9D8

B13B12C12B11

B9C9B8A7

F10E9F9F7C6E6D5C4C8B7B6B5A3B3A2B2

B29A29B28A28B26B25B24C23E26D26E25C25E24F22E22F21A24B23C22B22B20C19B19B18D23D22D21E21F19E18D18F18

A18C17B17C16B16D16A16E16F16D15F15A15G17

D20B21F24C26C5D7B10D11

D12A10E7A4A27D24A21D19

C14

B14

C15

D17

D14

A13

K18K17

K13K14

E15B15

FBCD0FBCD1FBCD2FBCD3FBCD4FBCD5FBCD6FBCD7FBCD8FBCD9FBCD10FBCD11FBCD12FBCD13FBCD14FBCD15FBCD16FBCD17FBCD18FBCD19FBCD20FBCD21FBCD22FBCD23FBCD24FBCD25FBCD26FBCD27FBCD28FBCD29FBCD30FBCD31FBCD32FBCD33FBCD34FBCD35FBCD36FBCD37FBCD38FBCD39FBCD40FBCD41FBCD42FBCD43FBCD44FBCD45FBCD46FBCD47FBCD48FBCD49FBCD50FBCD51FBCD52FBCD53FBCD54FBCD55FBCD56FBCD57FBCD58FBCD59FBCD60FBCD61FBCD62FBCD63

FBCA0FBCA1FBCA2FBCA3FBCA4FBCA5FBCA6FBCA7FBCA8FBCA9

FBCA10FBCA11FBCA12

FBCDQM7FBCDQM6FBCDQM5FBCDQM4FBCDQM3FBCDQM2FBCDQM1FBCDQM0

FBCDQS0FBCDQS1FBCDQS2FBCDQS3FBCDQS4FBCDQS5FBCDQS6FBCDQS7

FBCRAS#

FBCCAS#

FBCWE#

FBCCS0#

FBCCS1#

FBCCKE

FBCCLK0FBCCLK0#

FBCCLK1FBCCLK1#

FBCBA0FBCBA1

R388

1K_0402_1%

12

R372@120_0402_5%

12

NMRASA# 20

NMCASA# 20

NMWEA# 20

NMCSA0# 20

NMCKEA 20

NMAA[0..11]20

NDQSA[0..7]20

NDQMA[0..7]20

NMDA[0..63]20

NMA_BA0 20NMA_BA1 20

NMDB[0..63]21

NDQMB[0..7]21

NMAB[0..11]21

NDQSB[0..7]21

NMCLKA0 20

NMCLKA1 20

NMCLKA1# 20

NMCASB# 21

NMCSB0# 21

NMWEB# 21

NMRASB# 21

NMCKEB 21

NMCLKB1# 21

NMCLKB1 21

NMB_BA0 21NMB_BA1 21

NMCLKA0# 20

NMCLKB0 21

NMCLKB0# 21

Page 18: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

NV31 use only.NV18,NV33,NV34 not use.

NV31 use only.NV18,NV33,NV34 not use.

+FB_DLLVDDNV31,NV33,NV34 use.NV18 not use.

+AGP_PLLVDDNV31,NV33,NV34 use.NV18 not use.

TESTMECLKNV31,NV33,NV34 use.NV18 not use.

FBCAL_TERM_GNDNV31 use (tie to GND).NV18,NV33,NV34 not use.

FBCAL_PUK_GNDNV31,NV33,NV34 use.NV18 not use.

FBCAL_PD_VDDQNV31,NV33,NV34 use.NV18 not use.

FBCAL_CLK_GNDNV31 use.NV18,NV33,NV34 not use.

FBCAL_TERM_GND & FBCAL_CLK_GNDNV31 use.NV18,NV33,NV34 not use.

LA-1911 0.2

nVIDIA NV34M POWER)

18 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

+PLLVDD+FB_DLLVDD

+DACA/BVDD

+IFPABPLLVDD

IFPCVPROBE

+IFPCIOVDD

+IFPCPLLVDD

DVOCAL_2

+IFPABIOVDD

+VIP/DVOVDDQ

VIPCAL_2

IFPABVPROB EIFPABRSET

DVOCAL_1

VIPCAL_1

+DVO_VREF

DACBVREF

+AGP_PLLVDD+FB_DLLVDD

+DACA/BVDD

+VIP/DVOVDDQ+IFPABIOVDD

+IFPABPLLVDD

+AGP_PLLVDD

AGPCALPD_VDDQAGPCALPU_GND

DACAVREF

+PLLVDD

+VIP/DVOVDDQ

+2.5VS+3VS

+1.5VS

+3VS

+3VS

+5VS

+3VS

+3VS

+3VS+3VS

+VGA_CORE

+3VS

+1.5VS +5VS

+2.5VS

+1.5VS

C36 0.01U_0402_16V7K

1 2

C541

0.022U_0402_16V7K

1

2

R349 @49.9_0402_1%1 2

R28949.9_0402_1% 12

L37

KC FBM-L11-201209-221LMAT_080512

R320 1K_0402_5%1 2

C454

470P_0402_50V7K

1

2

C424 0.1U_0402_10V6K1 2

R364 10K_0402_5%1 2

R347 @49.9_0402_1%12

C490

4.7U_0805_10V4Z

1

2

C476

4.7U_0805_10V4Z

1

2

C493

4.7U_0805_10V4Z

1

2

C443 0.01U_0402_16V7K

1 2

L31

KC FBM-L11-201209-221LMAT_080512

I/O

PO

WE

R

U1D

NV34M_EPBGA701

AD11AD14AD17AD20AD23AE11AE14AE17AE20AE23

L11L13L14L17L18L20N6

N11N20P11P20U11U20V11V20Y11Y13Y14Y17Y18Y20

AA17AA18

G14H6H7M6

P24U6U7

AC6AC7

AD12AD15AD19AD22AD16

N4AE9

AA13AA14AE12

F8F11F14F17F20F23G8

G11G20G23H24H25L24L25P25U25Y24Y25

AC24AC25

C27AK7

F5E4D3E3

AA4V6

U10V10

T 5T 6

Y4W5

AA3R4

P10N10

R5R6

L6L7M7

P6P7

AD8AD9AE8

AB6AB7AF4

AE5G24

AB5AB4

AH8AG9

B4B27C11C20D6D25D29E12E19F27L28M26N5W7W26Y7

Y28

AA6AC5

AF10AG29AE27

G9

AGPVDDQAGPVDDQAGPVDDQAGPVDDQAGPVDDQAGPVDDQAGPVDDQAGPVDDQAGPVDDQAGPVDDQ

VDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDD

VDD33VDD33VDD33VDD33VDD33VDD33VDD33VDD33VDD33VDD33VDD33VDD33VDD33VDD33

VD50CLAMP0VD50CLAMP1AGPCALPD_VDDQAGPCALPU_GNDAGP_PLLVDD

FBVDDQFBVDDQFBVDDQFBVDDQFBVDDQFBVDDQFBVDDQFBVDDQFBVDDQFBVDDQFBVDDQFBVDDQFBVDDQFBVDDQFBVDDQFBVDDQFBVDDQFBVDDQFBVDDQFBVDDQ

FB_DLLVDDPLLVDD

FBCAL_PD_VDDQFBCAL_PU_GND

FBCAL_TERM_GNDFBCAL_CLK_GND

IFPABVPROBEIFPABRSET

IFPABPLLVDDIFPABPLLGND

IFPAIOVDDIFPAIOGND

IFPBIOVDDIFPBIOGND

IFPCVPROBEIFPCRSET

IFPCPLLVDDIFPCPLLGND

IFPCIOVDDIFPCIOGND

VIPVDDQVIPVDDQVIPVDDQ

VIPCAL_PD_VDDQVIPCAL_PU_GND

DVOVDDQDVOVDDQDVOVDDQ

DVOCAL_PD_VDDQDVOCAL_PU_GND

DVO_VREF

TESTMODETESTMECLK

DACB_VREFDACB_VDD

DACA_VREFDACA_VDD

NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

NC

NCNCNCNCNCNC

C427

470P_0402_50V7K

1

2

R378 49.9_0402_1%12

C423 0.1U_0402_10V6K1 2

R324 1K_0402_5%1 2

C428

4700P_0402_25V7K

1

2

L24KC FBM-L11-201209-221LMAT_08051 2

C457

470P_0402_50V7K

1

2

R404 10K_0402_5%1 2

C414

4.7U_0805_10V4Z

1

2

C467

470P_0402_50V7K

1

2

C448

470P_0402_50V7K

1

2

L25

KC FBM-L11-201209-221LMAT_08051 2

R335 10K_0402_5%1 2

C41

4.7U_0805_10V4Z

C436

0.1U_0402_10V6K

1

2

C450

4700P_0402_25V7K

1

2

R3161K_0402_1%

12

C429

0.1U_0402_10V6K

1

2

L40

KC FBM-L11-201209-221LMAT_08051 2

C422

4700P_0402_25V7K

1

2R325@549_0402_1% 12

C460

0.022U_0402_16V7K

1

2

C555

470P_0402_50V7K

1

2

R28849.9_0402_1% 12

R3401K_0402_1%

12

C556

4700P_0402_25V7K

1

2

C32

4.7U_0805_10V4Z

1

2

C464

4700P_0402_25V7K

1

2

C449

4.7U_0805_10V4Z

1

2

R332 10K_0402_5%1 2

C485

4700P_0402_25V7K

1

2

R334 @49.9_0402_1%1 2

R6140_0402_5%

12

C465

470P_0402_50V7K

1

2

L4

KC FBM-L11-201209-221LMAT_08051 2

C430

4700P_0402_25V7K

1

2

R6150_0402_5%

12

C507

0.022U_0402_16V7K

1

2

R348 @49.9_0402_1%1 2

R373 49.9_0402_1%12

R287@0_0402_5% 12

C7

4.7U_0805_10V4Z

1

2

C482

0.1U_0402_16V4Z

1

2

L34

KC FBM-L11-201209-221LMAT_08051 2

C452

0.1U_0402_10V6K

1

2

Page 19: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-1911 0.2

nVIDIA NV34M (DECOUPLING CAP)

19 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

SUSP

+VGA_CORE

+VGA_CORE

+VGA_CORE

+2.5VS

+2.5VS

+3VS

+3VS

C499

0.1U_0402_10V6K

1

2

C500

4700P_0402_25V7K

1

2

C531

1U_0603_10V6K

1

2

C513

1U_0603_10V6K

1

2

C504

4.7U_0805_10V4Z

1

2

R391@470_0402_5%

12

C472

470P_0402_50V7K

1

2

C453

1U_0603_10V6K

1

2

G

D

S

Q28@2N7002

2

13

C478

4700P_0402_25V7K

1

2

C506

0.1U_0402_10V6K

1

2

C481

0.1U_0402_10V6K

1

2

C530

4.7U_0805_10V4Z

1

2

C487

0.022U_0402_16V7K

1

2

C477

1U_0603_10V6K

1

2

C447

0.022U_0402_16V7K

1

2

C483

0.1U_0402_10V6K

1

2

C552

0.022U_0402_16V7K

1

2

C456

0.1U_0402_10V6K

1

2

C517

4700P_0402_25V7K

1

2

C547

4700P_0402_25V7K

1

2

C550

0.022U_0402_16V7K

1

2

C484

470P_0402_50V7K

1

2

C522

4700P_0402_25V7K

1

2

C480

0.1U_0402_10V6K

1

2

C501

4700P_0402_25V7K

1

2

C494

0.1U_0402_10V6K

1

2

C471

470P_0402_50V7K

1

2

C515

0.1U_0402_10V6K

1

2

C540

0.1U_0402_10V6K

1

2

GR

OU

ND

U1E

NV34M_EPBGA701

A9A12A19A22A25

C3C7

C10C13C18C21C24

D4D28

E5E8

E11E14E17E20E23

F1F6

F25F30G3

G28H11H20H26

J1J7

J30K3K5

K28L5L8

L23L26M1

M30N3

N28P26

T 1U26V28W1

W30Y8

Y23Y26AA5

AA28AB1

AB30AC11AC20AC26AD28

AE1AE6

AE25AE30

AF5AF8

AF11AF14AF17AF20AF23AF26AG4

AG27AH3AH7

AH10A6

M12M13M14M15M16M17M18M19N12N13N14N15N16N17N18N19P12P13P14P15P16P17P18P19R12R13R14R15R16R17R18R19T12T13T14T15T16T17T18T19U12U13U14U15U16U17U18U19V12V13V14V15V16V17V18V19W12W13W14W15W16W17W18W19

AH13AH16AH18AH21AH24AH28AK6AK9AK12AK15AK19AK22AK25

G12G15G16G19G22J24M24

R24T24

W24AB24

A1AK30

G6R7T 7

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

T_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GNDT_GND

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

NCNCNCNCNCNCNC

NCNCNCNCNC1NC2NC3NC4NC5

C511

1U_0603_10V6K

1

2

C532

0.1U_0402_10V6K

1

2

C549

4700P_0402_25V7K

1

2

C537

1U_0603_10V6K

1

2

C473

470P_0402_50V7K

1

2

C539

0.1U_0402_10V6K

1

2

C466

0.1U_0402_10V6K

1

2

C551

0.022U_0402_16V7K

1

2

C512

1U_0603_10V6K

1

2

C475

1U_0603_10V6K

1

2

C516

0.1U_0402_10V6K

1

2

C510

4700P_0402_25V7K

1

2

C533

0.1U_0402_10V6K

1

2

C446

0.022U_0402_16V7K

1

2

C548

4700P_0402_25V7K

1

2

C437

0.1U_0402_10V6K

1

2

C524

4.7U_0805_10V4Z

1

2

C463

1U_0603_10V6K

1

2

C474

0.1U_0402_10V6K

1

2

SUSP 31,43,50

Page 20: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

(25mil) (25mil)

As close as ppossible to related pin

LA-1911 0.2

VGA DDR FOR CHANNEL A

20 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

NMRASA#

NMCKEA

NMWEA#NMCSA0#

NMCASA#

VR_VREF_2

NMCKEA

VR_VREF_1

NMCASA#

NMAA0

NMAA9

NMAA3

NMA_BA1

NMAA7

NMRASA#

NMAA11

NMAA1NMAA2

NMAA4

NMAA10

NMAA8

NMAA5

NMWEA#NMCSA0#

NMAA6

NMA_BA0

NMAA7

NMAA4

NMAA1NMAA2NMAA3

NMAA5NMAA6

NMAA10NMAA9

NMAA0

NMAA8

NMAA11

NDQMA1NDQMA2

NDQMA6NDQMA5

NDQSA2NDQSA1

NDQSA5NDQSA6

NDQMA[0..7]

NMAA[0..11]

NDQSA[0..7]

NMDA[0..63]

NMCLKA0

NMCLKA1#

NMCLKA1

NMA_BA1NMA_BA0

NMCLKA0#

NMDA46NMDA47

NMDA44NMDA45

NMDA42

NMDA43NMDA41

NMDA40

NMDA53

NMDA48NMDA50NMDA51

NMDA52NMDA54

NMDA49

NMDA55

NMDA15

NMDA13

NMDA10

NMDA12

NMDA9

NMDA8

NMDA11

NMDA14

NMDA23

NMDA16

NMDA18

NMDA22NMDA20

NMDA21

NMDA17

NMDA19

NMDA7

NMDA4NMDA0NMDA3NMDA2NMDA1

NMDA5NMDA6

NMDA30NMDA29

NMDA24

NMDA26

NMDA31

NMDA25

NMDA28NMDA27

NDQMA0NDQMA3

NDQSA0NDQSA3

NMDA56

NMDA63

NMDA59

NMDA60

NMDA62

NMDA57NMDA58

NMDA61

NMDA38

NMDA32

NMDA36

NMDA35

NMDA39NMDA37

NMDA33

NMDA34

NDQMA4NDQMA7

NDQSA4NDQSA7

+2.5VS

+2.5VS +2.5VS

+2.5VS +2.5VS

+2.5VS

C127

0.01U_0402_16V7K

1

2

C157

22U_1206_10V4Z

12

C124

0.1U_0402_10V6K

1

2

R432

1K_0402_1%

12

C155

22U_1206_10V4Z

12

C144

0.1U_0402_10V6K

1

2

C130

0.1U_0402_10V6K

1

2

R454

1K_0402_1%

12

C125

0.1U_0402_10V6K

1

2

U37

K4D263238A-GC_FBGA144

B7C6B6B5C2D3D2E2K13K12J13J12G13G12F13F12F3F2G3G2J3J2K2K3E13D13D12C13B10B9C9B8

N5N6M6N7N8M9N9

N10N11

M8L6M7N4M5

B3H12

H3B12

B2H13

H2B13

N13M13

L9M10

M2L2L3N2

N12

M11M12

D7D8E4E11L4L7L8L11

C3C5C7C8C10C12E3E12F4F11G4G11J4J11K4K11

B4

B11

D4

D5

D6

D9

D10

D11

E6

E9

F5 F10

G5

G10

H5

H10

J5 J10

K5

K10

F6 F7 F8 F9 G6

G7

G8

G9

H6

H7

H8

H9

J6 J7 J8 J9

E7E8

E10K6K7K8K9L5

L10E5

C4C11

H4H11L12L13M3M4N3

DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9

DQ10DQ11DQ12DQ13DQ14DQ15DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31

A0A1A2A3A4A5A6A7A8/APA9A10A11BA0BA1

DM0DM1DM2DM3

DQS0DQS1DQS2DQS3

VREFMCLRFU1RFU2

RAS#CAS#WE#CS#

CKE

CKCK#

VDDVDDVDDVDDVDDVDDVDDVDD

VDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

NCNCNCNCNCNCNCNCNC

C136

22U_1206_10V4Z

12

C126

0.1U_0402_10V6K

1

2

R114@120_0402_5%

C5910.1U_0402_10V6K

1

2

C135

0.1U_0402_10V6K

1

2

R458

1K_0402_1%

12

C145

0.01U_0402_16V7K

1

2

C159

0.01U_0402_16V7K

1

2

C147

0.1U_0402_10V6K

1

2

C142

0.01U_0402_16V7K

1

2

R104@120_0402_5%

C141

22U_1206_10V4Z

12

C6260.1U_0402_10V6K

1

2

C154

0.01U_0402_16V7K

1

2

C131

0.1U_0402_10V6K

1

2

U38

K4D263238A-GC_FBGA144

B7C6B6B5C2D3D2E2K13K12J13J12G13G12F13F12F3F2G3G2J3J2K2K3E13D13D12C13B10B9C9B8

N5N6M6N7N8M9N9

N10N11

M8L6M7N4M5

B3H12

H3B12

B2H13

H2B13

N13M13

L9M10

M2L2L3N2

N12

M11M12

D7D8E4E11L4L7L8L11

C3C5C7C8C10C12E3E12F4F11G4G11J4J11K4K11

B4

B11

D4

D5

D6

D9

D10

D11

E6

E9

F5 F10

G5

G10

H5

H10

J5 J10

K5

K10

F6 F7 F8 F9 G6

G7

G8

G9

H6

H7

H8

H9

J6 J7 J8 J9

E7E8

E10K6K7K8K9L5

L10E5

C4C11

H4H11L12L13M3M4N3

DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9

DQ10DQ11DQ12DQ13DQ14DQ15DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31

A0A1A2A3A4A5A6A7A8/APA9A10A11BA0BA1

DM0DM1DM2DM3

DQS0DQS1DQS2DQS3

VREFMCLRFU1RFU2

RAS#CAS#WE#CS#

CKE

CKCK#

VDDVDDVDDVDDVDDVDDVDDVDD

VDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

NCNCNCNCNCNCNCNCNC

R430

1K_0402_1%

12

C132

0.01U_0402_16V7K

1

2

NMCLKA0#17 NMCLKA1#17

NMCLKA117NMCLKA017

NMCSA0#17

NMCKEA17

NMRASA#17NMCASA#17NMWEA#17

NMAA[0..11]17

NDQMA[0..7]17

NDQSA[0..7]17

NMDA[0..63]17

NMA_BA017NMA_BA117

Page 21: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

(25mil)

As close as ppossible to related pin

(25mil)

LA-1911 0.2

VGA DDR FOR CHANNEL B

21 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

NMAB0

NMAB7

NMAB10

NMAB4NMAB5

NMAB2

NMAB6

NMAB3

NMAB1

NMAB11

NMAB8NMAB9

NMCKEB

NMWEB#

NMRASB#

NMCSB0#

NMCASB#

VR_VREF_3

NMAB5NMAB4NMAB3

NMAB0

NMAB11

NMAB6

NMAB10NMAB9NMAB8NMAB7

NMAB1NMAB2

NMCSB0#NMWEB#

NMCKEB

NMRASB#NMCASB#

VR_VREF_4

NDQMB1NDQMB2

NDQSB1NDQSB2

NDQSB6NDQSB5

NDQMB6NDQMB5

NDQMB[0..7]

NMDB[0..63]

NDQSB[0..7]

NMAB[0..11]

NMCLKB0#

NMCLKB1

NMCLKB1#

NMCLKB0

NMB_BA1NMB_BA0

NMB_BA1NMB_BA0 NMDB51

NMDB50

NMDB53

NMDB54

NMDB55NMDB52

NMDB48

NMDB9

NMDB15

NMDB13NMDB12

NMDB11NMDB10

NMDB8

NMDB14

NMDB16NMDB18

NMDB22

NMDB17NMDB19

NMDB20

NMDB21

NMDB23

NMDB42NMDB41

NMDB47NMDB46NMDB45NMDB44

NMDB43NMDB40

NMDB3NMDB2

NMDB4NMDB0

NMDB6

NMDB7

NMDB1

NMDB5

NMDB24NMDB25

NMDB31

NMDB26

NMDB28

NMDB27

NMDB29

NMDB30

NDQMB0NDQMB3

NDQSB0NDQSB3

NMDB34

NMDB39

NMDB35

NMDB37NMDB36

NMDB32NMDB33

NMDB38

NDQMB4NDQMB7

NDQSB4NDQSB7

NMDB62NMDB49

NMDB59

NMDB61

NMDB58NMDB63NMDB60

NMDB56

NMDB57

+2.5VS

+2.5VS +2.5VS

+2.5VS

+2.5VS

+2.5VS

C71

0.01U_0402_16V7K

1

2

C76

22U_1206_10V4Z

12

C65

0.01U_0402_16V7K

1

2

C74

0.1U_0402_10V6K

1

2

C5020.1U_0402_10V6K

1

2

C30

22U_1206_10V4Z

12

U34

K4D263238A-GC_FBGA144

B7C6B6B5C2D3D2E2K13K12J13J12G13G12F13F12F3F2G3G2J3J2K2K3E13D13D12C13B10B9C9B8

N5N6M6N7N8M9N9

N10N11

M8L6M7N4M5

B3H12

H3B12

B2H13

H2B13

N13M13

L9M10

M2L2L3N2

N12

M11M12

D7D8E4E11L4L7L8L11

C3C5C7C8C10C12E3E12F4F11G4G11J4J11K4K11

B4

B11

D4

D5

D6

D9

D10

D11

E6

E9

F5 F10

G5

G10

H5

H10

J5 J10

K5

K10

F6 F7 F8 F9 G6

G7

G8

G9

H6

H7

H8

H9

J6 J7 J8 J9

E7E8

E10K6K7K8K9L5

L10E5

C4C11

H4H11L12L13M3M4N3

DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9

DQ10DQ11DQ12DQ13DQ14DQ15DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31

A0A1A2A3A4A5A6A7A8/APA9A10A11BA0BA1

DM0DM1DM2DM3

DQS0DQS1DQS2DQS3

VREFMCLRFU1RFU2

RAS#CAS#WE#CS#

CKE

CKCK#

VDDVDDVDDVDDVDDVDDVDDVDD

VDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

NCNCNCNCNCNCNCNCNC

R40@120_0402_5%

C64

22U_1206_10V4Z

12

C72

0.1U_0402_10V6K

1

2

C40

0.1U_0402_10V6K

1

2

C69

0.1U_0402_10V6K

1

2

C35

0.01U_0402_16V7K

1

2

C73

0.1U_0402_10V6K

1

2

C46

22U_1206_10V4Z

1

2

R55@120_0402_5%

C42

0.1U_0402_10V6K

1

2

R382

1K_0402_1%

12

C66

0.01U_0402_16V7K

1

2

U30

K4D263238A-GC_FBGA144

B7C6B6B5C2D3D2E2K13K12J13J12G13G12F13F12F3F2G3G2J3J2K2K3E13D13D12C13B10B9C9B8

N5N6M6N7N8M9N9

N10N11

M8L6M7N4M5

B3H12

H3B12

B2H13

H2B13

N13M13

L9M10

M2L2L3N2

N12

M11M12

D7D8E4E11L4L7L8L11

C3C5C7C8C10C12E3E12F4F11G4G11J4J11K4K11

B4

B11

D4

D5

D6

D9

D10

D11

E6

E9

F5 F10

G5

G10

H5

H10

J5 J10

K5

K10

F6 F7 F8 F9 G6

G7

G8

G9

H6

H7

H8

H9

J6 J7 J8 J9

E7E8

E10K6K7K8K9L5

L10E5

C4C11

H4H11L12L13M3M4N3

DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9

DQ10DQ11DQ12DQ13DQ14DQ15DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31

A0A1A2A3A4A5A6A7A8/APA9A10A11BA0BA1

DM0DM1DM2DM3

DQS0DQS1DQS2DQS3

VREFMCLRFU1RFU2

RAS#CAS#WE#CS#

CKE

CKCK#

VDDVDDVDDVDDVDDVDDVDDVDD

VDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

SQ

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VS

S T

HV

SS

TH

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

NCNCNCNCNCNCNCNCNC

R376

1K_0402_1%

12 R402

1K_0402_1%12

R410

1K_0402_1%

12

C38

0.01U_0402_16V7K

1

2

C43

0.1U_0402_10V6K

1

2

C5530.1U_0402_10V6K

1

2

C34

0.01U_0402_16V7K

1

2

C37

0.1U_0402_10V6K

1

2

NMCLKB0#17

NMRASB#17NMCASB#17NMWEB#17NMCSB0#17

NMCKEB17

NMCLKB017 NMCLKB117

NMCLKB1#17

NDQSB[0..7]17

NMDB[0..63]17

NMAB[0..11]17

NMB_BA017NMB_BA117

NDQMB[0..7]17

Page 22: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

CRT Conn.

TV-OUT Conn.

1. Y ground2. C ground3. Y (luminance+sync)4. C (crominance)

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

CRT, TV-OUT & LVDS CONNECTORLVDS Conn.Use for B+ discharge

***

LA-1911 0.2

CRT,TV-OUT & LVDS Connector

Compal Electronics, Inc.

B

22 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

CRMA_1

CRT_B

CRT_R

DACA_HSYNC_2

CRT_VCC

DDC_DATA_1DACA_HSYNC_1

DACA_VSYNC_1

DDC_CLK_1DACA_VSYNC_2

CRT_G

LUMA_1

PID2PID1PID0

PID3

PID2PID1

PID3

PID0

IB+

DISPOFF#

DISPOFF#

ENVDD

ENVDD

+LCDVDD

+3VS

+5V+LCDVDD

+12VALW

+CRT_VCC

+CRT_VCC

+CRT_VCC

+5VS +CRT_VCC+R_CRT_VCC

+5VS+CRT_VCC +5VS +5VS

+3VS

+3VS

+3VS

B+

+3VS

+LCDVDD

B+

+3VS

R2981K_0402_5%

12

C572

@220P_0402_25V8K

L26 CHB1608B121_06031 2

22K

22K

Q31DTC124EK_SOT23

2

13

D42

@DAN217_SOT 23

2 31

U2SN74AHCT1G125GW_SOT353-5

2 4

13

5

A YOE

#G

P

C432

18P_0402_50V8K

12

D43@DAN217_SOT 23

2 31

R62810K_0402_5%

12

R327

75_0603_1%

12

R7

75_0603_1%

12

C417

330P_0402_50V7K

12

L27

FCM2012C-800_08051 2

C458

4.7U_0805_10V4Z

12

C409

15P_0402_50V8J

12

R50

200K_0402_5%

12

G

D S

Q272N7002

2

1 3

C6

220P_0402_50V8K

12

R594 @0_0402_5%1 2

C11

270P_0402_50V7K

12

R39210K_0402_5%

12

RP5

10K_8P4R_1206_5%

18273645

R39847K_0402_5%

1 2

G

D

S

Q3

SI2302DS-T1_SOT23

2

13

22K

22K

Q29DTC124EK_SOT23

2

13

R307

4.7K_0402_5%

12

G

D S

Q12N7002

2

1 3

R10

75_0603_1%

12

L2 CHB1608B121_06031 2

R329

75_0603_1%

12

L29

FCM2012C-800_08051 2

U26SN74AHCT1G125GW_SOT353-5

2 4

13

5

A YOE

#G

P

F1

FUSE_1A

21

C412

220P_0402_50V8K

12

R593 0_0402_5%1 2

C559

@220P_0402_25V8K

C54

1000P_0402_50V7K

12

R7210K_0402_5%

12

D4DAN217_SOT 23

2 31

C220.1U_0402_16V4Z

1 2

R328

75_0603_1%

12

U58

TC7SH08FU_SSOP5

1

2

3

4

5

R49

100K_0402_5%

12

G

D

S Q22N7002

2

13

C600

10U_1210_35V4Z

R627 @0_0402_5%1 2

L28

FCM2012C-800_08051 2

C578

220P_0402_50V8K

12

L1 CHB1608B121_06031 2

C806 0.1U_0402_16V4Z12

R441

100K_0402_5%

12

C413

@68P_0402_50V8K

12

D2

CH491D_SOT23

2 1

R337

4.7K_0402_5%

12

L3 CHB1608B121_06031 2

R6

4.7K_0402_5%

12

R13

4.7K_0402_5%

12

C564

@220P_0402_25V8K

JP2

ACES_85204-0700

1234567

1234567

D17RB751V_SOD323

21

C426

0.1U_0402_16V4Z

1 2

C3

100P_0402_50V8K

12

C416

330P_0402_50V7K

12

D5DAN217_SOT 23

2 31

C433

18P_0402_50V8K

12

R9

75_0603_1%1

2

C10

270P_0402_50V7K

12

C31

4.7U_0805_10V4Z

12

C6070.1U_0603_50V4Z

JP13SUYIN_7849S-15G2T-HC

611

17

1228

1339

144

1015

5

D3DAN217_SOT 23

2 31

C41522P_0402_50V8J

1 2

C418 22P_0402_50V8J1 2

L9 CHB2012U170_08051 2

R336

100K_0402_5%

12

C431

18P_0402_50V8K

12

C5

@68P_0402_50V8K

12

C411

15P_0402_50V8J

12

R39

100_0402_5%

12

C575

@220P_0402_25V8K

C410

15P_0402_50V8J

12

JP1

IPEX_20143-030E_30P

123456789101112131415161718192021222324252627282930

C2

0.1U_0402_16V4Z

12

JP14

SUYIN_030008FR004T100XU

1234

L8 CHB2012U170_08051 2

C492

0.1U_0402_16V4Z

12

LUMA16

COMPS16

CRMA16

ENVDD16

R16

G16

B16

DACA_VSYNC16

DACA_HSYNC16

DDC_DATA 16

DDC_CLK 16

BKOFF#37

TXOUT1+16

TXOUT 0-16TXOUT0+16

TXOUT 2-16TXOUT2+16

TXOUT 1-16

TXCLK-16TXCLK+16

TZOUT2+16

TZCLK+16

TZOUT2-16

TZOUT0-16

TZCLK-16

TZOUT1-16TZOUT1+16

TZOUT0+16

PID034

PID234PID134

PID334

DAC_BRIG37

INVT_PWM37

TXOUT 3-16TXOUT3+16

TZOUT3-16TZOUT3+16

PCIRST#10,16,23,26,27,29,30,33,34,37

Page 23: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

(GNTA#)DISABLE "TOP BLOCK SWAP"

Close to ICH ball <250mils

Close to ICH ball <250mils

Note:HI_SWING_MCH, HI_VREF_MCHtrace width of 10mils andspace 7mils

Close to ICH(L20)

Close to ICH(L24)

LA-1911 0.2

23 57Friday, August 08, 2003

Compal Electronics, Inc.

ICH5-PCI/HUB/LANTitle

Size Document Number Rev

Date: Sheet of

IDE_IRQ15

IDE_IRQ14

INTRUDER#

HUB_HL11

HI_SWING_ICHHI_VREF_ICHHI_RCOMP_ICH

CLK_ICH_66M

PCI_PIRQA#PCI_PIRQB#

IRQ_SERIRQ

PCI_PIRQC#PCI_PIRQD#

PCI_GNT#0PCI_GNT#1PCI_GNT#2PCI_GNT#3

CLK_PCI_ICH

PCI_SERR#

PCI_PIRQE#PCI_PIRQF#PCI_PIRQG#PCI_PIRQH#

PCI_REQ#0

PCI_REQ#2PCI_REQ#1

PIDERST#

PCI_REQ#3PCI_REQ#4

PCI_REQ#APCI_REQ#B

PCI_DEVSEL#PCI_FRAME#

PCI_TRDY#

PCI_PERR#

PCI_STOP #

PCI_PAR

PCIRST#

PCI_PLOCK#

CLK_PCI_ICH

PIDERST#

LAN_RST#

SMI#

PCI_IRDY#

PCI_AD31PCI_AD30PCI_AD29PCI_AD28PCI_AD27PCI_AD26PCI_AD25PCI_AD24PCI_AD23PCI_AD22PCI_AD21PCI_AD20PCI_AD19PCI_AD18PCI_AD17PCI_AD16PCI_AD15PCI_AD14PCI_AD13PCI_AD12PCI_AD11PCI_AD10PCI_AD9PCI_AD8PCI_AD7PCI_AD6PCI_AD5PCI_AD4PCI_AD3

NC_EE_DOUT

PCI_AD2PCI_AD1PCI_AD0 INTRUDER#

LINK_ALERT#

ICH_SMB_CLKICH_SMB_DATA

ICH_SMLINK0

ICH_SMLINK1

HI_SWING_ICH

HI_VREF_ICH

CLK_ICH_66M

PCI_AD[0..31]

IRQ_SERIRQ

ICH_SMB_CLK

HUB_HL0HUB_HL1

ICH_SMB_DATA

HUB_HL2HUB_HL3HUB_HL4

HUB_HL6HUB_HL5

HUB_HL8HUB_HL7

HUB_HL9

IDE_IRQ15

HUB_HL10

ICH_SMLINK0

IDE_IRQ14

ICH_SMLINK1LINK_ALERT#

HUB_HL[0..10]

PCI_PIRQA#PCI_PIRQC#

PCI_PIRQH#

GPI_11

GPI_11

PCI_REQ#B

PCI_REQ#2

PCI_PIRQF#

PCI_PIRQE#

PCI_REQ#0

PCI_PIRQD#PCI_STOP#

PCI_FRAME#

PCI_REQ#APCI_REQ#4

PCI_REQ#1

PCI_REQ#3

PCI_PLOCK#

PCI_PIRQG#

PCI_IRDY#

PCI_SERR#

PCI_PERR#

PCI_DEVSEL#

PCI_PIRQB#

PCI_TRDY#

+RTCVCC

+3VS

+3VS

+3VS

+3VS

+1.5VSS

+3VALW

+3VS

+1.5VSS

+3VS

+3VS

+3VS

+3VS

R507 0_0402_5% 12

RP28

8.2K_8P4R_1206_5%

1 82 73 64 5

R473@1K_0402_5%

12

R229 10K_0402_5%1 2

R486 8.2K_0402_5%

1 2

C6790.01U_0402_16V7K

1

2

R490 62_0402_5%12

R532 8.2K_0402_5%1 2

R533 8.2K_0402_5%1 2

R488 10K_0402_5%

1 2

R549 2.7K_0402_5%1 2

R544 1M_0603_5%1 2

R497

226_0603_1%

12

R547 10K_0402_5%1 2

R523 10K_0402_5%1 2

RP37

8.2K_8P4R_1206_5%

1 82 73 64 5

C683

0.1U_0402_16V4Z 1

2

R548 2.7K_0402_5%1 2

Interrupt I/F

EEPROM I/F

LAN I/F

PCI I/F

SMB I/F

CPU I/F

HUB I/F

ICH5/(ICH5-M)U14A

ICH5

J4J5G3K4H5H2J3J2K5F2M4H4L5G2K1G5G4L1B2P5H3N5C4N4E6P3D3N2F5P4F4P2

E3J1N3M2

D5C1C5B6C6

D4A3B7C7A4

N1

D2L3M3F1K2L2V2V4L4E5E4

A5E7

E8B4

Y12AD3AA2V5AD2AD1AC3

T22V23A11U24R21R23U23R22P24P23P22V24T24

H20H21J20H23M23M21N21M20L22J22K21G22

N22

K23J24

N24L24L20

B3E1A2C2D7A6E2B1Y17Y24F23

B10B11B9A12

C10C9C11D9E9B12E10D10AA1

R24

AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31

C/BE0#C/BE1#C/BE2#C/BE3#

REQ0#REQ1#REQ2#REQ3#REQ4#/GPI40

GNT0#GNT1#GNT2#GNT3#GNT4#/GPO48

PCICLK

FRAME#DEVSEL#IRDY#PARPERR#PLOCK#PME#PCIRST#SERR#STOP#TRDY#

REQA#/GPI0REQB#REQ5#/GPI1

GNTA#/GPO16GNTB#/GNT5#/GPO17

INTRUDER#SMLINK0SMLINK1

LINKALERT#SMBCLK

SMBDATASMBALERT#/GPI11

A20GATEA20M#

NCFERR#

IGNNE#INIT#INTR

NMICPUPWRGD/GPO49

RCIN#CPUSLP#

SMI#STPCLK#

HI0HI1HI2HI3HI4HI5HI6HI7HI8HI9

HI10HI11

CLK66

HI_STBFHI_STBS

HIRCOMPHIREF

HI_VSWING

PIRQA#PIRQB#PIRQC#PIRQD#

PIRQE#/GPI2PIRQF#/GPI3PIRQG#/GPI4PIRQH#/GPI5

IRQ14IRQ15

SERIRQ

EE_CSEE_DIN

EE_DOUTEE_SHCLK

LAN_RXD0LAN_RXD1LAN_RXD2LAN_TXD0LAN_TXD1LAN_TXD2

LAN_CLKLAN_RSTSYNC

LAN_RST#

NC/(DPSLP#)

R493

147_0603_1%

12

RP93

8.2K_8P4R_1206_5%

1 82 73 64 5

C684

@10P_0402_50V8K1

2

RP94

8.2K_8P4R_1206_5%

1 82 73 64 5

C674

0.1U_0402_16V4Z 1

2

R499

@10_0402_5%

12

R503 52.3_0603_1%12

RP95

8.2K_8P4R_1206_5%

1 82 73 64 5

RP30

8.2K_8P4R_1206_5%

1 82 73 64 5

R211@10_0402_5%

12

C6780.01U_0402_16V7K

1

2

R524 0_0402_5% 12

C287@10P_0402_50V8K

1

2

R53810K_0402_5%

12

R546 10K_0402_5%1 2

R495

113_0603_1%

12

HUB_HLSTRF 10HUB_HLSTRS 10

PCI_GNT#030PCI_GNT#129

PCI_GNT#326

PCI_REQ#030PCI_REQ#129

PCI_REQ#326

PCI_FRAME#26,27,29,30

PCI_PAR26,27,29,30

PCI_TRDY#26,27,29,30

PCI_DEVSEL#26,27,29,30

PCI_STOP #26,27,29,30

PCI_IRDY#26,27,29,30

PCI_PERR#26,27,29,30

PCI_SERR#26,27,29,30

CLK_PCI_ICH15

PCIRST#10,16,22,26,27,29,30,33,34,37

PCI_REQ#227

PCI_GNT#227

PIDERST#33

CLK_ICH_66M 15

GATEA20 37

H_FERR# 5

H_A20M# 5

H_IGNNE# 5

H_CPUSLP# 5

H_INIT# 5H_INTR 5H_NMI 5

H_SMI# 5H_STPCLK# 5

KBRST# 37H_PWRGOOD 5

PCI_PIRQA# 16,27PCI_PIRQB# 27PCI_PIRQC# 27PCI_PIRQD# 27

ICH_SMB_DATA 12,13,15ICH_SMB_CLK 12,13,15

PCI_AD[0..31]26,27,29,30

SERIRQ 27,34,37IDE_IRQ15 33,42

PCI_C/BE#326,27,29,30PCI_C/BE#226,27,29,30PCI_C/BE#126,27,29,30PCI_C/BE#026,27,29,30

IDE_IRQ14 33

HUB_HL[0..10]10

PCI_PIRQE# 30PCI_PIRQF# 26PCI_PIRQG# 29PCI_PIRQH# 29

Page 24: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Near ICH

ICH_SYNC# SYS_PWROK ICH_PWROK

0

1

0

0

0

0

0 01

1 1 1

Note:USBRBIAS keep less than 500mils

Disable timer timeout

Note:SATABIAS keep less than 500mils

LA-1911 0.2

24 57Friday, August 08, 2003

Compal Electronics, Inc.

ICH5-IDE/LPC/PM/GPIO/USBTitle

Size Document Number Rev

Date: Sheet of

ICH_PWROK

TP0_PU

H_THERMTRIP#

SYS_RESET#

PM_SLP_S3#PM_SLPS4#

ICH_AC_SYNC_R

ICH_AC_RST_R#

ICH_AC_SDOUT_R

ICH_AC_BITCLK

ICH_AC_SDIN0ICH_AC_SDIN1

PM_SLPS5#

ICH_RTCRST#

ICH_RTCX2

ICH_VGATE

ICH_VBIAS

SYS_RESET#

ICH_AC_BITCLK

CLK_ICH_14M

ICH_RTCX1

EC_THRM#

ICH_VGATE

H_CPUPERF#

USBRBIAS

IDE_PDIORDY

IDE_SDIORDY

IDE_SDD7IDE_SDD6

IDE_SDD11

IDE_SDD9

IDE_SDD2

IDE_SDD12

IDE_SDCS1#

IDE_SDD1

IDE_SDCS3#

IDE_SDA0

IDE_SDD10

IDE_SDD8

IDE_SDD14

IDE_SDD4

IDE_SDIORDY

IDE_SDD3

IDE_SDD13

IDE_SDD15

IDE_SDDACK#IDE_SDDREQ

IDE_SDIOW#

IDE_SDD0

IDE_SDA1IDE_SDA2

IDE_SDD5

IDE_SDIOR#

ICH_INTVRMEN

EC_SCI#EC_LID_OUT#

EC_SMI#

SPKR

H_CPUPERF#

LPC_AD[0..3]

EC_THRM#

ICH_AC_RST_R#

ICH_AC_SYNC_R

ICH_AC_SDOUT_R

ICH_AC_SDIN0

ICH_AC_BITCLK

ICH_AC_SDIN1

ICH_AC_SDOUT

SATABIAS

CLK_ICH_14M

IDE_PDD15

IDE_PDD7IDE_PDD6

IDE_PDCS3#

IDE_PDD2

IDE_PDD5

IDE_PDD3

IDE_PDIOW#

IDE_PDDREQ

IDE_PDD11IDE_PDD12

IDE_PDCS1#

IDE_PDD9

IDE_PDA1

IDE_PDD10

IDE_PDIOR#

IDE_PDD0

IDE_PDA2

IDE_PDD14

IDE_PDD8

IDE_PDD1

IDE_PDIORDY

IDE_PDA0

IDE_PDD4

IDE_PDDACK#

IDE_PDD13

ICH_INTVRMEN

ICH_ACIN

CLK_ICH_48M

SUSCLK

CLK_ICH_48M

LPC_AD2LPC_AD1LPC_AD0

LPC_AD3

LPC_FRAME#LPC_DRQ1#

USB_OC0#

IDE_PDD[0..15]

USB_OC1#USB_OC2#

TP0_PU

IDE_SDD[0..15]

SPKR

ICH_RTCRST#

USB_OC3#

ICH_PWROK

ICH_RTCX1

ICH_RTCX2

USB_OC4#USB_OC5#USB_OC6#USB_OC7#

EC_RSMRST#

EC_RSMRST#

SUSCLK

H_THERMTRIP#

ACINICH_ACIN

SIDERST#

USB_OC6#

USB_OC3#USB_OC1#

USB_OC5#USB_OC7#

PM_SLPS5#

PM_SLPS4#

PM_CLKRUN#

PM_CLKRUN#

+3VS

+CPU_CORE

+RTCVCC

+3VALW

+3VS

+CPU_CORE

+3VS

+RTCVCC

+3VS

+3VS

+3VS

+3VS

+3VALW

+3VALW

+3VALW

RP92

10K_8P4R_1206_5%

1 82 73 64 5

R5404.7K_0402_5%

12

X4

32.768KHZ_12.5PF_CM155

R482 @10K_0402_5%12

R545

200K_0402_5%

12

R470 33_0402_5% 12

R216 4.7K_0402_5%

12

R502 10K_0402_5%12

R574@220_0402_5%

12

R489

@10_0402_5%

12

R261

@220_0402_5%

12

[email protected]_0402_16V4Z

C356

12P_0402_50V8J

R534 @10K_0402_5%12

R468 @8.2K_0402_5%

12

R550 330K_0402_5%

1 2

R597 @0_0402_5%12

R572 0_0402_5%1 2

[email protected]_0402_50V8C

12

R232 10K_0402_5%12

J1JOPEN

12

R245 10M_0603_5%12

R47122.6_0603_1%

1 2

Q21@MMBT3904_SOT23

2

31

D36RB751V_SOD323

2 1

C648

@10P_0402_50V8K1

2

R527 24.9_0603_1%12

R504 0_0402_5%1 2

R543 10K_0402_5%12 R595 @0_0402_5%

1 2

R234 10K_0402_5%12

C357

12P_0402_50V8J

R254@1K_0402_5%

12

R50510K_0402_5%1 2

R529 4.7K_0402_5%

12

R554 @1K_0402_5%12

C663@10P_0402_50V8K

1

2

C350

0.1U_0402_16V4Z

1

2

R479

@10_0402_5%

12

R508 0_0402_5%1 2

U15

TC7SH08FU_SSOP5

1

2

3

4

5

R562@10M_0603_5%

12

R475 33_0402_5%

12

Q55@MMBT3904_SOT23

2

31

R509 62_0402_5%1 2

C320 0.1U_0402_16V4Z12

R566

@2.4M_0603_1%

12

R484 @10K_0402_5%12

R487@10_0402_5%

12

R222 8.2K_0402_5%

12

R480 10K_0402_5%12

R528 4.7K_0402_5%

12

R220100K_0402_5%

1 2

R485 @1K_0402_5%

12

R472 33_0402_5% 12

R559 @22M_0603_5%1 2

R481 @10K_0402_5%12

MISC

CLOCK

GPI

IDE I/F

SATA I/F

PM

IST

AC97 I/F

LPC I/F

USB I/F

GPIO

ICH5/(ICH5-M)U14B

ICH5

R5U1

AB2R1

AC1P20

Y4AC12

AB3AB13

T20W1U2

AA3U22U21

Y1AB1

T 2

F22U20R20

D8C12E12D12A13

A9B8

T 5R4R3U4U5R2T 4

C23D23A22B22C21D21A20B20C19D19A18B18C17D17A16B16

C15D15D14C14B14A14D13C13

A24B24

T 1G23F21

AD10

E24

T21

F20

F24

U3Y2W4W5W3V3W2

AA19AD19AC19AB19Y18

AC17AC18AD18AA17AA18

AB16Y13Y14AC14AA14AC15AD14AB14AD15Y15AD16AA15AC16Y16AA16AB17

W22W23W21V22V20

Y20W20Y23Y22Y21

AA22AB23AD23AD24AB21AC21AB20AC20Y19AD22AC22AA20AB22AC24AB24AA23

AA8AB8AD7AC7

AA10AB10AD9AC9

Y11Y9

AC5AD5

AA12

AC11

AB12

GPI6/(AGPBUSY#)SYS_RESET#TP0/(BATLOW#)GPO21/(C3_SAT#)GPIO24/(CLKRUN#)NC/(DPRSLPVR)PWRBTN#PWROKRI#RSMRST#GPO19/(SLP_S1#)SLP_S3#SLP_S4#SLP_S5#GPO20/(STP_CPU#)GPO18/(STP_PCI#)SUSCLKSUS_STAT#/LPCPD#THRM#

GPO23/(SSMUXSEL)GPO22/(CPUPERF#)VRMPWRGD/(VGATE)

AC_BIT_CLKAC_RST#AC_SDIN0AC_SDIN1AC_SDIN2AC_SDOUTAC_SYNC

LAD0LAD1LAD2LAD3LDRQ0#LDRQ1#/GPI41LFRAME#

USBP0PUSBP0NUSBP1PUSBP1NUSBP2PUSBP2NUSBP3PUSBP3NUSBP4PUSBP4NUSBP5PUSBP5NUSBP6PUSBP6NUSBP7PUSBP7N

OC0#OC1#OC2#OC3#OC4#/GPI9OC5#/GPI10OC6#/GPI14OC7#/GPI15

USBRBIASUSBRBIAS#

GPIO32GPIO33GPIO34

INTVRMEN

SPKR

THRMTRIP#

CLK14

CLK48

GPI7GPI8

GPI12GPI13

GPIO25GPIO27GPIO28

PDA0PDA1PDA2

PDCS1#PDCS3#

PDDREQPDDACK#

PDIOR#PDIOW#PIORDY

PDD0PDD1PDD2PDD3PDD4PDD5PDD6PDD7PDD8PDD9

PDD10PDD11PDD12PDD13PDD14PDD15

SDA0SDA1SDA2

SDCS1#SDCS3#

SDDREQSDDACK#

SDIOR#SDIOW#SIORDY

SDD0SDD1SDD2SDD3SDD4SDD5SDD6SDD7SDD8SDD9

SDD10SDD11SDD12SDD13SDD14SDD15

SATA0TXPSATA0TXNSATA0RXNSATA0RXP

SATA1TXPSATA1TXNSATA1RXNSATA1RXP

SATARBIASSATARBIAS#

CLK100PCLK100N

RTCRST#

RTCX1

RTCX2

R519 @10K_0402_5%12

R598@0_0402_5%12

SUSCLK27

SYS_PWROK7,27,40

ICH_AC_BITCLK31,36

ICH_AC_SDIN031ICH_AC_SDIN136

PM_SLP_S3#37

IDE_SDA1 33,42IDE_SDA2 33,42

IDE_SDDREQ 33,42

IDE_SDCS3# 33,42

IDE_SDDACK# 33,42

IDE_SDIORDY 33,42

IDE_SDCS1# 33,42

IDE_SDIOR# 33,42

IDE_SDA0 33,42

IDE_SDIOW# 33,42

EC_LID_OUT# 37EC_FLASH# 38

LPC_AD[0..3]34,37

ICH_AC_SYNC31,36

ICH_AC_SDOUT31,36

ICH_AC_RST#31,36

EC_THRM#37

CLK_ICH_14M15

EC_SMI# 37EC_SCI# 37

CLK_ICH_48M15

LPC_FRAME#34,37LPC_DRQ1#34

IDE_PDDREQ 33

IDE_PDIORDY 33

IDE_PDCS3# 33

IDE_PDA2 33IDE_PDA1 33

IDE_PDCS1# 33

IDE_PDA0 33

IDE_PDIOR# 33IDE_PDDACK# 33

IDE_PDIOW# 33

IDE_PDD[0..15] 33

IDE_SDD[0..15] 33,42

EC_RSMRST#37,41

SPKR32

EC_SWI#37

USB_OC0#35

USB_OC2#35

PBTN_OUT#37

USB_OC4#35

USBP0+35USBP0-35

USBP2+35USBP2-35

USBP4+35USBP4-35

USBP6+36USBP6-36

PM_SLP_S5# 37

H_THERMTRIP#5

ACIN 37,38,45

SIDERST#33,42

PM_CLKRUN#26,27,29,30,34,37

VCORE_PWRGD40,49,52

Page 25: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Place0.1u near +1.5VS, Direction to ballG24,H24,K24,M24,AD4 and AD18; 0.01u near +1.5VS, Direction to ball AD8.

Place near ball AD6

Decoupling Reference Document:Springdale Chipset Platform Design guide Rev1.2(12837)page282

Place0.1u near +3VALW, Direction to ball A17,A23,V1.Addition cap near A15,A19

Place near AB4, Direction to ball (VSS)AD4

Place near ball AD11

Place nearball T22

Place near ball D24

Place near +3VS, DIRECTION TO ball D1,A7,H1,P1,W24 and A21

Place near ball A8

Place near ball(VSS) E16

Place nearF19,Direction to ball (VSS)A19

Place near F7, Direction to ball (VSS)A7

LA-1911 0.2

25 57Friday, August 08, 2003

Compal Electronics, Inc.

ICH5 Power & DecouplingTitle

Size Document Number Rev

Date: Sheet of

ICH_V5REF_SUS

VCCSUS15_B

ICH_V5REF

VCCSUS15_A

VCCSUS15_C

ICH_V5REF_SUS

ICH_V5REF

+1.5VSS

+1.5VSS

+3VS

+1.5VSS

+3VALW

+CPU_CORE

+RTCVCC

+3VALW

+CPU_CORE

+1.5VSS

+1.5VSS

+3VS

+3VS +5VS

+3VALW +5VALW

C722

0.01U_0402_16V7K

1

2

C710

1U_0603_10V6K

1

2

C733

0.01U_0402_16V7K

1

2

C739

0.1U_0402_10V6K

1

2

C660

0.1U_0402_16V4Z

1

2

C666

0.1U_0402_16V4Z

1

2

C727

0.1U_0402_16V4Z

1

2

C686

1U_0603_10V6K

1

2

GND

Power

ICH5/(ICH5-M)U14C

ICH5

A1A7

A10A15A17A19A21A23AA5AA7AA9

AA11AA13AA21AA24

AB5AB7AB9

AB11AB15AB18

AC2AC4AC6AC8

AC10AC13AC23

AD4AD6AD8

AD17AD21AD12

B13B17B19B21B23

C3C8

C16C18C20C22

D1D6

D11D16D18D20D22D24E17E19E20E21E23

F3F9G6

G20G24

H1H19H22

J6J21J23K3

K11K14K20K22K24L10L11L12L13L14L15L21L23M1M5

M11M12M13M14M22M24N11N12N13N14N20

P1P10P11P12P13

B5F6G1H6K6L6M10N10P6R13V19W15W17W24AD13AD20G19G21

E18B15E11F10F11E13E14U6V6F16F17F18K15

K10K12K13L19P19R10R6H24J19K19M15N15N23E15F15F14W19R12W9W10W11W6W7W8E22

F19Y5AA4AB4F7F8

A8W14

E16

R15R19T19

AA6AB6

C24

AD11

P14P15P21R11R14T23T 3T 6U19V1V21W16W18Y3Y6Y7Y8Y10

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3

VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3

VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5

VCCSUS1_5_AVCCSUS1_5_BVCCSUS1_5_BVCCSUS1_5_BVCCSUS1_5_CVCCSUS1_5_C

V5REFV5REF

V5REF_SUS

V_CPU_IOV_CPU_IOV_CPU_IO

VCCSATAPLLVCCSATAPLL

VCCUSBPLL

VCCRTC

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

D39RB751V_SOD323

21

R521

1K_0402_5%

12

C668

0.1U_0402_16V4Z

1

2

C728

0.01U_0402_16V7K

1

2

C717

0.1U_0402_16V4Z

1

2

C642

0.1U_0402_16V4Z

1

2

C698

0.1U_0402_16V4Z

1

2

C680

0.1U_0402_16V4Z

1

2

C665

0.01U_0402_16V7K

1

2

C676

0.1U_0402_16V4Z

1

2

C712

0.1U_0402_16V4Z

1

2

C650

0.1U_0402_16V4Z

1

2

C661

0.1U_0402_16V4Z

1

2

C672

0.1U_0402_16V4Z

1

2

C645

0.1U_0402_16V4Z

1

2

C664

0.01U_0402_16V7K

1

2

C675

0.1U_0402_16V4Z

1

2

C651

0.01U_0402_16V7K

1

2C718

0.1U_0402_16V4Z

1

2

C670

1U_0603_10V6K

1

2

C644

0.01U_0402_16V7K

1

2

C667

0.1U_0402_16V4Z

1

2

C708

0.1U_0402_16V4Z

1

2

C737

0.1U_0402_16V4Z

1

2

R491

1K_0402_5%

12

C420

0.1U_0402_16V4Z

1

2

C738

0.1U_0402_16V4Z

1

2

C732

0.1U_0402_16V4Z

1

2

D37RB751V_SOD323

21

Page 26: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Layout NoteTS6121 pls close toconn.

Termination plane should be coupled to chassis ground

IDSEL:PCI_AD17

T RACE=20mil

T RACE=20mil

T RACE=20mil

T RACE=20mil TRACE=30mil

P l ace closed to R T L8101L pin58

TRACE=20mil

R T L 8 101L has internal+ 2 . 5 V generator at pin58

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

reserve transistor for ver.C

LAN Realtek RT8101L

Closed to RTL8101L Closed to Bothhand TS6121

** **

**

**

LA-1911 0.2

LAN REALTEK RTL8101L

26 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

PCI_C/BE#1PCI_C/BE#0

PCI_C/BE#3

PCI_AD17 LAN_IDSEL

+3V_LAN_VDD1

+3V_LAN_VDD2

LAN_X1 LAN_X2

CLK_PCI_LAN

PCI_C/BE#2

+2.5V_LAN

+3V_LAN_VDD3

RJ45_RX-

RJ45_RX+

RJ45_TX-

RJ45_TX+

PCI_AD[0..31]

PCI_AD0PCI_AD1PCI_AD2PCI_AD3PCI_AD4PCI_AD5PCI_AD6PCI_AD7PCI_AD8PCI_AD9PCI_AD10PCI_AD11PCI_AD12PCI_AD13PCI_AD14PCI_AD15PCI_AD16PCI_AD17PCI_AD18PCI_AD19PCI_AD20PCI_AD21PCI_AD22PCI_AD23PCI_AD24PCI_AD25PCI_AD26PCI_AD27

PCI_AD31PCI_AD30PCI_AD29PCI_AD28

LINK10_100#

RJ45_PR

LAN_X2

LAN_TD+LAN_TD-

LAN_RD+LAN_RD-

LINK10_100#ACTIVITY#

LAN_EECLKLAN_EEDILAN_EEDO

LAN_EECS

CLK_PCI_LAN

+2.5V_DLAN

ACTIVITY#

LAN_RD-LAN_RD+

LAN_TD-LAN_TD+

RJ45_RX+

RJ45_TX+RJ45_TX-

RJ45_RX-

RJ45_PR

LAN_X1

LANGND

+3V

+3V

+3V

+3V

+2.5V_LAN

+3VS

+3V

+3V

+2.5V_LAN

+3V

+2.5V_LAN

+3V

C49

0.1U_0402_16V4Z

12

C7884.7U_0805_10V4Z

R37949.9_0402_1%

12

47K

10KC

BE

Q32@2SB1197K_SOT23

2

31

C577@10P_0402_50V8K

12

C505

0.1U_0402_16V4Z

12

C538

0.1U_0402_16V4Z

12

R412 300_0402_5%1 2

U32

AT93C46-10SI-2.7_SO8

1234

8765

CSSKDIDO

VCCNCNC

GND

C573

0.1U_0402_16V4Z

12

C567

0.1U_0402_16V4Z

U31

TS6121C_16P

132

768 9

1110

151416

TD+TD-CT

CTRD+RD- RX-

RX+CT

CTTX-

TX+

R38049.9_0402_1%

12

R423 100_0402_5%1 2

L36LQG21N4R7K10_0805

1 2

47K

10K

C

BE

Q34DTA114YKA_SOT23

2

3 1

R47 5.6K_0603_1%1 2

R401 300_0402_5%1 2

PCI

I/F

Power

Powe

rLA

N I/

FAC

-Lin

k

U35

RTL8101L_LQFP100

4746454342

16

414039363534333230292815141312111098

9693929189878685

84

98

69

17

181920

2

2123

2526

24

2738

628844

1

55545352

31

74

65

64

63

73

57

66

787776

61

60

80

8197

8283

7271

6867

62237499095

4894

3457

79

10099

50

51

56

58

59

70

75

AD0AD1AD2AD3AD4

DGND2

AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31

C/BE#3

IDSEL

NC

C/BE#2

FRAME#IRDY#TRDY#

DGND1

DEVSEL#STOP#

PERR#SERR#

PAR

C/BE#1C/BE#0

AGND1DGND5DGND4

AC_RST#

EECSEESKEEDI

EEDO

DGND3

ISOLATE#

RTSET

LWAKE

RTT3

AGND3

PME#

AGND2

LED0LED1LED2

X1

X2

INTA#

RST#PCICLK

GNT#REQ#

TXD+TXD-

RXIN+RXIN-

VDDVDDVDDVDDVDDVDD

VDD25VDD25

AC_SYNCAC_DOUT

AC_DINAC_BCK

INTB#

GPIO0GPIO1

CLKRUN#

ROMCS/OEB

VCTRL

AVDD25

AVDD

AVDD

AVDD

C49727P_0402_50V8J

12

R2275_0402_5%

12

JP16

AMP RJ45/RJ11 with LED

2

1

3

4

5

6

7

8

9

10

11

12

13

14

16

15

PR1-

PR1+

PR2+

PR3+

PR3-

PR2-

PR4+

PR4-

Green LED+

Green LED-

Amber LED-

Amber LED+

SHLD1

SHLD2

SHLD4

SHLD3

C576

0.1U_0402_16V4Z

C486

22U_1206_10V4Z

1

2

R421@10_0402_5%

12

R3835.6K_0402_5%

1 2

R39449.9_0402_1%

12

C528

0.1U_0402_16V4Z

12

C498

0.1U_0402_16V4Z

12

R46 15K_0402_5%1 2

R2175_0402_5%

12

Y225MHZ_20PF_6X25000017

R2375_0402_5%

12

C526

0.1U_0402_16V4Z

C495

0.1U_0402_16V4Z

12

C580

0.1U_0402_16V4Z

R39549.9_0402_1%

12

R375 0_0805_5%

C581

0.1U_0402_16V4Z

C459

0.1U_0402_16V4Z

12

C566

0.1U_0402_16V4Z

C50327P_0402_50V8J

12

C488

0.1U_0402_16V4Z

12

R2475_0402_5%

12

C438

@0.1U_0402_16V4Z1

2

C45

@22U_1206_10V4Z

12

R48 1K_0402_5%1 2

C787

1000P_1206_2KV7K

1 2

C496

0.1U_0402_16V4Z

12

47K

10K

C

BE

Q33DTA114YKA_SOT23

2

3 1

PCI_REQ#323PCI_GNT#323

LAN_PME#27,29,30,37

PCIRST#10,16,22,23,27,29,30,33,34,37

PCI_PIRQF#23

PCI_AD[0..31]23,27,29,30

PCI_C/BE#023,27,29,30PCI_C/BE#123,27,29,30PCI_C/BE#223,27,29,30PCI_C/BE#323,27,29,30

PCI_PAR23,27,29,30PCI_FRAME#23,27,29,30

PCI_TRDY#23,27,29,30PCI_DEVSEL#23,27,29,30

PCI_STOP#23,27,29,30

PCI_PERR#23,27,29,30PCI_SERR#23,27,29,30

PCI_IRDY#23,27,29,30

CLK_PCI_LAN15PM_CLKRUN#24,27,29,30,34,37

Page 27: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

CardBus Controller T7L65XB (BGA) PCI/SD INTERFACE

UNUSED PIN PULL UP/DOWN

CardBus Controller T7L65XB (BGA) CARDBUS INTERACE

PC CARD PULL-UP REQUIREMENTBASE ON 16-BIT PC-CARD STANDARD R7ELECTRICAL SPECIFICATION

FUZZY SIGNALRESERVEDPULL UP/DOWN

**

**

** **

**

***

LA-1911 0.2

CardBus Controller<T7L65XB>

Custom

27 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

PCI_AD[0..31]

S1_A[0..25]

S1_D[0..15]

PCI_AD2

PCI_AD7

PCI_AD16

PCI_AD23

PCI_AD20

PCI_AD27

PCI_AD6

PCI_AD17

PCI_AD11PCI_AD12

PCI_AD9

PCI_AD3

PCI_AD29

PCI_AD8

PCI_AD26

PCI_AD31

PCI_AD14

PCI_AD5

PCI_AD22

PCI_AD30

PCI_AD0

PCI_AD21

PCI_AD1

PCI_AD28

PCI_AD15

PCI_AD10

PCI_AD19

PCI_AD13

PCI_AD4

PCI_AD25PCI_AD24

PCI_AD18

PCIRST#

SCV5ENSCV3EN

SCDAT

BIOSWP#

QSWON

HDSTSHDSTP

GPSTSO#

FDVCE#

HDSTS

SCV3EN

TOPICREG

PCI_AD20

PCI_AD22

S1_D6

S1_A19

S1_CD2#

S1_D10

S1_VS2

S1_D4

S1_A9

S1_A0

S1_A4

S1_RST

S1_WP

S1_A20

S1_A5

S1_D9

S1_WAIT#

S1_D15

S1_D5

S1_A8

S1_D13

S1_D1

S1_RDY#

S1_A17

S1_A6

S1_A21

S1_A2

S1_VS1

S1_CD1#

S1_A23

S1_A12

S1_D8

S1_D14

S1_A15

S1_A3

S1_D12

S1_D3

S1_A25

S1_A18

S1_INPACK#

S1_BVD1

S1_A16

S1_A10

S1_D2

S1_D7

S1_A22

S1_A1

S1_BVD2

S1_D11

S1_D0

S1_A24

S1_A14S1_A13

S1_A11

S1_A7

SD_CLK1

GPSTSO#BIOSWP#

FDVCE#

HDSTP

QSWONSCDAT

SCV5EN

SUSPEND#

EXSMI#

EXSMI#

TOPICREG

TOPICREG

PCLR#PCIRST#

PCLR#

PCI_AD21

+3VC

+3VC

+S1_VCC

+3VC

+3VC

+3VC

+3VS

+3VALW +3VALW

+3VC

+3VC

+3VS

+3V

+3VC

+S1_VCC

+3VC

J2

PAD-OPEN 4x4m

1 2

PCI BUS INTERFACE

DOCKING

I/F

EXT

I/F

GENERAL

PORT

TEST

DEBUG

PORT

SMARTCARD

I/F

SD CARD

I/F

EC/KBCI/F

SYSTEM I/F

PC CARD

PS I/F

DEEPER

SLEEP

CNT I/F

CLOCKINPUT

TOSHIBA T7L65XB 1/2

U5A

T7L65XB_BGA256

J16J15J14J13K16K15K14K13L16L15L14L13

M15M14M13N16N15N14P16P15P14R14P13R13T13N12P12R12T12N11P11R11

T8

R2

L12

K12

T11

H13

N9P9R9T9N8P8

N10P10R10T10

M8M9

M10M11

R8M12

R15T14T15

K1

B2B1

T3R1R3P3T2

N6

C1

C2

F2

F4

G4

G5

C4

D4

G2E4G3

H1H2

H16G12H14H15

B4A2

A5B5

A3B3C5A4

H5F3F1

C3D1T6P6R6M7

R7P7T7N7

K3E1E2J4J3H3H4D2D3E3G1

P5N5P4N4

T5R5T4R4

J2J1

L1L2K2M1M2N1N2P2P1L4L3

M3K4M4N3

AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31

IRQDT#

CK32K

REQ#

GNT#

CLKRUN#

PCIRST#

FRAME#IRDY#DEVSEL#TRDY#STOP#PAR

C/BE#0C/BE#1C/BE#2C/BE#3

INTA#INTB#INTC#INTD#

SERR#PERR#

IDSELFLIDSELVIIDSELSD

PCICLK

CK48MCK14M

ECSMIKBSMIECBEEP#ECNMIPCLR#

TOPICREG

DBGRX

DBGTX

SCDAT

SCCD#

SCRST#

SCCLK

SDCMD

SDCKSL

GCPSTP#DPSLP

DPRSVR

CPUSTP#VRCHG#

VPEN0AVPEN1AVC3ENAVC5ENA

SDCLKSDPWR

SDWPSDCD#

SDCD3SDCD2SDCD1SDCD0

SCVPENSCV3ENSCV5EN

SDLEDZVAENTSTO3TSTO2TSTO1TSTO0

TSTI3TSTI2TSTI1TSTI0

GPO1PDNVGA

RSTVGA#QSWON

DCPCLR#IDERSTA#IDERSTB#LCDENA#LCDENB#CRTEN#

BIOSWP#

IFMO#FDVCE#HDSTPHDSTS

MBSTS2MBSTS1MBSTS0

IFAMON#

DPSMI#PCM2SPK#

SUSPEND#SYSGSPKPSBEEP#PNL0PNL1PNL2PNL3VGAMODFCMODEXSMI#PME#AUDIOALARMATBEEPGPSTSO#

R113

100K_0402_5%

12

R93

100K_0402_5%

12

R115100K_0402_5%

12

R6100_0402_5%

1 2

PJP12

PAD-OPEN 4x4m

1 2

U55F

SN74LVC14APWLE_TSSOP14

1213

14

7

OI

PG

R608

@1K_0402_5%12

R616

0_0402_5%1 2

R120100K_0402_5%

12

R443 @10_0402_5%1 2

U55E

SN74LVC14APWLE_TSSOP14

1011

14

7

OI

PG

R71 @100_0402_5%1 2

R119100K_0402_5%

12

C611 @10P_0402_50V8K

C785 @0.1U_0402_10V6K

12

R609

@0_0402_5%1 2

R111100K_0402_5%

12

R760_0402_5%

1 2

PC CARD I/F SLOTAVOLTAGE/GROUND

NCTOSHIBA T7L65XB 2/2

U5B

T7L65XB_BGA256

F12F16F14E16E14

D16

D13

C12

A12

D7B6D6

D5

G14

F15F13E15E13D15

E12

G13

C15A15

G15

B9

E9

C8

A7C7

A6C6E6

G16

A8

H6J6K6L6L7L8L9

L10L11N13M16K11J11H11G11

G6

F5H7J7J8K7L5T1M6K8K9J9

K10T16J10H10H12H9

G10A16E11G9G8H8G7E5A1

J5K5M5

B7D8B8E8A9C9D9B10B14C14D14C16D10C13A13B11B15A14B13D12B12D11C11A11C10A10

R16J12B16E7

E10

F11F10F9F8F7F6

SLTA2/D3/CAD0SLTA3/D4/CAD1SLTA4/D5/CAD3SLTA5/D6/CAD5SLTA6/D7/CAD7

SLTA7/CE#1/CCBE#0

SLTA9/OE#/CAD11

SLTA15/WE#/CGNT#

SLTA16/BSY#/CINT#

SLTA30/D0/CAD27SLTA31/D1/CAD29

SLTA32/D2/RESERVED

SLTA33/WP#/CCLKRUN#

SLTA36/CD#1/CCD#1

SLTA37/D11/CAD2SLTA38/D12/CAD4SLTA39/D13/CAD6

SLTA40/D14/RESERVEDSLTA41/D15/CAD8

SLTA42/CE#2/CAD10

SLTA43/VS1/CVS1

SLTA44/IORD#/CAD13SLTA45/IOWR#/CAD15

SLTA57/VS2/CVS2

SLTA58/RESET/CRST#

SLTA59/WAIT#/CSERR#

SLTA61/REG#/CCBE#3

SLTA62/BVD2/CAUDIOSLTA63/BVD1/CSTSCHG

SLTA64/D8/CAD28SLTA65/D9/CAD30

SLTA66/D10/CAD31

SLTA67/CD#2/CCD#2

SLTA60/INPACK#/CREQ#

VCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCC

VCCS

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

NCNCNC

SLTA29/A0/CAD26SLTA28/A1/CAD25SLTA27/A2/CAD24SLTA26/A3/CAD23SLTA25/A4/CAD22SLTA24/A5/CAD21SLTA23/A6/CAD20SLTA22/A7/CAD18

SLTA12/A8/CCBE#1SLTA11/A9/CAD14SLTA8/A10/CAD9

SLTA10/A11/CAD12SLTA21/A12/CCBE#2

SLTA13/A13/CPARSLTA14/A14/CPERR#SLTA20/A15/CIRDY#

SLTA19/A16/CCLKSLTA46/A17/CAD16

SLTA47/A18/RESERVEDSLTA48/A19/CBLOCK#SLTA49/A20/CSTOP#

SLTA50/A21/CDEVSEL#SLTA53/A22/CTRDY#

SLTA54/A23/CFRAME#SLTA55/A24/CAD17SLTA56/A25/CAD19

VIOVIOVIOVIOVIO

VCCAVCCAVCCAVCCAVCCAVCCA

R635 100_0402_5%1 2

R448 22_0402_5%1 2

R73@100K_0402_5%

12

R102@10K_0402_5%

12

R96100K_0402_5%

12

R69100_0402_5%1 2

R88100K_0402_5%

12

R101

100K_0402_5%

12

R105@10K_0402_5%1 2

R770_0402_5%

12

S1_D[0..15] 28

S1_A[0..25] 28

PCI_DEVSEL#23,26,29,30PCI_TRDY#23,26,29,30

PCI_FRAME#23,26,29,30

PCI_STOP#23,26,29,30

PCI_GNT#223

PCI_SERR#23,26,29,30

CLK_PCI_CB15

PCI_PAR23,26,29,30

PCI_IRDY#23,26,29,30

PCI_PERR#23,26,29,30

PCI_C/BE#123,26,29,30

PCIRST#10,16,22,23,26,29,30,33,34,37

PCI_C/BE#323,26,29,30PCI_C/BE#223,26,29,30

PCI_C/BE#023,26,29,30

PCI_AD[0..31]23,26,29,30

PM_CLKRUN#24,26,29,30,34,37

PCI_PIRQB#23PCI_PIRQA#16,23

SERIRQ23,34,37

PCI_PIRQC#23PCI_PIRQD#23

SUSCLK24

PCM_PME#26,29,30,37

VPEN0A 28VPEN1A 28VC3ENA 28VC5ENA 28

SD_PWREN 28

SD_DAT2 28SD_DAT1 28SD_DAT0 28

SD_CMD 28

SD_CLK 28

SD_DAT3 28

SD_WP 28MMC_DET#28

PCM_SPK#32

PCI_REQ#223

S1_CD2# 28

S1_CE2# 28

S1_BVD1 28

S1_CD1# 28

S1_OE# 28

S1_INPACK# 28

S1_VS2 28

S1_BVD2 28

S1_IOWR# 28

S1_RDY# 28

S1_RST 28

S1_VS1 28

S1_REG# 28

S1_CE1# 28

S1_IORD# 28S1_WE# 28

S1_WP 28S1_WAIT#28

SYS_PWROK7,24,40

SDLED 39

Page 28: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

PCMCIA POWER CTRL.

W = 40mils

W = 40mils

W =30mils

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

CARDBUS SOCKET

SLOT 1 VCC DECOUPLING SLOT 1 VPP DECOUPLING +3V DECOUPLING

SD SOCKET POWER SWITCHPIN PULL DOWN

**

****

LA-1911 0.2

PCMCIA/SD SOCKET

Custom

28 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

S1_A[0..25]

S1_D[0..15]

VPEN0AVC5ENAVC3ENA

VPEN1A

SD_PWREN

VPEN1A

VC3ENAVC5ENAVPEN0A

SD_PWREN

S1_D3S1_D4S1_D5S1_D6S1_D7S1_CE1#S1_A10S1_OE#S1_A11S1_A9S1_A8S1_A13S1_A14S1_WE#S1_RDY#

S1_A16S1_A15S1_A12S1_A7S1_A6S1_A5S1_A4S1_A3S1_A2S1_A1S1_A0S1_D0S1_D1S1_D2S1_WP S1_CD2#

S1_CD1#S1_D11S1_D12S1_D13S1_D14S1_D15S1_CE2#S1_VS1S1_IORD#S1_IOWR#S1_A17S1_A18S1_A19S1_A20S1_A21

S1_A22S1_A23S1_A24S1_A25S1_VS2S1_RSTS1_WAIT#S1_INPACK#S1_REG#S1_BVD2S1_BVD1S1_D8S1_D9S1_D10

+5V

+S1_VCC

+SD3_VCC

+S1_VPP

+S1_VPP

+S1_VCC

+3V

+3VC

+SD3_VCC +3VC

+3V

+3VC

+S1_VCC

+5V

+3V

+S1_VPP+S1_VCC

+S1_VPP+S1_VCC

C104

4.7U_0805_10V4Z

C2450.1U_0402_16V4Z

C2930.1U_0402_16V4Z

C799 1U_0603_10V4Z1 2

C2260.1U_0402_16V4Z

C798 0.1U_0402_16V4Z1 2

C259

10U_1206_10V4Z

C610

0.01U_0402_16V7K

1

2

R517

@15_0402_5%

1 2

C596

0.1U_0402_16V4Z

1

2

R14747K_0402_5%1 2

C2280.1U_0402_16V4Z

RP25

47K_0804_8P4R_5%

1 82 73 64 5

C707

@15P_0402_50V8J

1 2

C592

0.01U_0402_16V7K

1

2

RP110

10K_0804_8P4R_5%

18

27

36

45

JP3

SD_SOCKET

12345678

9

11 1012

13

DAT3CMDVss1VddSDCLKVss2DAT0DAT1

DAT2

Wr_Pt Wr_Pt_VssVSS

MMC_DET#

C609

0.1U_0402_16V4Z

1

2

C599

0.01U_0402_16V7K

1

2

C1801U_0805_25V4Z

C2060.1U_0402_16V4Z

C195

0.1U_0402_16V4Z

C2654.7U_0805_10V4Z

JP26

FOXCONN_1CA415M1-TA_68P

13579

11131517192123252729313335373941434547495153555759616365676971737577798183

24681012141618202224262830323436384042444648505254565860626466687072747678808284

135791113151719212325272931333537394143454749515355575961636567GNDGNDGNDGNDGNDGNDGNDGND

2468

101214161820222426283032343638404244464850525456586062646668

GNDGNDGNDGNDGNDGNDGNDGND

R50010K_0402_5%

12

C797 0.1U_0402_16V4Z1 2

C307

0.01U_0402_25V4Z

C308

0.1U_0402_16V4Z

C601

0.1U_0402_16V4Z

1

2

C602

0.01U_0402_16V7K

1

2

R21710K_0402_5%

12

C2970.1U_0402_16V4Z

C1814.7U_0805_10V4Z

Slot BPowerSupply

Slot APowerSupply

U10

MIC2563A-0BSM_SSOP28

1

2

3

4

56

78

910

11

121314

15 1617

18

1920

2122

2324

25

2628

27

AVCC5IN

AVCCOUT

AVCC5IN

GND

AVCC5_ENAVCC3_EN

AEN0AEN1

BVPPINBVPPOUT

NC0

BVCCOUTBVCC3INBVCCOUT

BVCC5IN BVCCOUTBVCC5IN

GND

BVCC5_ENBVCC3_EN

BEN0BEN1

AVPPINAVPPOUT

NC1

AVCCOUTAVCCOUT

AVCC3IN

C615

0.01U_0402_16V7K

1

2

C597

0.01U_0402_16V7K

1

2

R461@10K_0402_5%

12

C1880.1U_0402_16V4Z

C1990.1U_0402_16V4Z C613

0.01U_0402_16V7K

1

2

C203

1000P_0402_50V7K

C2360.1U_0402_16V4Z

S1_D[0..15]27

S1_A[0..25]27

SD_PWREN27

VC5ENA27VC3ENA27

VPEN0A27VPEN1A27

SD_CLK27

SD_DAT127SD_DAT027

SD_CMD27SD_DAT327

SD_DAT227

SD_WP27

MMC_DET#27

S1_RDY#27S1_WE#27

S1_CE1#27

S1_OE#27

S1_WP27

S1_VS1 27

S1_IOWR# 27

S1_VS2 27S1_RST 27S1_WAIT# 27

S1_REG# 27

S1_BVD1 27

S1_CD2# 27

S1_CD1# 27

S1_CE2# 27

S1_IORD# 27

S1_BVD2 27

S1_INPACK# 27

Page 29: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

LAN RESERVED

LAN RESERVED

W=30mils

W=30mils W=20mils

W=40mils

W=40mils

W=40mils

W=30mils

0603

IDSEL : PCI_AD18

TIP RING

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

MINI_PCI SOCKET

LA-1911 0.2

MINI_PCI

Compal Electronics, Inc.

B

29 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

CLK_PCI_MINI

PCI_AD18

PCI_AD[0..31]

PCI_AD3

PCI_AD12

PCI_AD27

PCI_AD4

PCI_AD14

PCI_AD26

PCI_AD18

PCI_AD21

PCI_AD11

PCI_AD17

PCI_AD23

PCI_AD13

PCI_AD20

PCI_AD5

PCI_AD9PCI_AD10

PCI_AD19

PCI_AD24

PCIRST#

PCI_AD15

MINI_IDSEL

PCI_AD25

PCI_AD31

PCI_AD0

PCI_AD8

PCI_AD2

PCI_AD6

PCI_AD22

PCI_AD1

PCI_AD29

CLK_PCI_MINI

PCI_AD7

PCI_AD16

PCI_AD28

PCI_AD30

PCI_PIRQG#PCI_PIRQH#

+3V

+3VS_MINIPCI

+5VS

+5VS_MINIPCI

+5VS_MINIPCI

+3VS_MINIPCI

+5VS_MINIPCI

+3VS_MINIPCI

+3V

+3V

+5VS_MINIPCI

+3V

+3V

C250

0.1U_0402_16V4Z

12

D38RB751V_SOD323

21

C321

0.1U_0402_16V4Z

12

L21

0_0603_5%

1 2

C779 0.1U_0402_16V4Z

C280

0.1U_0402_16V4Z

12

KEY KEY

JP24

KEYLINK_5305-4-211

1 2

3 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 5051 5253 5455 5657 5859 6061 6263 6465 6667 6869 7071 7273 7475 7677 7879 8081 8283 8485 8687 8889 9091 9293 9495 9697 9899 100

101 102103 104105 106107 108109 110111 112113 114115 116117 118119 120121 122123 124

1 2

3 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 5051 5253 5455 5657 5859 6061 6263 6465 6667 6869 7071 7273 7475 7677 7879 8081 8283 8485 8687 8889 9091 9293 9495 9697 9899 100101 102103 104105 106107 108109 110111 112113 114115 116117 118119 120121 122123 124

C209

0.1U_0402_16V4Z

12

C143

1000P_0402_50V7K

12

C184

0.1U_0402_16V4Z

12

C1530.1U_0402_16V4Z

12L14 0_0603_5%

1 2

C299

0.1U_0402_16V4Z

12

C32810U_1206_10V4Z

1

2

C711@10P_0402_50V8K

12

C251

0.1U_0402_16V4Z

12

L20

0_0603_5%

1 2

R520@33_0402_5%

12

C28810U_1206_10V4Z

1

2

R192 100_0402_5%1 2

U54

TC7SH08FU_SSOP5

1

2

3

4

5

CLK_PCI_MINI15

PCI_C/BE#223,26,27,30

PCI_SERR#23,26,27,30

PCI_C/BE#323,26,27,30

PCI_PERR#23,26,27,30

PM_CLKRUN#24,26,27,30,34,37

PCI_IRDY#23,26,27,30

PCI_C/BE#123,26,27,30

PCI_REQ#123

PCI_AD[0..31] 23,26,27,30

PCIRST# 10,16,22,23,26,27,30,33,34,37

PCI_TRDY# 23,26,27,30PCI_FRAME# 23,26,27,30

PCI_STOP# 23,26,27,30

PCI_GNT#1 23

PCI_PAR 23,26,27,30

PCI_DEVSEL# 23,26,27,30

WLANPME # 26,27,30,37

PCI_C/BE#0 23,26,27,30

PCI_PIRQG# 23PCI_PIRQH#23

KILL_SW#37,39

WL_OFF#37

Page 30: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PROPRIETARY NOTE

IDSEL:PCI_AD16

LA-1911 0.2

1394 Interface

Compal Electronics, Inc.

B

30 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

PCI_C/BE#0PCI_C/BE#1PCI_C/BE#2PCI_C/BE#3

PCI_PAR

PCI_FRAME#PCI_IRDY#PCI_TRDY#

PCI_DEVSEL#PCI_STOP #

1394_IDSEL

PCI_AD16

PCI_GNT#0PCI_REQ#0

PCI_SERR#

PCI_PERR#

CLK_PCI_1394

1394_PME #PCI_PIRQE#

TPBIAS0

TPB0+TPB0-

PCI_AD[0..31]

CLK_PCI_1394

1394_IDSEL

1394_PLLVDD

PCI_AD0PCI_AD1PCI_AD2PCI_AD3PCI_AD4PCI_AD5PCI_AD6PCI_AD7PCI_AD8PCI_AD9

PCI_AD10PCI_AD11PCI_AD12PCI_AD13PCI_AD14PCI_AD15PCI_AD16PCI_AD17PCI_AD18PCI_AD19PCI_AD20PCI_AD21PCI_AD22PCI_AD23PCI_AD24PCI_AD25PCI_AD26PCI_AD27

PCI_AD31PCI_AD30PCI_AD29PCI_AD28

PCIRST# TPA0+TPA0-

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

C554

0.1U_0402_16V4Z

C84

1000P_0402_50V7K

R428@10_0402_5%

12

R42056.2_0603_1%

R385 4.7K_0402_5%1 2

R427 4.7K_0402_5%1 2

C544

0.1U_0402_16V4Z

C582

0.01U_0402_25V4Z

C588 22P_0402_50V8J

C584

1000P_0402_50V7K

L7BLM21A601SPT_0805

1 2

R41556.2_0603_1%

R416 100_0402_5%1 2

R42220_0402_5%

12

C82

1000P_0402_50V7K

C565

0.1U_0402_16V4Z

R68 6.34K_0603_1%

R386 10K_0402_5%1 2

R4075.11K_0603_1%

R45 220_0402_5%1 2

C587 22P_0402_50V8J

C62

1000P_0402_50V7K

C58

1000P_0402_50V7K

C77

0.1U_0402_16V4Z

C81

0.1U_0402_16V4Z

C583@10P_0402_50V8K

R384 4.7K_0402_5%1 2

R403 1K_0402_5%1 2

R44 220_0402_5%1 2

C79

0.1U_0402_16V4Z

R41156.2_0603_1%

C543

220P_0402_50V8K

R42256.2_0603_1%

R43220_0402_5%

12

R429 4.7K_0402_5%12

C520

0.1U_0402_16V4Z

C509

0.1U_0402_16V4Z

C108

4.7U_0805_10V4Z

C579

0.33U_0603_16V4Z

1

2

JP20

FOX_UV31413-T 1_4P

4321

4321

C519

0.1U_0402_16V4Z

X524.576MHz_16P_3XG-24576-43E1

12

PHY PORT 1

POWER CLASS

EEPROM 2 WIRE BUS

FILTER

OSCILLATOR

BIAS CURRENT

PCI BUS INTERFACE

TSB43AB21/(TSB43AB22)

U36

TSB43AB21_PQFP128

86 96 10 118720 35 48 62 78

3132373840414243454661636566676970717476777980818284

3447607316181936495052535456132157581285

14

8990

8 9 109

110

111

117

126

127

128

17 23 30 33 44 55 64 68 75 83 93 103

15273951597288100712107108120

106

125124123122121

118

119

6

5

3

4

92

91

999897

116115114113112

9495

101102104105

222425262829

CY

CLE

OU

T/C

AR

DB

US

CN

AT

ES

T17

TE

ST

16

CY

CLE

IN

VD

DP

VD

DP

VD

DP

VD

DP

VD

DP

PCI_AD25PCI_AD24PCI_AD23PCI_AD22PCI_AD21PCI_AD20PCI_AD19PCI_AD18PCI_AD17PCI_AD16PCI_AD15PCI_AD14PCI_AD13PCI_AD12PCI_AD11PCI_AD10PCI_AD9PCI_AD8PCI_AD7PCI_AD6PCI_AD5PCI_AD4PCI_AD3PCI_AD2PCI_AD1PCI_AD0

PCI_C/BE3PCI_C/BE2PCI_C/BE1PCI_C/BE0PCI_CLKPCI_GNTPCI_REQPCI_IDSELPCI_FRAMEPCI_IRDYPCI_TRDYPCI_DEVSELPCI_STOPPCI_PERRPCI_INTA/CINTPCI_PME/CSTSCHGPCI_SERRPCI_PARPCI_CLKRUNPCI_RST

G_RST

GPIO3GPIO2

PLL

GN

D1

RE

G_E

NA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DD

GN

DD

GN

DR

EG

18D

GN

DD

GN

DD

GN

DD

GN

DD

GN

DD

GN

DD

GN

DR

EG

18D

GN

D

DVDDDVDDDVDDDVDDDVDDDVDDDVDDDVDD

PLLVDDAVDDAVDDAVDDAVDDAVDD

CPS

NC/(TPBIAS1)NC/(TPA1+)NC/(TPA1-)

NC/(TPB1+)NC/(TPB1-)

R0

R1

X0

X1

FILTER0

FILTER1

SDA

SCL

PC0PC1PC2

TPBIAS0TPA0+TPA0-

TPB0 +TPB0 -

TEST9TEST8

TEST3TEST2TEST1TEST0

PCI_AD31PCI_AD30PCI_AD29PCI_AD28PCI_AD27PCI_AD26

C586

0.1U_0402_16V4Z

C585

0.1U_0402_16V4Z

PCI_C/BE#023,26,27,29PCI_C/BE#123,26,27,29PCI_C/BE#223,26,27,29PCI_C/BE#323,26,27,29

PCI_PAR23,26,27,29

PCI_FRAME#23,26,27,29PCI_IRDY#23,26,27,29

PCI_TRDY#23,26,27,29PCI_DEVSEL#23,26,27,29

PCI_STOP #23,26,27,29

PCI_REQ#023PCI_GNT#023

PCI_PERR#23,26,27,29

PCI_SERR#23,26,27,29

CLK_PCI_139415

1394_PME #26,27,29,37

PM_CLKRUN#24,26,27,29,34,37PCIRST#10,16,22,23,26,27,29,33,34,37

PCI_PIRQE#23

PCI_AD[0..31]23,26,27,29

Page 31: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AC97 Codec

AGND

AGNDDGND

(4.5V)

DGND To AGND BypassAudio Signal Bias Circuit

CD_AGND To CD_GNA Bypass Analog Reference V

DGND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PROPRIETARY NOTE

+5VALWP TO +5VLDO

+5VALWP DECOUPLING(4.5V)

(4.5V)

+5VALWP TO +5VLDO

***

Remove Bypass R**

**

***

DIRECT PLAY PATHPOWER ON PATH

+5VLDO DECOUPLING

*** ***

********

****

Adjustable Output

LA-1911 0.2

AC97 Codec

Custom

31 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number R e v

Date: Sheet o f

LINER

C_MD_SPK

LINEIN_L

CD_L

AC97_R

C D _ R

LINEIN_R

LINEL

C_MIC

C D _ G N A

AC97_L

C D _ R

CD_L

C D _ G N A

LINEIN_L

LINEIN_R

CD_PLAY

AGND

AMP_LEFT

AMP_RIGHT

INT_CD_L

INT_CD_R

AC97_R

AC97_L AMP_LEFT

AMP_RIGHT

SUSP#

+VDDA

SUSP#

+3VS

+AUD_VREF

+AVDD_AC97

+5VALWP B+ +5VALWP

+5VLDO

+AUD_VREF

+5VALWP

+5VLDO

+5VLDO

+5VLDO +5VAMP

+AVDD_AC97

+5VALWP

+5VALWP

+5VALWP

+5VALWP

+5VAMP

+5VAMP

+5VAMP

+5VAMP

+VDDA

+VDDA

+5VALWP

+5VAMP

L11

CHB2012U170_08051 2

L12

CHB2012U170_0805

1 2

C8094.7U_0805_10V4Z

C173

1U_0

603_

10V

4Z

1

2

Q14

2N7002_SOT231

32

D

SG

U44

ALC202_E_LQFP48

14

15

17

16

23

24

18

20

19

21

22

13

12

35

36

37

11

10

6

5

8

2

3

29

30

28

27

1 925 38

32

46

47

48

47

39

41

3133344344

45

402642

AUX_L

AUX_R

VIDEO_R

VIDEO_L

LINE_IN_L

LINE_IN_R

CD_L

C D _ R

C D _ G N D

MIC1

MIC2

PHONE

PC_BEEP

LINE_OUT_L

LINE_OUT_R

MONO_OUT

RESET#

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

XTL_IN

XTL_OUT

AFILT1

AFILT2

VREFOUT

VREF

DVDD

1

DVDD

2

AVD

D1

AVD

D2

VRDA

XTLSEL

EAPD

SPDIFO

DVSS1DVSS2

TRUE_LOUT_L

TRUE_LOUT_R

VRADDCVOL

VAUXGPIO0GPIO1

N C

N CAVSS1AVSS2

C291

0.1U

_040

2_16

V4Z

C700

1U_0

603_

10V

6K

C653

22P_0402_25V8K

1

2

R63769.8K_0603_1%

12

R225 6.8K_0402_5%12

R188@0_0402_5%

12

L62

@CHB2012U170_0805

1 2

R6231M_0402_5%

12

C633

1U_0

603_

10V

4Z

1

2

C692 1U_0603_10V6K

R512 6.8K_0402_5%12

C634

22U

_120

6_10

V4Z

1

2

C8120.1U_0402_16V4Z

C284 1U_0603_10V6K

R18620K_0402_1%

12

R456

3.9K_0603_1%

12

C238 15P_0402_50V8J1 2

C687

0.1U_0402_16V4Z

C252

10U_1206_10V4Z

R209 @0_0402_5%1 2

R45910K_0402_5%

12

C97

22U

_120

6_10

V4Z

1

2

Q41

2N7002_SOT231

32

D

SG

C702 1U_0603_10V6K

[email protected]_0402_25V4Z

U 5 7 B74HCT4066

11 10

147 12

C115

4.7U

_080

5_10

V4Z

1

2

R162

@1M_0402_5%

12

R514 20K_0402_1%12

C696 @1000P_0402_50V7K

C317

1U_0

603_

10V

6K

C694 1000P_0402_50V7K

C688

0.1U

_040

2_16

V4Z

C703 1U_0603_10V6K

C658 1U_0603_10V6K

C314

1U_0

603_

10V

6K

R6181M_0402_5%

12

R227 6.8K_0402_5%12

C693 1U_0603_10V6K

C99

0.1U

_040

2_10

V6K

1

2

U61

SI9182DH-AD_MSOP8

4

8

5

3

6

7 1

2VIN

ON/OFF#

VOUT

G N D

SENSE

ERROR CNOISE

DELAY

R634 0_0402_5%1 2

R210 0_0402_5%1 2

C102

4.7U

_080

5_10

V4Z

1

2

R47710K_0402_5%

12

C636

22U

_120

6_10

V4

Z

1

2

U59SI4800DY_SO8

1234

8765

SSSG

DDDD

R177 22_0402_5%1 2

C635

1U_0

603_

10V

4Z

1

2

U 5 7 A74HCT4066

1 2

147 13 R620

1M_0402_5%

12

U57D74HCT4066

8 9

147 6

R63824K _0402_1%

12

R617

1M_0402_5%

12

C262 1U_0603_10V6K

L10

CHB2012U170_08051 2

C306 1000P_0402_50V7K

C8021U_0603_10V6K

R513 20K_0402_1%12

R476 100_0402_5%12

C695 @1000P_0402_50V7K

C304 1U_0603_10V6K

C7810.1U_0402_10V6K

1

2

R228 6.8K_0402_5%12

C654

0.1U_0402_16V4Z

D51

LM431SC_SOT23

1

3

2

A

R

K

+ C589

150U

_D2_

6.3V

M1

2

C652

22P_0402_25V8K

1

2

R13610K_0402_5%

12

R6221M_0402_5%

12

R6191M_0402_5%

12

R178 22_0402_5%1 2

R455

4.99K_0603_1%

12

C8100.1U_0402_16V4Z

C8031U_0603_10V6K

C303 1U_0603_10V6K

U57C74HCT4066

4 3

147 5

R173 @10K_0402_5%1 2

R226 6.8K_0402_5%12

C106

0.1U

_040

2_10

V6K

1

2

C807

1U_0

805_

25V

4Z 1

2

C689

0.01

U_0

402_

25V

4Z

R621

1M_0402_5%

12

R1846.8K_0402_5%

12

C705

1U_0

603_

10V

6K

R515 6.8K_0402_5%12

C8114.7U_0805_10V4Z

R212 0_0402_5%1 2

C179

1U_0

603_

10V

4Z

1

2

X624.576MHz_16P_3XG-24576-43E1

1 2

R6241M_0402_5%

12

R195

@0_0603_5%

1 2

C282

10U_1206_10V4Z

R187

0_0402_5%

12

R474

0_0402_5%1 2

ICH_AC_BITCLK 24,36

MD_SPK36

ICH_AC_SDIN0 24

EAPD32

ICH_AC_SYNC24,36

ICH_AC_RST#24,36

MONO_IN32

ICH_AC_SDOUT24,36

INT_CD_L33

LINE_IN_R32

INT_CD_R33

LINE_IN_L32

CD_AGND33

MIC32

CD_PLAY33,37

AMP_RIGHT 32

AMP_LEFT 32

SUSP#33,37,38,43,49,51 SUSP19,43,50

Page 32: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PROPRIETARY NOTE

Left Speaker Connector

+3V POWER

+3V POWER

+3V POWER

Right Speaker Connector

LINE IN JACK

HEADPHONE OUT JACK

MICROPHONE IN JACK

EC Beep

PCI Beep

CardBus Beep

System Beep To AC97' Codec

** **

fo=1/(2*3.14*R*C)=225HzR=1.5K / C=0.47U

W=40Mil

Audio Amplifier

***

***

LA-1911 0.2

AMP & Audio Jack

Custom

32 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

INTSPK_L1-2

MIC

INTSPK_L1 INTSPK_L1-4

INTSPK_R1-2INTSPK_R1

MIC-1

INTSPK_R1-4

MONO_IN

INTSPK_R1-3

INTSPK_L1-3

LINE_IN_R-1

LINE_IN_L-1

INTSPK_R2

NBA_PLUG

INTSPK_L2INTSPK_L1

INTSPK_R1

NBA_PLUG

INTSPK_R2INTSPK_L2

AMP_LEFT

AMP_RIGHT

NBA_PLUGVOL_AMP

HP_L

HP_R

AMP_LEFT

AMP_RIGHT

INTSPK_L1INTSPK_R1

SHUTDOWN#

+AUD_VREF

+3V

+3V

+3V

+AVDD_AC97

+5VAMP

+5VAMP

+5VAMP

+5VAMP

+5VAMP

D62@V-PORT-0603-220 M-V05_0603

21

C3230.47U_0603_16V4Z

1 2

R97560_0402_5%

1 2

G

D

S

Q522N7002_SOT 23

2

13

R43810K_0402_5%

12

C1210.22U_0603_10V7K

1

2

C335

0.47

U_0

603_

16V

4Z

12

+

C392150U_D2_6.3VM

1 2

R11710K_0402_5%

12

L51

FBM-11-160808-700T_06031 2

Q57@2SC2411K-CQ_SOT23

2

31

C1741U_0603_10V6K

1 2

C714

0.1U_0402_16V4Z

12

C769330P_0402_50V7K

12

R58747_0402_5%

1 2

C960.1U_0402_16V4Z

1 2

C340

0.47

U_0

603_

16V4

Z

12

C6041U_0603_10V6K

1 2

R553100K_0402_5%

12

R95560_0402_5%

1 2

C3250.47U_0603_16V4Z

1 2

C768@1U_0603_10V4Z

U48

TPA0232

234

215

620

71819

23

2413121

810169111415

17

22

PC-ENABLEVOLUMELOUT+ROUT+LLINEIN

LHPINRHPIN

PVDDPVDDVDD

RLINEIN

GNDGNDGNDGND

RINLIN

ROUT-LOUT-

BYPASSPC-BEEPSE/BTL#

CLK

SHUTDOWN#

D61@V-PORT-0603-220 M-V05_0603

21

L61 FBM-11-160808-121-T_06031 2

[email protected]_0402_5%

12

R578@18K_0603_1%

1 2

C3321U_0603_10V6K

1 2

U4C

SN74LVC125APWLE_T SSOP14

9 8

10

I OOE

#

C3374.7U_0805_10V4Z

12

R230100K_0402_5%

12

R582 0_0402_5%1 2

JP28

FOXCONN JA6033L-5S1-TR

12

3

4

5

6

C339

0.47

U_0

603_

16V4

Z

L59 FBM-11-160808-121-T_06031 2

JP30

FOXCONN JA6033L-5S1-TR

12

3

4

5

6

R1182.4K_0402_5%

12

JP11

MOLEX_53398-0290

12

R4468.2K_0402_5%

1 2

L48

FBM-11-160808-700T_06031 2

C3270.47U_0603_16V4Z

1 2

R10710K_0402_5%

12

C721

0.1U_0402_16V4Z

12

C804 0.1U_0402_16V4Z

C931U_0603_10V6K

1 2

L60 FBM-11-160808-121-T_06031 2

C8050.047U_0402_16V4Z

L58 FBM-11-160808-121-T_06031 2

R576@18K_0603_1%

1 2

U39ASN74LVC14APWLE_T SSOP14

21

147

OI

PG

C764

330P_0402_50V7K

12

R2411.5K_0603_5%

12

U39BSN74LVC14APWLE_T SSOP14

43

147

OI

PG

JP29

FOXCONN JA6033L-5S1-TR

12

3

4

5

6

R440560_0402_5%

1 2

+

C391150U_D2_6.3VM

1 2

D50RB751V_SOD323

21

D58

@V-PORT-0603-220 M-V05_0603

21

C766

220P_0402_50V8K

12

R63310K_0402_5%

12

C7441U_0603_10V6K

1 2

L50FBM-11-160808-700T_0603

1 2

L47FBM-11-160808-700T_0603

1 2

C773330P_0402_50V7K

12

JP10

MOLEX_53398-0290

12

L49

FBM-11-160808-700T_0603

1 2

C

BE

Q372SC2411K_SOT23

1

2

3

C1201U_0603_10V6K

1 2

R629 0_0402_5%1 2

C3260.47U_0603_16V4Z

1 2

C761

330P_0402_50V7K

12

R2381.5K_0603_5%

12

D57

@V-PORT-0603-220 M-V05_0603

21

R583@100K_0402_5%

12

R58647_0402_5%

1 2

R5812.2K_0402_5%1

2

R81100K_0402_5%

12

C14010U_1206_10V4Z

1

2

MIC31

SPKR24

PCM_SPK#27

BEEP#37

MONO_IN 31

LINE_IN_L31

LINE_IN_R31

NBA_PLUG38

AMP_LEFT31

AMP_RIGHT31

VOL_AMP38

EAPD 31

Page 33: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

W=80mils

Place component's closely MODULE CONNECTOR.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

HDD CONNECTOR

Placea caps. near HDDCONN.

+3V POWER

**

***

LA-1911 0.2

IDE/ FDD MODULE CONN.

Compal Electronics, Inc.

B

33 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

IDE_PDD14

IDE_PDCS1# IDE_PDCS3#

IDE_PDD13

IDE_PDA2IDE_PDA0

IDE_IRQ14

IDE_PDIOR#

IDE_PDA1

IDE_PDIOW#

IDE_PDD3

PCIRST#

PCIRST1#

IDE_PDD4

IDE_PDDREQ

PCSEL

IDE_PDD1

IDE_PDD12

IDE_PDD5

IDE_PDD[0..15]

IDE_PDD2

IDE_PDD11

IDE_PDD7

IDE_PDD10

IDE_PDD8

IDE_PDD0

IDE_PDD6 IDE_PDD9

PIDE_RST#

IDE_PDD15

SHDD_LED#

IDE_SDD3IDE_SDD2

IDE_SDD12IDE_SDD13

IDE_SDD9

IDE_SDD11

IDE_SDD1IDE_SDD0

IDE_SDD14

IDE_SDD10

IDE_SDD15

IDE_SDD8

SHDD_LED#

CD_AGND

IDE_SDIOW#IDE_SDIOR#

IDE_SDCS3#IDE_SDA0IDE_SDA1IDE_IRQ15

IDE_SDDREQ

IDE_SDCS1#

SIDE_RST#

INT_CD_L INT_CD_R

IDE_SDD7IDE_SDD6

IDE_SDD4IDE_SDD5

IDE_SDD[0..15]

IDE_SDDACK#

SUSP# CD_PLAY

SIDE_RST#

PIDE_RST#PCIRST1#

+5VCD

+5VS+5VS

+5VS

+5VS

+5VS

+5VCD

+5VCD+5VCD

+5VCD

+5VCD

+5VCD

+5VALWP

+5VALWP

+5VCD

+5VALWP

C390

1U_0805_25V4Z

C3850.1U_0402_16V4Z

22K

22K

Q26@DTC124EK_SOT23

2

13

R602 10_0402_5%

1 2

U60C

74HCT08PW_TSSOP14

9

108I0

I1O

C367 0.1U_0402_10V6K

1 2

C383

1000P_0402_50V7K

C387

1U_0805_25V4Z

C370

10U_1206_10V4Z

R8010K_0402_5%

R276 240K_0402_5%1 2

R270 100K_0402_5%1 2

R636 @0_0402_5%

C389

10U_1206_10V4Z

C365

1U_0805_25V4Z

C388

10U_1206_10V4Z

U60B

74HCT08PW_TSSOP14

4

56I0

I1O

R281 470_0402_5%1 2

JP27

ALLTOP_C12424-25001

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50

C384

0.1U_0402_16V4Z

R27915_0402_5%

12

U24

SI4425DY-T1_SO8

1234 5

678S

SSG D

DDD

R280

15_0402_5%

12

R268 100K_0402_5%1 2

C363

0.1U_0402_16V4ZC37210U_1206_10V4Z

1

2

R278 10K_0402_5%

U60A

74HCT08PW_TSSOP14

1

23

147

I0

I1O

PG

C382

15P_0402_50V8J

12

C381

15P_0402_50V8J

12

R277 100K_0402_5%1 2

22K

22K

Q25DTC124EK_SOT23

2

13

C759

4.7U_0805_10V4Z

1

2

U4D

SN74LVC125APWLE_T SSOP14

12 11

13

I OOE

#

C376

1U_0805_25V4Z

12

R269

470_0402_5%

12

C3690.1U_0402_16V4Z

JP9

ALLTOP_C17826-14401

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 44

C758

1000P_0402_50V7K

PCIRST#10,16,22,23,26,27,29,30,34,37

IDE_PDIORDY24

IDE_PDCS3# 24

IDE_PDDACK#24

IDE_PDCS1#24

IDE_IRQ1423

SIDERST#24,42

IDE_PDA024

IDE_PDIOR#24

IDE_PDD[0..15]24

IDE_PDA124

IDE_PDDREQ24

IDE_PDA2 24

IDE_PDIOW#24

PIDERST#23

PHDD_LED#37

CD_AGND31

SHDD_LED#37IDE_SDCS1#24,42

IDE_SDA2 24,42

IDE_IRQ1523,42IDE_SDIORDY24,42

IDE_SDIOW#24,42IDE_SDIOR# 24,42

IDE_SDCS3# 24,42IDE_SDA024,42IDE_SDA124,42

IDE_SDDREQ 24,42

INT_CD_L31 INT_CD_R 31

IDE_SDD[0..15]24,42

IDE_SDDACK# 24,42

CD_PLAY 31,37SUSP#31,37,38,43,49,51

PCMRST# 37

EC_IDERST37

Page 34: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

SUPER I/O SMsC FDC47N227

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PROPRIETARY NOTE

Base I/O Address0 = 02Eh1 = 04Eh

*

LA-1911 0.2

SUPER I/O

Compal Electronics, Inc.

B

34 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

LPD[0..7]

CTS#2DSR#2DCD#2RI#2

LPD0LPD1

LPD4LPD5

DCD#2

CLK_PCI_SIO

RI#2

CTS#1

LPD3

RI#1

LPTBUSY

LPD7

LPTSLCT

CTS#2

LPD6

LPTACK#LPTERR#

LPTPE

DSR#2

LPD2

RTS#1

TXD1DSR#1

DTR#1

DCD#1

DSR#1CTS#1RI#1DCD#1

RXD1

CLK_14M_SIO

LPC_AD0LPC_AD1LPC_AD2LPC_AD3

LPC_AD[0..3]

WP#

RDATA#

MTR0#

FDDIR#

DSKCHG#INDEX#

STEP#

WDATA#WGATE#

TRACK0#

DRV0#

HDSEL#

CLK_PCI_SIO CLK_14M_SIO

PID3PID2PID1PID0

IRRX

IRRX

DCD#1RI#1DTR#1CTS#1RTS#1DSR#1TXD1RXD1

PID[0..3]

HDSEL#WGATE#STEP#

WDATA#

DRV0# DSKCHG#FDDIR#

MTR0#

RDATA#WP#TRACK0#INDEX#

+3VS

+3VS+3VS

+3VS

+5V

+3VS

+3VS

+3VS

+5VS

+5VS

+5VS

+3VS

RP67

10P8R_1K

109876

12345

JP25

@96212-1011S

123456789

10

12345678910

RP66

4.7K_8P4R_1206_5%

1 82 73 64 5

R252 @1K_0402_5%1 2

R271 1K_0402_5%1 2

U21

LPC47N227 TQFP100 SUPER I/O

3028

1

13

3

5

89

1011

1415

16

12

4

2

8382

81

66

67

80

797877

6869707172737475

19

95

92

96

94

979899100

849190

8586878889

7316076

65

29

636162

53

20212223

2425

2627

18

17

93

632333435363738394041424344454647

48

49

50

5152

545556575859

64

SIRQCLKRUN#

DRVDEN0

INDEX#

MTR0#

DS0#

DIR#STEP#

WDATA#WGATE#

TRK0#WRTPRT#

RDATA#

HDSEL#

DSKCHG#

DRVDEN1

STROBE#/DS0#AUTOFD#/DRVDEN0#

ERROR#/HDSEL#

INIT#/DIR#

SLCTIN#/STEP#

ACK#/DS1#

BUSY/MTR1#PE/WDATA#

SLCT/WGATE#

PD0/INDEX#PD1/TRK0

PD2/WRTPRT#PD3/RDATA#

PD4/DSKCHG#PD5

PD6/MTR0#PD7

CLK14

RXD2

RI2#

TXD2

DCD2#

DSR2#RTS2#CTS2#DTR2#

RXD1DCD1#

RI1#

TXD1DSR1#RTS1#CTS1#DTR1#

VSSVSSVSSVSS

VCC

PCICLK

IRMODE/IRRX3IRRX2IRTX2

VCC

LAD0LAD1LAD2LAD3

LFRAME#LDRQ#

PCIRST#LPCPD#

VTR

IO_PME#

VCC

GPIO24GPIO30GPIO31GPIO32GPIO33GPIO34GPIO35GPIO36GPIO37GPIO40GPIO41GPIO42GPIO43GPIO44GPIO45GPIO46GPIO47

GPIO10

GPIO11/SYSOPT

GPIO12/IO_SMI#

GPIO13/IRQIN1GPIO14/IRQIN2

GPIO15GPIO16GPIO17GPIO20GPIO21GPIO22

GPIO23/FDC_PP

R262@33_0402_5%

12

R275 10K_0402_5%12

RP68

1K_8P4R_1206_5%

1 82 73 64 5

C366@22P_0402_25V8K

1

2

R247 10K_0402_5%12

C352

0.1U_0402_16V4Z

12

R248 10K_0402_5%12

R243 10K_0402_5%1 2

C3710.1U_0402_16V4Z

12

R274@10_0402_5%

12

R603 10_0402_5%

1 2

C364

4.7U_0805_10V4Z

12

C375@15P_0402_50V8J

12

R24910K_0402_5%

1 2

R251 10K_0402_5%12

R244 10K_0402_5%1 2

R253 1K_0402_5%1 2

R26710K_0402_5%

12

RP65

4.7K_8P4R_1206_5%

18273645

C351

0.1U_0402_16V4Z

12

R255 1K_0402_5%1 2

LPD[0..7] 36

LPTBUSY 36LPTPE 36LPTSLCT 36LPTERR# 36LPTACK# 36INIT# 36LPTAFD# 36LPTSTB# 36SLCTIN# 36CLK_14M_SIO15

CLK_PCI_SIO15PM_CLKRUN#24,26,27,29,30,37SERIRQ23,27,37

LPC_FRAME#24,37LPC_DRQ1#24

LPC_AD[0..3]24,37

IRMODE 35

IRTXOUT 35IRRX 35

PID[0..3]22

PCIRST#10,16,22,23,26,27,29,30,33,37

BT_DET#36

FIR_EN#35

Page 35: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

FIR Module

The component's most placecloely IRDA MODULE.

FIR_EN# LOW FIR Poped

HIGH FIR Un-Poped

USBCONNECTOR

USBCONNECTOR

Keep 20 mils minimum spacing

**

LA-1911 0.2

USB Conn.

Compal Electronics, Inc.

B

35 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

USB_OC4#

USB_OC0#

USB_OC2#

IRMODEIRTXOUT

+IR_VCCIRRX

+IR_ANODE

USBP2-

USBP4+

USBP2+

USBP4-

USB0-

USB0+

USBP0-

USBP0+

USB0-

USB2-

USB2+USB4+

USB4-

USB0-USBP0-

USBP0+

USBP2-

USBP2+

USBP4-

USBP4+

USB0+

USB2-

USB2+

USB4-

USB4+

+IR_GND

USB2+USB2-

USB4-

USB0+

USB4+

+USB_CS

+5V

+3VALW

+USB_AS

+5V

+3VALW+USB_BS

+3VS

+3VS

+IR_ANODE

+USB_AS

+USB_BS

+USB_CS

C470

0.1U_0402_16V4Z

12

U29

TPS2042ADR_SO8

12

56

8

34

7GNDIN

OC2#OUT2

OC1#

EN1#EN2#

OUT1

R344 0_0402_5%1 2

C767

100P_0402_50V8K

12

C25

@0.1U_0402_16V4Z

JP31

SUYIN_2569A-04G3T -A

1234

U53

TPS2041ADR_SO8

1234 5

678GND

ININEN# OC#

OUTOUTOUT

R36647_0402_5%

1 2

[email protected]_1206_5%

1 2

R588 0_0402_5%1 2

C771

@0.1U_0402_16V4Z

JP15

SUYIN_2553A-08G1T-D_8P

12345678

+C439@150U_D2_6.3VM

1

2

C444

0.1U_0402_16V4Z

12

R589 0_0402_5%1 2

D7

@V-PORT-0603-220 M-V05_0603

21

R342 0_0402_5%1 2

D60

@V-PORT-0603-220 M-V05_0603

21

+C393@150U_D2_6.3VM

1

2

C373

22U_1206_10V4Z

1

2

R584

100K_0402_5%

12

C7650.1U_0402_16V4Z

12

R35747_0402_5%

1 2

R58547_0402_5%

1 2

R343 0_0402_5%1 2

C425

0.1U_0402_16V4Z

L32

@JTS0402-03_4P1 4

2 3

D6

@V-PORT-0603-220 M-V05_0603

21

+ C377

4.7U_0805_6.3VM

1

2

+ C442

150U_D2_6.3VM

12

R250 0_0402_5%

1 2

U52

IR_VISHAY_TFDU6101E-TR4_8P

2

875

1

46

3IRED_C

GNDMODE

SD/MODE

IRED_A

RXDVCC

TXD

D59

@V-PORT-0603-220 M-V05_0603

21

C23

@0.1U_0402_16V4Z

C774

@0.1U_0402_16V4Z

R358

100K_0402_5%

12

C435

0.1U_0402_16V4Z

L33

@JTS0402-03_4P

1 4

2 3

R2733.3_1206_5%

1 2

R345 0_0402_5%1 2

D9

@V-PORT-0603-220 M-V05_0603

21R359

100K_0402_5%

12

C770

0.1U_0402_16V4Z

12

C775

0.1U_0402_16V4Z

C24

@0.1U_0402_16V4Z

+ C445

150U_D2_6.3VM

12

+C776

150U_D2_6.3VM

12

C772

0.1U_0402_16V4Z

12

L52

@JTS0402-03_4P

1 4

2 3

C469

0.1U_0402_16V4Z

12

C26

@0.1U_0402_16V4Z

R579

47_1206_5%

12

D8

@V-PORT-0603-220 M-V05_0603

21

USB_OC4# 24

USB_OC0# 24

USB_OC2# 24

IRRX34IRTXOUT 34IRMODE 34

FIR_EN#34

USBP4+24

USBP4-24

USBP2+24

USBP2-24

USBP0-24

USBP0+24

Page 36: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

PARALLEL PORT

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

(Top Contact)

BlueTooth Interface

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

MDC CONN.

Reset input High Active --> Low ,Reset input Low Active --> Open

Module IDIndication for polarity of reset

Module ID

(MAX=200mA)

Bluetooth Connector

**

LA-1911 0.2

PARALLEL/MDC PORT

Compal Electronics, Inc.

36 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

LPD[0..7]

LPTSTB#

LPTSLCTIN#

AFD#/3M#

FD6

LPTACK#

FD1

FD4

LPTPE

FD7

LPTERR#

FD5

LPTSLCTIN#

LPTINIT#

FD0

LPTBUSY

FD2

FD3

LPTSLCT

LPTINIT#LPTSLCT IN#

LPTINIT#FD2

FD3

+3VS_MDC

+5VS_MDC

+3V_MDC

FD4FD5FD6FD7

FD3

LPD3

FD2 LPTSLCTIN#

FD0FD1

AFD#/3M#

LPTINIT#LPTERR#

FD3LPD2 FD2LPD1 FD1LPD0 FD0 LPD7 FD7

LPD6 FD6LPD5 FD5LPD4 FD4

LPTPELPTSLCT

LPTACK#LPTBUSY

LPTERR#FD1

AFD#/3M#FD0

LPTACK#

LPTPELPTSLCT

LPTBUSY

FD5FD6FD7

FD4

BT_RESET#BT_WAKE_UP

USB6+USB6-USBP6-

USBP6+

Module_Detect

+5V_PRN

+5VS

+3VS+5VS

+3V+3VS

+3V_MDC

+5VS

+3VS_MDC

+3VS

+5VS_MDC

+5V_PRN

+5V_PRN+5V_PRN

+5V_PRN

+BT_VCC

+BT_VCC

L39 CHB1608B121_06031 2

R5 33_0402_5%1 2

JP12

SUYIN_7843S-25G2T-01

1325122411231022

921

820

719

618

517

416

315

214

1CP3

220P_1206_8P4C_50V8K

234 5

6781

L38 @CHB2012U170_08051 2

C5211U_0805_25V4Z

1

2

RP12.7K_10P8R_1206_5%

10 9 8 7 6

1 2 3 4 5

C57

@0.1U_0402_16V4Z

C5621U_0805_25V4Z

1

2

R406 10K_0402_5%12

22K

22KQ30

@DTC124EK_SOT23

2

13

R400 @0_0603_5%

CP2

220P_1206_8P4C_50V8K

234 5

6781

JP17

@ACES_87153-20081234567891011121314151617181920

C55

@0.1U_0402_16V4Z

C5421U_0805_25V4Z

1

2

L41 CHB1608B121_06031 2

C527

@0.1U_0402_16V4Z

R419 22_0402_5%1 2

R3 33_0402_5%1 2

C489

@10U_1206_10V4Z

RP22.7K_10P8R_1206_5%

10 9 8 7 6

1 2 3 4 5

R133_0402_5%

1 2

R408 @0_0603_5%

RP6968_8P4R_1206_5%

1 82 73 64 5

CP1

220P_1206_8P4C_50V8K

234 5

6781

RP70

68_8P4R_1206_5%

1 82 73 64 5

Q4@SI2301DS-T1_SOT23

2

13

R414 22_0402_5%1 2

R393@100K_0402_5%

12

R409 0_0402_5%

R413 0_0402_5%1 2

R4 33_0402_5%1 2

R22.2K_0402_5%

12

JP19

AMP 3-1565120-0 30P H:9MM

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 30

C529

220P_0402_25V8K

C1

220P_0402_50V8K

1 2

D1

RB420D_SOT 23

2 1

CP4

220P_1206_8P4C_50V8K

234 5

6781

LPTACK#34

LPTBUSY34

LPTSLCT34

LPTERR#34

LPD[0..7]34

LPTPE34

INIT#34

SLCTIN#34

LPTSTB#34

LPTAFD#34

BT_PWR37

ICH_AC_SYNC 24,31

MD_SPK 31

ICH_AC_SDOUT24,31ICH_AC_RST#24,31

ICH_AC_SDIN1 24

ICH_AC_BITCLK 24,31

BT_WAKE_UP37BT_RST#37

BT_DETACH37

USBP6-24USBP6+24

BT_DET#34

Page 37: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E P R O P R IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDT R A D E S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y N OT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DD E P A R T M E N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L E L E CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BEU S E D B Y O R D I S C L O S E D T O A N Y T H I R D P A R TY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

I/O Address

SHBM(KBA5)=1: Enable shared memory with host BIOS

0

1

0

4E

Reserved

ENV1 (KBA1)

0

ENV0 (KBA0) TRIS (KBA4)

(HCFGBAH, HCFGBAL)(HCFGBAH, HCFGBAL)+1

11

PROG0

2E 2F

4F

DEV 0

0

Data

OBD 0

1

Index

IRE

TRIS(KBA4)=1: While in IRE and OBD, float all the signals for clip-on ISE use

0

0

1

BADDR1(KBA3) BADDR0(KBA2)

0

0

01

1 1

*

*

KEYBOARD CONN.

For EC Tools

Ra

Rb

Analog Board ID definition,Please see page 3.

(Need to check layout library with KB spec)

( A C E S _ 8 5201-2405_24P)

P R O P R IETARY NOTE

***

LA-1911 0.2

EC PC87591

Compal Electronics, Inc.

Custom

37 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

KBA[0..19]ADB[0..7]

BATT_TEMPECAGND

ECAGND

FRD#SELIO#FSEL#

CRY1

TP_CLK KBA2

KBA1

TP_DATA

KBA5

KBA3

EC_TINIT#EC_TCK

EC_TDIEC_TDO

EC_TMS

EC_URXD

EC_USCLK

EC_SMB_CK2EC_SMB_DA2

EC_SMB_DA1EC_SMB_CK1

KBA10

EC_PME#

TP_DATA

KBA9

ADB4

KBA7

KBA1

CRY2

KSO8

KSI7

KBA17

ADB7

KSO13

CRY2

SYSON

KBA4

BEEP#

KSI0

LPC_AD2

SUSP#KBA12

SELIO#

KBA5

PBTN_OUT#

AD_BID0

EC_PME#

KBA16

ADB1ADB0

KBA3

AD_BID0

KSO10

KSO7

FSEL#

FSTCHG

EC_LID_OUT#EC_ON

ACOFF

EN_DFAN1#

KSO5KSO4

PM_SLP_S3#

EC_SMB_CK2

BATT_OVP

TP_CLK

EC_TMS

KSO11

KSI5

BKOFF#

KBA13

CAPS_LED#

KBA0

FAN_SPEED1EC_SMB_DA2

DAC_BRIG

EC_TDO

KSI4

KSI2

KBA15

EC_SMI#

FRD#

ADB2

FAN_SPEED2EC_THRM#

IREF

CRY1

KSO3KSO2

KBA14

EC_TDI

KSI1

ECAGND

ACIN

FWR#

EN_DFAN2#

EC_TCK

KSO15

KSO6

KSO0

NUM_LED#

KBA2

KSO1

EC_SCI#

LPC_AD1

KBA11

ADB5

PM_SLP_S5#

INVT_PWM

BATT_TEMP

KSI3

KBA18

ADB6

EC_SMB_DA1EC_SMB_CK1

KBA8

ADB3

LID_SW#

KSO12

KSO9

KSI6

VR_ON

KBA6

EC_TINIT#

KSO14

LPC_AD3

LPC_AD0

KSO11KSO10KSO14

KSI5

KSO4

KSI1KSO1

KSO2

KSO0KSI0

KSO5KSO6

KSO12

KSI6

KSO3

KSO9

KSO7

KSI2

KSI4

KSI3

KSO8

KSO13KSI7

KSO15

NUM_LED#

CAPS_LED#PADS_LED#

PADS_LED#

KSO4

KSI1

KSO2KSI2

KSO11KSO10KSO14KSO15

KSO9KSO8

KSO13KSI7

KSO12

KSO3KSO7

KSI4

KSI5

KSO5KSO6

KSI6

KSO1KSO0KSI0KSI3

NUM_LED#

CAPS_LED#PADS_LED#

BT_WAKE_UP

BT_DETACH

INTERNET#EC_RST#

EC_USCLK

EC_URXD

KILL_SW#

MODE#

MODE#EMAIL#

ALI/MH#

CD_PLAY

EC_UTXD

EC_UTXD

PWR_SUSP_LED

HDD_LED#

KBA19

+3VALW

+RTCVCC +51AVCC +3VALW

+3VALW

+3VS

+51AVCC+3VALW+RTCVCC

+5VS

+3VALW

+3VALW

+3VALW

+5VALW

+3VS

+3VS

+3VS

+3VALW

+51VDD

+3VALW

C336 0.01U_0402_25V4Z12

C295

0.1U_0402_16V4Z

12

CP8 100P_1206_8P4C_50V8

234 5

6781

R215 4.7K_0402_5%1 2

CP10 100P_1206_8P4C_50V8

234 5

6781

CP11 100P_1206_8P4C_50V8

234 5

6781

C334

0.1U_0402_16V4Z

12

C796 @1U_0603_10V4Z1 2

CP5 100P_1206_8P4C_50V8

234 5

6781

RP46

10K_1206_8P4R_5%

18273645

C2571000P_0402_50V7K

12

JP7

@96212-1011S

12345678910

123456789

10C750 0.22U_0603_16V4Z

1 2

R221 4.7K_0402_5%12

C65610P_0402_50V8K

12

C268

1U_0603_10V4Z

1

2

CP7 100P_1206_8P4C_50V8

234 5

6781

R18510K_0402_5%

12

X7

32.768KHz_12.5P_CM155

12

R478

20M_0603_5%

1 2

R5520_0402_5%

12

L22

FBM-L11-160808-800LMT_06031 2

R265 300_0402_5%1 2

C267

0.1U_0402_16V4Z

12

CP6 100P_1206_8P4C_50V8

234 5

6781

R219 4.7K_0402_5%1 2

L23FBM-L11-160808-800LMT_0603

1 2

R561 100K_0402_5%1 2

R204 @0_0402_5%

JP8

6278-34P-KBCON123456789

10111213141516171819202122232425262728293031323334

R469120K_0402_5%

12

R264 300_0402_5%1 2

R189 1K_0402_5%1 2

RP48

10K_1206_8P4R_5%

1 82 73 64 5

R218 0_0402_5%

R203 1K_0402_5%1 2

C701@22P_0402_25V8K

1

2

H o s t interface

K e y matrix scan

J T A G debug port

P S 2 interface

A D Input

D A output

PWMo r PORTA

PORTB

PORTC

PORTE

PORTH

PORTI

P ORTJ-1

P ORTD-1

P ORTD-2 PORTJ-2

PORTK

PORTL

PORTM

U45

PC87591L-VPCN01 A2_LQFP176

56

15141310

19

9

7

18

31

2223

8

16

34

45

12

31

36

95

16

1

7172737477787980

49505152535657585960616465666768

106

108107

105

109

110111114115116117118119

158

160

81828384878889909394

99100101102

3233363738394043

153154162163164165

1681691701711721751761

2442425

124125126127128131132133

138139140141144145146147

150151

1529

6

17

35

46

12

21

59

262930

15

71

66

16

71

37

41425455

626369707576 143

142135134130129121120

113112104103

148149155156

34

2728

48

17317447

12

20

21

85

86

91

92

97

98

11

GA20/IOPB5KBRST/IOPB6

LAD0LAD1LAD2LAD3

RESET1#

LFRAME#

SERIRQ

LCLK

IOPD3/ECSCI#

SMI#PWUREQ#

LDRQ#

VD

D

VC

C1

VC

C2

VC

C3

VC

C4

AV

CC

VB

AT

KBSIN0KBSIN1KBSIN2KBSIN3KBSIN4KBSIN5KBSIN6KBSIN7

KBSOUT0KBSOUT1KBSOUT2KBSOUT3KBSOUT4KBSOUT5KBSOUT6KBSOUT7KBSOUT8KBSOUT9KBSOUT10KBSOUT11KBSOUT12KBSOUT13KBSOUT14KBSOUT15

TCK

TDITDO

TINT#

TMS

PSCLK1/IOPF0PSDAT1/IOPF1PSCLK2/IOPF2PSDAT2/IOPF3PSCLK3/IOPF4PSDAT3/IOPF5PSCLK4/IOPF6PSDAT4/IOPF7

32KX1/32KCLKIN

32KX2

AD0AD1AD2AD3

IOPE0AD4IOPE1/AD5IOPE2/AD6IOPE3/AD7

DP/AD8DN/AD9

DA0DA1DA2DA3

IOPA0/PWM0IOPA1/PWM1IOPA2/PWM2IOPA3/PWM3IOPA4/PWM4IOPA5/PWM5IOPA6/PWM6IOPA7/PWM7

IOPB0/URXDIOPB1/UTXD

IOPB2/USCLKIOPB3/SCL1IOPB4/SDA1

IOPB7/RING/PFAIL/RESET2

IOPC0IOPC1/SCL2IOPC2/SDA2

IOPC3/TA1IOPC4/TB1/EXWINT22

IOPC5/TA2IOPC6/TB2/EXWINT23

IOPC7/CLKOUT

IOPE4/SWINIOPE5/EXWINT40

IOPE6/LPCPD/EXWIN45IOPE7/CLKRUN/EXWINT46

IOPH0/A0/ENV0IOPH1/A1/ENV1

IOPH2/A2/BADDR0IOPH3/A3/BADDR1

IOPH4/A4/TRISIOPH5/A5/SHBM

IOPH6/A6IOPH7/A7

IOPI0/D0IOPI1/D1IOPI2/D2IOPI3/D3IOPI4/D4IOPI5/D5IOPI6/D6IOPI7/D7

IOPJ0/RDIOPJ1/WR0

SELIO#A

GN

D

GN

D1

GN

D2

GN

D3

GN

D4

GN

D5

IOPD0/RI1/EXWINT20IOPD1/RI2/EXWINT21

IOPD2/EXWINT24/RESET2

VC

C5

VC

C6

GN

D6

GN

D7

IOPD4IOPD5IOPD6IOPD7

IOPJ2/BST0IOPJ3/BST1IOPJ4/BST2IOPJ5/PFSIOPJ6/PLIIOPJ7/BRKL_RSTO IOPK0/A8

IOPK1/A9IOPK2/A10IOPK3/A11IOPK4/A12

IOPK5/A13_BE0IOPK6/A14_BE1

IOPK7/A15_CBRD

IOPL0/A16IOPL1/A17IOPL2/A18IOPL3/A19

IOPM0/D8IOPM1/D9IOPM2/D10IOPM3/D11IOPM4/D12IOPM5/D13IOPM6/D14IOPM7/D15

IOPL4/WR1#

SEL0#SEL1#CLK

NC

2N

C3

NC

4N

C5

NC

6N

C7

NC

8N

C9

NC

10

NC

1

CP9 100P_1206_8P4C_50V8

234 5

6781

C735

0.1U_0402_16V4Z

12

R190 1K_0402_5%1 2

R193 @1K_0402_5%1 2

C745

0.1U_0402_16V4Z

12

C285

1000P_0402_50V7K

12

R501@33_0402_5%

12

C264

0.1U_0402_16V4Z

12

C659

0.1U_0402_16V4Z

12

C723

0.1U_0402_16V4Z

12

C64712P_0402_50V8J

12

R263 300_0402_5%1 2

R541100K_0402_5%

12

ADB[0..7]38KBA[0..19]38

1394_PME#26,27,29,30

FSEL#38

SUSP#31,33,38,43,49,51SYSON40,43,49

ENBKL16BKOFF#22

TP_CLK38TP_DATA38

LID_SW#39

LPC_FRAME#24,34

CLK_PCI_LPC15

EC_SMI#24

EC_SWI#24

PCIRST# 10,16,22,23,26,27,29,30,33,34

EC_SMB_DA2 5EC_SMB_CK2 5

FAN_SPEED1 40

PBTN_OUT# 24

PM_SLP_S3# 24

EC_SCI#24

LPC_AD224,34

PCM_PME#26,27,29,30

WLANPME#26,27,29,30

LAN_PME#26,27,29,30

FAN_SPEED2 40BT_PWR 36

EC_RSMRST#24,41

VR_ON52

KSI038KSI138KSI238KSI338

SERIRQ23,27,34

FSTCHG 47

INVT_PWM 22

ON/OFF 39

DAC_BRIG 22

EC_LID_OUT# 24

SELIO# 38

EC_ON 39,41

EC_SMB_DA1 38,46

BATT_OVP 47

FWR# 38

EC_SMB_CK1 38,46

BATT_TEMPA 46

EN_DFAN1 40

EN_DFAN2 40

ACIN 24,38,45

FRD# 38

BEEP# 32

PM_SLP_S5# 24

PM_CLKRUN# 24,26,27,29,30,34

IREF 47

ACOFF 47

LPC_AD024,34

LPC_AD324,34

LPC_AD124,34

BT_WAKE_UP 36

PHDD_LED# 33

BT_DETACH 36

ADP_I 47,51

INTERNET# 39

EC_THRM# 24

BT_RST#36

S4_SATA40WL_OFF#29

GATEA2023KBRST#23

KILL_SW# 29,39

ALI/MH# 46

MODE# 38EMAIL# 39

CD_PLAY 31,33

S4_LATCH40

PCMRST#33

PWR_SUSP_LED 38,39

EC_URXD 41EC_UTXD 41EC_USCLK 41

TV_OUT_EN#39

SHDD_LED#33

KSO1738,39

HDD_LED#39

EC_IDERST33

Page 38: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

SW Board Connector

SW/B and TP/B FFC Connector Pin 1 Definition Same As SW/B and TP/B

Direct CD button board

VR/B FFC Connector Pin 1 Definition Swap with VR/B

VR/CIR Board Connector

to 3V

1MB Flash ROM

512KB Flash ROM**

**

**

**

LA-1911 0.2

BIOS & EXT. I/O PORT

Compal Electronics, Inc.

Custom

38 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

FWE#

ADB4

ADB6

KBA2

ADB0ADB1ADB2ADB3

ADB5

ADB7

AASELIO#

CDON_LED#MP3_LED#EMAIL_LED#PWR_LED#

BATT_CHGI_LED#BATT_LOW_LED#

MODE#

VOL_AMP

ADB4

ADB6

KBA4

ADB0ADB1ADB2ADB3

ADB5

ADB7

CCSELIO#

EC_RCVENEC_RCRST#

RCIRRX

KSO17EC_FRDBTN#EC_STOPBTN#

EC_PLAYBTN#EC_REVBTN#

KBA0

FWE#

FSEL#

KBA3

KBA5

KBA7

KBA9

KBA1KBA2

KBA6

KBA11

KBA14KBA15

KBA4

KBA10

KBA19

ADB0

KBA12

KBA8

KBA13

ADB3ADB2ADB1

KBA16KBA17KBA18

ADB7ADB6ADB5

ADB[0..7]

ADB4

KBA[0..19]

KBA17

KBA5

ADB5

KBA1

ADB5

ADB3

KBA4

FWE#

KBA3

KBA7

KBA14

KBA1

KBA3

KBA8

ADB6

KBA15

KBA17

ADB6

ADB4

KBA10

KBA0

KBA11

ADB0

KBA9

FWE#

KBA10

ADB7

KBA12

KBA6

ADB2ADB1ADB0

KBA15

KBA2KBA6

KBA16KBA4

KBA12

KBA8

KBA0

KBA2

ADB3

KBA5

KBA13

ADB7

FSEL#

FRD#

KBA16

KBA18

KBA11

KBA9

ADB2

KBA18KBA13

KBA14

FRD#

ADB1

ADB4

FSEL#

KBA7

FRD#

51ON#

EMAIL_LED#

CDON_LED#MP3_LED#

BATT_CHGI_LED#

TP_DATA

BATT_LOW_LED#

TP_CLK

PWR_LED#PWR_SUSP_LEDACIN

+3VALW+3VALW

+3VALW

+5VALW

+5VALWP

+5VS

+5VALWP

+3VALW

+5VALW

+5VALW

+5VS

+5VALWP

+5VAMP

+3VALW

+5VALW

+5V_CIR

+5VALWP

+3VALW

+3VALW

+3VALW

+3VALW

+3VALW

R231100K_0402_5%

12

[email protected]_0402_16V4Z

D67

V-PORT-0603-220 M-V05_060321D64

V-PORT-0603-220 M-V05_0603

21

U46

@SST39VF040_TSOP

123456789

101112131415

17181920212223242526272829

3132

16

30

A11A9A8A13A14A17WE#VCCA18A16A15A12A7A6A5

A3A2A1A0

DQ0DQ1DQ2VSSDQ3DQ4DQ5DQ6DQ7

A10OE#

A4

CE#

U56

SST39VF080-70_TSOP40

212019181716151487

36654321

13

2224

2526272832333435

39

40

9

3031

23

37

2938

1110

12

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16

A18

CE#OE#

D0D1D2D3D4D5D6D7

GND1

A17

WE#

VCC1VCC0

GND0

A19

NC0NC1

NCRP#

READY/BUSY#

U47

@SN74HCT273PW_TSSOP20

24 57 68 9

13 1214 1517 1618 19

3

11

20

1

10

Q0D1 Q1D2 Q2D3 Q3D4 Q4D5 Q5D6 Q6D7 Q7

D0

CP

VC

C

MR GN

D

JP5

ACES_85201-1005

1 23 45 67 89 10

C819

220P_0402_50V8K

12

R235

100K_0402_5%

12

U13

@29F040/SST39VF040_PLCC

123456789

101112131415

17181920212223242526272829

3132

16

30

NCA16A15A12A7A6A5A4A3A2A1A0DQ0DQ1DQ2

DQ3DQ4DQ5DQ6DQ7CE*A10OE*A11A9A8

A13A14

WE*VCC

VSS

A17

C817

22

0P

_0

40

2_50

V8K

12

C786

0.1U_0402_16V4Z

1

2

C813

22

0P

_0

40

2_

50

V8

K1

2

C726 @0.1U_0402_16V4Z1 2

C783

@1U_0603_10V6K

1 2

R560

100K_0402_5%

12

R236

100K_0402_5%

12

C791

22

0P

_0

40

2_50

V8K

12

R611@100K_0402_5%

1 2

C345

0.1U_0402_16V4Z

1 2

C792

220P_0402_50V8K

12

U17BSN74LVC32APWLE_TSSOP14

4

56

14

7

A

BO

PG

R607@20K_0603_1%

1 2

[email protected]_0402_16V4Z

1 2

U50

SN74HCT374PW_TSSOP20

24 57 68 9

13 1214 1517 1618 19

3

11

20

1

10

Q0D1 Q1D2 Q2D3 Q3D4 Q4D5 Q5D6 Q6D7 Q7

D0

CP

VC

C

MR GN

D

C818

22

0P

_0

40

2_

50

V8

K1

2

C789

1U_0603_10V4Z

1

2

JP6

ACES_85201-1005

1 23 45 67 89 10

D66

V-PORT-0603-220 M-V05_060321

C814

22

0P

_0

40

2_50

V8K

12

C7530.1U_0402_16V4Z

1 2

U17ASN74LVC32APWLE_TSSOP14

1

23

14

7

A

BO

PG

D65

V-PORT-0603-220 M-V05_0603

21

C793

100P_0402_50V8K

12

C790

22

0P

_0

40

2_50

V8K

12

U17C

SN74LVC32APWLE_TSSOP14

10

98

14

7

A

BO

PG

C729

1U_0603_10V6K

1 2

G

D S

Q182N7002_SOT23

2

1 3

D63

V-PORT-0603-220 M-V05_0603

21

C815

22

0P

_0

40

2_50

V8K

12

C2900.1U_0402_16V4Z1 2

C3110.1U_0402_16V4Z

1

2

L54FCM2012C-800_0805

1 2C816

22

0P

_0

40

2_50

V8K

12

JP4

ACES_85201-2005

123456789

1011121314

161718

15

2019

1234567891011121314

161718

15

2019

U16

AT24C16N10SC-2.7_SO8

12

56

8

34

7 A0A1

SDASCL

VCC

A2GND

WP

C3100.1U_0402_16V4Z

1

2

R542820K_0402_5%

1 2

EC_FLASH# 24

FWR# 37

SUSP# 31,33,37,43,49,51

SELIO#37

PWR_LED# 39

KSI137KSI337

KSI2 37

MODE#37

EC_SMB_CK137,46EC_SMB_DA137,46

TP_CLK37TP_DATA37

ODD_LED# 39

WL_BT_LED# 39

51ON# 39,45

KSI0 37KSO1737,39

VOL_AMP 32

CIR_GATING# 41

EC_RCVEN 41EC_RCRST# 41

RCIRRX 41

ADB[0..7]37KBA[0..19]37

FRD# 37

FSEL# 37

NBA_PLUG32

ACIN24,37,45PWR_SUSP_LED37,39

Page 39: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Power Button

LID Switch

POWER LED

HDD LED ODD LED

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Wireless LED SD LED Kill SWITCH

Internet Button Console/E-MAIL Button TV OUT Button

* Change +3V to +5VALW

* Add R16 1M Pull Low

**

***

LA-1911 0.2

Switchs & Connectors

Compal Electronics, Inc.

B

39 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

EC_ON

51ON#

PWR_LED#

ODD_LED#

WL_BT_LED#

EMAIL#

INTERNET#

51ON#

HDD_LED#

LID_SW#

KSO17 KSI4

PWR_SUSP_LED

SDLED

+3VALW

+3VALW

+3VALW

+5VALWP

+3VALW

+5VALWP+5VALWP

+3VALW

+5VALWP

+5VALWP

+5VALWP

12

D46

RLZ20A2

1

D16

PSOT24C_SOT23

32

D30

@V-PORT-0603-220 M-V05_0603

21

SW5

HCH SMT1-05

3

2

1

4

D54

@V

-PO

RT

-060

3-22

0 M

-V05

_060

3

21

D

SGQ8

NDS352P_SOT23

2

13

D33

HT-191NB_BLUE_0603

21

D53

@V-PORT-0603-220 M-V05_0603

21

G

D

S

Q6

2N70022

13

C801

0.01U_0402_16V7K

1

2

C800

0.01U_0402_16V7K

1

2

R67 100K_0402_5%12

C574

1000P_0402_50V7K

R61

300_0402_5%

12

G

D

S

Q44

2N70022

13

SW2

HCH SMT1-05

3

2

1

4

D11

DAN202U_SC70

2

31

R498

300_0402_5%

12

47K

10KC

BE

Q5DTA114YKA_SOT23

2

31

R16

1M_0402_5%

12

R56

0_0603_5%

12

D29

@V-PORT-0603-220 M-V05_0603

21

R54

100K_0402_5%

12

D241N4148_SOT 23

21

D10

@V-PORT-0603-220 M-V05_0603

21

R426100K_0402_5%

12

R4244.7K_0402_5%

12

D49

DAN202U_SC70

2

31

D69

HT-191NB_BLUE_0603

21

D15

@V-PORT-0603-220 M-V05_0603

21

D68

HT-191UD_AMBER_0603

21

D18

1N4148_SOT 23

21

SW1

FR2283_2P

12

R122 100K_0402_5%12

D26

1N4148_SOT 23

21

D22

PSOT24C_SOT23

32

R213

300_0402_5%

12

R425100K_0402_5%

12

D48

@V-PORT-0603-220 M-V05_0603

21

R418

33K_0603_1%

1 2

G

D

S Q352N7002

2

13

47K

10KC

BE

Q45DTA114YKA_SOT23

2

31

R492300_0402_5%

47K

10KC

BE

Q16DTA114YKA_SOT23

2

31

SW7DS-1200-02

123

123

SW3

HCH SMT1-05

3

2

1

4

SW4

HCH SMT1-05

3

2

1

4

D121N4148_SOT 23

21

22K

22KE

B

C

Q36DTC124EK_SOT23

2

13

R62

300_0402_5%

12

D31

HT-191NB_BLUE_0603

21

D13

@V-PORT-0603-220 M-V05_0603

21

R142300_0402_5%

D47

PSOT24C_SOT23

3 2

D34

HT-191NB_BLUE_0603

21

D25

HT-191NB_BLUE_0603

21

LID_SW#37

EC_ON37,41

51ON# 38,45

ON/OFF 37

ON/OFFBTN# 40,41

PWR_LED# 38

PWR_SUSP_LED37,38

HDD_LED#37

ODD_LED#38

KILL_SW# 29,37

WL_BT_LED#38

SDLED27

EMAIL# 37INTERNET# 37

CIR_LID_SW#41

S4_LID_SW#40

TV_OUT_EN# 37KSO1737,38

Page 40: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

+3V POWER +3V POWER

Power ON Circuit

FAN CONN. 2

FAN CONN. 1

- +RTC Battery

Battery mode Hibernation

CK409 Power Good Circuit

***

***

***

LA-1911 0.2

Power OK/Reset/RTC battery/Lid Switch/Int. KB

40 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

D_SET_S4

EN_DFAN2

FAN2

EN_FAN2

EN_DFAN1EN_FAN1

+RTCBATT

FAN1

+3V +3V

+3VS

+3VALW

+5VALW

+3VS

RTCVREF RTCVREF RTCVREF

RTCVREF

RTCVREF

RTCVREF

+12VALW

+5VALW

+3VS

+12VALW

+RTCVCC

CHGRTC

+RTCBATT

+3VS

+3VS

+3VS

VS

R6310_0603_5%

12

R464 33K_0402_5%1 2

R397 10K_0402_5%1 2

D52

RB751V_SOD323

2 1

R91

100K_0402_5%

C8910U_1206_10V4Z

1

2

R51100_0402_5%

1 2

G

D

SQ59@2N7002_SOT23

2

13

JP18

ACES_85205-0300

123

R126

100K_0402_5%

12

C194 0.1U_0402_10V6K1 2

C112

1U_0805_25V4Z1

2

C643

@1U_0805_16V7K

1

2

C641 1U_0805_16V7K1 2

D19

1N4148_SOT 231

2

R445

820K_0402_5%

12

U8NC7SZ14M5X

2

3

4

5

R48310K_0402_5%

1 2

U42

74LCX74

1234567

14131211100908

CD1#D1CP1SD1#Q1Q1#GND

VCCCD2#

D2CP2

SD2#Q2

Q2#R58

10K_0402_5%

12

C534

1000P_0402_50V7K

12

C56

0.1U_0402_16V4Z1

2

C

BE

Q7

FMMT619_SOT 231

2

3

C637

0.1U_0402_10V6K1 2

R625

10K_0402_5%1 2

R17110K_0402_5%

1 2

R466 100K_0603_1%1 2

BATT1

RTCBATT

12

R15410K_0402_5%

1 2

D20

1SS355_SOD323

12

C374

0.1U_0402_16V4Z

12

U39DSN74LVC14APWLE_T SSOP14

89

147

OI

PG

C5680.1U_0402_16V4Z

1 2

U39CSN74LVC14APWLE_T SSOP14

65

147

OI

PG

R16810K_0402_5%

1 2

C183 1U_0805_16V7K1 2

G

D

S

Q432N7002_SOT 23

2

13

C629

1U_0603_10V6K

1

2

C

BE

Q9

FMMT619_SOT 231

2

3

C5610.1U_0402_16V4Z

C54610U_1206_10V4Z

1

2

C525

1000P_0402_50V7K

12

R5310K_0402_5%

12

R6320_0603_5%

12

+

-U33BLM358AMX

5

67

84

+

-

U33ALM358AMX

3

21

84

R57 8.2K_0402_5%1 2

G

D

SQ422N7002_SOT 23

2

13

U9A

LM393M_SO8

3

21

84

+

-O

PG

C87

1000P_0402_50V7K

12

R89100_0402_5%

1 2

D44

1N4148_SOT 23

12

R127

100K_0402_5%

12

D32

1N4148_SOT 23

12

R85 10K_0402_5%1 2

G

D

S

Q17

2N7002_SOT 23

2

13

C86

1000P_0402_50V7K1

2

D41

BAS40-04_SOT23

1

23

C94

0.1U_0402_16V4Z1

2

R52 8.2K_0402_5%1 2

D45

1SS355_SOD323

12

R46310K_0402_5%

12

C191

0.1U_0603_50V4Z

12

D27

RB751V_SOD323

21

C808

@220P_0402_50V8K

12

R167

620K_0402_5%

12

G

D

S

Q122N7002_SOT 23

2

13

JP21

ACES_85205-0300

123

R465

68K_0402_5%

12SYS_PWROK 7,24,27

ON/OFFBTN# 39,41

S4_SATA37

S4_LATCH37

SYSON37,43,49

EN_DFAN237

FAN_SPEED237

EN_DFAN137

FAN_SPEED137

CK409_PWRGD# 15

S4_LID_SW#39

VCORE_PWRGD24,49,52

Page 41: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Need to check

LA-1911 0.2

CIR & Screws

Compal Electronics, Inc.

B

41 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

CIR_URXDCIR_USCLK

CIR_USCLK

CIR_URXD

CIR_RCRST#

CIR_USCLKCIR_URXD

RCIRRX

CIR_UTXD

CIR_RCVEN

CIR_RCVEN

CIR_RCRST#

CIR_UTXD

CIR_RCRST#CIR_RCVEN

RC_ON/OFFBTN

CIR_UTXD

CIR_GATING#

CIR_GATING#

+5V_CIR +5VALWP

B+

+5V_CIR

B+

+3VALW

+3VALW

+3VALW

+3VALW

+5V_CIR

+5V_CIR

+5V_CIR

+5V_CIR

+5V_CIR

B+

R563@47K_0402_5%

12

Q49 @MMBT3904_SOT23

2

3 1

R537

@10K_0402_5%

12

R555 @10K_0402_5%1 2

100K

100K

Q20@DTC115EKA_SOT23

2

1 3

R558

@10K_0402_5%

12

R536 @10K_0402_5%1 2

X8@4MHz

12

R568

@10K_1206_8P4R_5%

1 82 73 64 5

R259

@1M_0603_5%1

2

U19

@M34501M4-XXXFP

1 2

3

4

5

6

78

910

1112

13141516

17181920

VDD VSS

XIN

XOUT

CNVSS

RESET#

P21/AIN1P20/AIN0

D3/KD2/C

D1D0

P13/INTP12/CNTR

P11P10

P03P02P01P00

R258 @0_0402_5%1 2

C362

@0.1U_0402_16V4Z

1

2

C358

@1U_0805_25V4Z

D55

@RB751V_SOD323

2 1Q54 @MMBT3904_SOT23

2

3 1

R257 @100K_0603_5%1 2

R573@100K_0402_5%

1 2

R260 @100K_0603_5%1 2

R256 @10K_0402_5%1 2

C360 @1U_0603_10V6K1 2

R570

@10K_0402_5%

12

D56

@RB751V_SOD323

2 1

C361

@0.1U_0402_16V4Z

1

2

C762

@1U_0603_10V6K

1

2

R551 @10K_0402_5%1 2

C755 @10P_0402_50V8K1 2

G

D

SQ22@2N7002_SOT23

2

13

G

D

SQ56@2N7002_SOT23

2

13

U20

@MIC2951

1234 5

678OUT

SNSSHDNGND ERR#

TAPFBIN

C756 @10P_0402_50V8K1 2

L53

@0_0805_5%

1 2

C760@1U_0603_10V6K

1

2

R569@10K_0402_5%

12R567 @10K_0402_5%1 2

G

D

SQ51@2N7002_SOT23

2

13

Q53@SI2301DS 1P_SOT23

2

13

2

13

C754

@1U_0805_25V4Z

100K

100K

Q50

@DTC115EKA_SOT232

13

R564 @0_0402_5%1 2

R240

@10K_0402_5%

12

R571 @0_0402_5%1 2

Q48@MMBT3904_SOT23

2

3 1

EC_ON 37,39

EC_RSMRST#24,37

CIR_LID_SW#39

EC_UT XD37

EC_URXD37

EC_USCLK37

ON/OFFBTN# 39,40

EC_RCRST#38

EC_RCVEN38

CIR_GATING#38

RCIRRX38

Page 42: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

OZ168 DIRECT CD CONTROLLER +5VOZ TO +5VCD

OZ168 8MHz CRYSTAL OZ168 UNUSED PIN PULL UP

PROGRAMMING CLOCK GENERATOR

LA-1911 0.2

OZ-168 CD_PLAY & Programming Clock

Compal Electronics, Inc.

B

42 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

IDE_SDA2

IDE_SDIOR#IDE_SDIOW#

IDE_SDDACK#

OSC1 OSC2

OSC1OSC2

DM_ON

IDE_SDDREQIDE_IRQ15

GPIO_1GPIO_0

IDE_SDA1IDE_SDA0

IDE_SDCS3#IDE_SDCS1#

IDE_SDD3IDE_SDD2IDE_SDD1

IDE_SDD11IDE_SDD10

IDE_SDD15IDE_SDD14

IDE_SDD9

IDE_SDD0

IDE_SDD13IDE_SDD12

IDE_SDD8IDE_SDD7IDE_SDD6IDE_SDD5IDE_SDD4

FRDBTN#

STOPBTN#REVBTN#

PLAYBTN#

STOPBTN#PLAYBTN#

REVBTN#

GPIO_1GPIO_0

FRDBTN#

+5VOZ

+5VOZ

+5VCD

+5VCD

C752

@0.1U_0402_16V4Z

12

X3@8MHZ_16PF_7D08000014

C747@10P_0402_50V8K

12

RP125

@10K_8P4R_1206_5%

18273645

RP126

@10K_8P4R_1206_5%

18273645

C748@10P_0402_50V8K

12

C757

@0.1U_0402_16V4Z

12

C751

@0.1U_0402_16V4Z

12

U51@OZ168T-A1_TQFP 100

7678818386909597

248

1115182022

687066

6361

996

93

741288

72

2459

77798284879196981371014171921

697167

6462

10057394

751389

2360

4853555046

4752544945

2836353437

2925

3132

30

26

27

80

5657

38

51

9 44 58

16 33 65 85 92

3940

414243

HDD0HDD1HDD2HDD3HDD4HDD5HDD6HDD7HDD8HDD9HDD10HDD11HDD12HDD13HDD14HDD15

HDA0HDA1HDA2

HCS0HCS1

HDIOR#HDIOW#

HIORDY

HINTRQHDMARQHDMACK#

HIOCS16#

HRESET#HDASPN

CDD0CDD1CDD2CDD3CDD4CDD5CDD6CDD7CDD8CDD9

CDD10CDD11CDD12CDD13CDD14CDD15

CDA0CDA1CDA2

CCS0CCS1

CDIOR#CDIOW#

CIOCS16#CIORDY

CHINTRQCDMARQ

CHDMACK#

CRESET#CDASPN

HSYNCHBIT_CLKHDATA_OUTHDATA_INHACRSTN

SSYNCSBIT_CLK

SDATA_OUTSDATA_INSACRSTN

PAV_ENPLAY/PAUSEFFORWARDREWINDSTOP/EJECT

PCSYSTEM_OFFINTN

OSCIOSCO

RESET#

SDATA

SCLK

ISCDROM

MODE0MODE1

PAVMODE

PWR_CTL

VD

D

VD

D

VD

D

GN

DG

ND

GN

DG

ND

GN

D

GPIO[1]/VOL_UPGPIO[0]/VOL_DN

CSNINCNUDN

R557 @10K_0402_5%12

R565

@1M_0402_5%

R556 @10K_0402_5%12

L45@CHB1608G301_0603

1 2

C763

@0.1U_0402_16V4Z

12

L46@CHB1608G301_0603

1 2

IDE_IRQ1523,33

IDE_SDA224,33

IDE_SDCS1#24,33IDE_SDCS3#24,33

IDE_SDIOR#24,33IDE_SDIOW#24,33

IDE_SDIORDY24,33

IDE_SDDACK#24,33IDE_SDDREQ24,33

IDE_SDA124,33IDE_SDA024,33

IDE_SDD[0..15]24,33

SIDERST#24,33

Page 43: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PROPRIETARY NOTE

+3VALW TO +3V

+3VALW TO +3VS +5VALW TO +5VS

+5VALW TO +5V

+2.5V TO +2.5VS

***

** **

***

LA-1911 0.2

POWER CONTROL CKT

Compal Electronics, Inc.

B

43 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

SUSPSUSP

5VS_GATE

SUSPSUSP

SYSON# SYSON#

SYSON#

5VS_GATE

5VS_GATE

SUSP

SYSON#

SYSON_ALW

SYSON_ALW

SYSON

+3VS

+12VALW

+5VALWP

+5VALWP +5VS

+5VALWP +5V

+5VS+3VS

+3V +5V

+5VALWP

+3VALW

+2.5V+2.5VS

+2.5VS

+12VALW

+3VALW

+3V

G

D

S Q232N7002_SOT 23

2

13

C176

0.1U_0402_16V4Z1

2

H12H_S315D142

1

R121

@1M_0402_5%

12

R123100K_0402_5%1 2

H16H_C197D98

1

C630

0.1U_0402_16V4Z1

2

R613

10K_0402_5%

12

PJP15

PAD-OPEN 2x2m

21

C196

1U_0805_25V4Z

1

2

C7254.7U_1206_16V4Z

1

2

C122

1U_0805_25V4Z

1

2

H20H_S315D142

1

H27H_C55D55N

1

H24H_S315D142

1

R52610K_0402_5%

12

R125100K_0402_5%

1 2

C177

10U_1206_10V4Z

1

2

H1H_C276D181

1

H18H_C228D165

1

G

D

S Q462N7002_SOT 23

2

13

H28H_C55D55N

1

G

D

S Q382N7002_SOT 23

2

13

R26610K_0402_5%

12

PJP14

PAD-OPEN 2x2m

21

H23H_O268X228D205X165

1

C3684.7U_1206_16V4Z

1

2

H13H_C276D181

1

G

D

S

Q472N7002_SOT 23

2

13

H26H_C276D181

1

U7

SI4800DY_SO8

1234

8765

SSSG

DDDD

R516470_0805_5%

12

G

D

S Q402N7002_SOT 23

2

13

G

D

S Q392N7002_SOT 23

2

13

H9H_S315D142

1

C380

0.1U_0402_16V4Z1

2

H8H_C142D142N

1

H6H_C276D142

1

H4H_S315D142

1

G

D

S Q102N7002_SOT 23

2

13

C625

1U_0805_25V4Z

1

2

C623

4.7U_0805_10V4Z

12

H2H_C276D181

1

PJP13

PAD-OPEN 2x2m

21

H22H_S315D142

1

H10H_C276D142

1

H17H_S315D142

1

U6

SI4800DY_SO8

1234

8765

SSSG

DDDD

C715

4.7U_1206_16V4Z

1

2

C186

10U_1206_10V4Z

1

2U22

SI4800DY_SO8

1234

8765

SSSG

DDDD

U41

SI4800DY_SO8

1234

8765

SSSG

DDDD

C724

1U_0805_25V4Z

1

2

H29H_SMDC157

1

G

D

S Q132N7002_SOT 23

2

13

H25H_C276D181

1

R612

10K_0402_5%

12 G

D

S

Q242N7002_SOT 23

2

13

H7H_SMDC138

1

C379

1U_0805_25V4Z

1

2

R124

@1M_0402_5%

12

H21H_S315D142

1

R457470_0805_5%

12

U49

SI4800DY_SO8

1234

8765

SSSG

DDDD

R452470_0805_5%

12

C640

4.7U_0805_10V4Z

12

C178

0.1U_0402_16V4Z1

2

H19H_S276D110

1

C743

0.1U_0402_16V4Z1

2

R272470_0805_5%

12

C133

10U_1206_10V4Z

1

2

H30H_SMDC157

1

C386

4.7U_1206_16V4Z

1

2

H3H_C236D236N

1

H11H_C276D181

1

H5H_S315D142

1

H15H_C197D98

1

R450470_0805_5%

12

H14TC197S276D110

1

C205

10U_1206_10V4Z

1

2SYSON37,40,49 SUSP#31,33,37,38,49,51

SUSP19,31,50

Page 44: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PROPRIETARY NOTE

+3VALW POWER

+3VALW POWER

+3VALW POWER+3VALW POWER

+3VALW POWER

**Remove +5VCD

***

LA-1911 0.2

Point and Capacitance

Compal Electronics, Inc.

B

44 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

+3V

+3VALW +1.5VS

+3VALWP

+3V+3VALW

+3VS

+3VALW

+3VALW+3VALW

+3VALW

+1.5VSS

+5VCD

C795

@1U_0603_10V6K

1

2

R606

0_0402_5%1

2U55D

SN74LVC14APWLE_T SSOP14

89

147

OI

PG

C405

4.7U_0805_10V4Z

12

CF6SMD40M80

1

CF13SMD40M80

1

FD1FIDUCAL

1

CF7SMD40M80

1

C407

4.7U_0805_10V4Z

12

R60510K_0402_5%

12

CF4SMD40M80

1

CF30SMD40M80

1

CF2SMD40M80

1

U55C

SN74LVC14APWLE_T SSOP14

65

147

OI

PG

CF5SMD40M80

1

C784

4.7U_0805_10V4Z

12

CF20SMD40M80

1

FD2FIDUCAL

1

CF25SMD40M80

1

CF28SMD40M80

1

R604

0_0402_5%

12

CF17SMD40M80

1

CF3SMD40M80

1

CF16SMD40M80

1CF21SMD40M80

1

CF1SMD40M80

1

CF18SMD40M80

1

FD3FIDUCAL

1

C397

4.7U_0805_10V4Z

12

CF19SMD40M80

1

C406

4.7U_0805_10V4Z

12

C782

0.1U_0402_16V4Z1

2

C402

4.7U_0805_10V4Z

12

FD6FIDUCAL

1

CF12SMD40M80

1

CF8SMD40M80

1

CF9SMD40M80

1

C396

4.7U_0805_10V4Z

12

C794

@0.1U_0402_16V4Z

12

CF32SMD40M80

1

CF11SMD40M80

1

CF24SMD40M80

1

FD4FIDUCAL

1

U55A

SN74LVC14APWLE_T SSOP14

21

147

OI

PG

CF31SMD40M80

1

FD5FIDUCAL

1

CF27SMD40M80

1CF23SMD40M80

1 C395

4.7U_0805_10V4Z

12

CF22SMD40M80

1

U55B

SN74LVC14APWLE_T SSOP14

43

147

OI

PG

CF10SMD40M80

1

CF14SMD40M80

1

C404

4.7U_0805_10V4Z

12

CF29SMD40M80

1

G

D

S

Q582N7002_SOT 23

2

13

CF15SMD40M80

1

CF26SMD40M80

1

C394

4.7U_0805_10V4Z

12

C403

4.7U_0805_10V4Z

12

V_ON 49

VS_ON# 50VS_ON 49,51

Page 45: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

(120mA,20mils ,Via NO.= 1)

(6A,240mils ,Via NO.= 12)

3.3V

(2A,80mils ,Via NO.= 4)

(150mA,40mils ,Via NO.= 2)

(12A,480mils ,Via NO.=24)

(6A,240mils ,Via NO.= 12)

(6A,240mils ,Via NO.= 12)

(6A,240mils ,Via NO.= 12)

3.3VVin Detector

High 18.764 17.901 17.063Low 17.745 16.903 16.038

Precharge detector15.34 15.90 16.4813.13 13.71 14.20

6.0V

3.3V

INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE

CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT ASAUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NORTHE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY

SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE

THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,

(2A,80mils ,Via NO.= 4)

LA-1911 0.2

DCIN & DETECTOR

45 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

N2

N1CHGRTCP

PACIN

PACIN

N3

VIN

VS

RTCVREF

CHGRTC

+12VALWP +12VALW

+1.5VSP +1.5VS

BATT+

+1.25VS+1.25VSP

+VCCVIDP

+2.5VP +2.5V

+5VALW

+3VALWP

+5VALWP

+3VALW

+VGA_COREP +VGA_CORE

VIN

RTCVREF

VIN

VS

VS

RTCVREF

B+VIN

VL

+5VALWP

+CPUVID

+VTT_GMC HP +VTT_GMCH

+1.5VS +1.5VSS

PR10

33_1206_5%

12

PU1A

LM393M_SO8

3

21

84

+

-O

PG

PC12

1U_0805_25V4Z

12

PJP7

PAD-OPEN 4x4m

1 2

PJP11

PAD-OPEN 4x4m

1 2

PC80.1U_0603_25V7K

12

PJP9

PAD-OPEN 2x2m

2 1

PJP1PAD-OPEN 4x4m1 2

PR21

10K_0603_5%

12

PD3

1N4148_SOD80

12

PF112A_65VDC_451012

21

PD2

RLZ4.3B_LL34

12

PQ1TP0610T_SOT23

13

2

PC9

1000P_0603_50V7K

12

PJP4

PAD-OPEN 3x3m

1 2

PD8

RLZ16B_LL34

21

100K

100K

PQ3DTC115EKA_SOT23 2

13

PR14

22K_0603_5%

1 2

PR13

100K_0603_5%

12

PC2100P_0603_50V8J

12

PD7

RB715F_SOT323

2

31

PC1

1000P_0603_50V7K

12

PR17499K_0603_1%

12

PD9

RLZ6.2C_LL34@

21

PJP10

PAD-OPEN 4x4m

1 2

PD6

RLZ3.6B_LL34

12

PR19

200_0603_5%

1 2PC10

1000P_0603_50V7K

12

PC31000P_0603_50V7K

12

PR20

499K_0603_1%

12

PU1BLM393M_SO8

5

67

84

+

-O

PG

PC5

1000P_0603_50V7K

12

PR2

5.6K_0603_5%

12

PC1310U_1206_10V4Z

12

PR1 1M_0603_1%

1 2

PR710K_0603_5%

12

PC11

0.1U_0603_16V7K

12

PC7

0.22U_1206_25V7K

12

PD4

RB751V_SOD323

12

PR22215K_0603_1%

12

PJP8

PAD-OPEN 4x4m

1 2

PR15 10K_0603_5%

1 2

PC60.1U_0603_25V7K

12

PR111K_1206_5%

1 2

PL1

C8B BPH 853025_2P

1 2

G

D

S

PQ22N7002_SOT 23

2

13

PU2S-81233SGUP-T1_SOT89

2

1

3 2

1

3

PR121K_1206_5%

1 2

PC4100P_0603_50V8J

12

PR3

84.5K_0603_1%

12

PD1

EC10QS04_SOD106

12

PJP5

PAD-OPEN 4x4m

1 2

PJP2

PAD-OPEN 4x4m

1 2

PJP6

PAD-OPEN 2x2m

2 1

PJP3PAD-OPEN 4x4m1 2

PR91K_1206_5%

1 2

PR8

10K_0603_5%

12

PR41K_0603_5%

1 2

PD5

1N4148_SOD80

12

PR16 1M_0603_1%

12

PR23 47K_0603_5%

12

PR18

200_0603_5%

12

PR5 22K_0603_5%

1 2

PR6

20K_0603_1%

12

1

2

GGGG

PCN1

SINGA_2DC-S113L200

1

23456

51ON#38,39

ACIN 24,37,38

PACIN 47,48

ACON47

MAINPWON46,48

Page 46: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

PH2 near main Battery CONN :

Recovery at 44 degree CBAT. thermal protection at 78 degree C

Recovery at 44 degree CCPU thermal protection at 84 degree CPH1 under CPU botten side :

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE

CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT ASAUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NORTHE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY

SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE

THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

LA-1911 0.2

BATTERY CONN / OTP

46 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

TM_REF2

TM_REF1

EC_SMCA

AB/I

EC_SMDA

ALI/NIMH#

TS_A

VL VS

VL

VL

BATT+

VMB

+3VALWP

+3VALWP

+5VALWP

VL

VLVL

PR32

3.32K_0603_1%

12

PF2 15A_65VDC_451012

21

PC19

0.22U_0805_16V7K_V2

12

PR31

1K_0603_5%

12

PR41

3.48K_0603_1%

12

PR35

100K_0603_1%

12

PD15

1SS355_SOD323

12

PH110KB_0603_1%_TH11-3H103FT

12

PR34

25.5K_0603_1%

1 2

PR39

14.7K_0603_1%

1 2

PD13

BAS40-04_SOT23@

1

3 2

PR2647K_0603_5%

1 2

PR241K_0603_5%

12

PR3747K_0603_1%

12

PR33

100K_0603_1%

12

PC17

0.22U_0805_16V7K_V2

12

PC140.1U_0603_25V7K

12

PC18

1000P_0603_50V7K

12

PC20

1000P_0603_50V7K

12

PC151000P_0603_50V7K

12

PR29

100_0603_5%

12

PU3B

LM393M_SO8

5

67

84

+

-O

PG

PD11

1SS355_SOD323

12

PD14

BAS40-04_SOT23@

1

32

PR27

47K_0603_1%

1 2

PD10

BAS40-04_SOT23@

1

3

2

100K

100K

PQ4

DTC115EKA_SOT23

2

13

PU3A

LM393M_SO8

3

21

84

+

-O

PG

PR40

100K_0603_1%

12

PH2

10KB_0603_1%_TH11-3H103FT

12

PR25

47K_0603_1%

12

PR42100K_0603_1%

12

PL2

C8B BPH 853025_2P

1 2

PR38

47K_0603_1%

1 2

PR28100_0603_5%

1

2

PCN2

SUYIN_20175A-09G1_M9P

1

3456

91011

2

78

BATT+

IDB/ITS

SMD

GND-GNDGND

BATT+

SMCGND-

PD12

BAS40-04_SOT23@1

3

2

PC160.01U_0603_50V7K

12

PR361K_0603_5%

12

PR30

16.9K_0603_1%

1 2

MAINPWON 45,48

ALI/MH# 37

BATT_TEMPA 37

EC_SMB_DA1 37,38

EC_SMB_CK1 37,38

Page 47: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE

CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT ASAUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NORTHE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY

SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE

THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

Iadp=0~5.8A

CC=0.5~2.7ACV=16.8V(12 CELLS LI-ION)

IREF=0.73~3.3VIREF=1.31*Icharge

4.2V

OVP voltage : LI

(BAT_OVP=0.1111 *VMB)4S3P : 17.4V--> BATT_OVP= 1.935V

LA-1911 0.2

CHARGER

47 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

CSACON

CS

N18

ACOFF#

PACIN

ACOFF#

LXCHRG

ACON

VIN

VIN

BATT+

P2 P3 B+ B++

VMB

+3VALWP

+5VALWP

PC23

4.7U_1210_25V6K

12

PR50 100K_0603_5%

12

PR64

143K_0603_0.1%

12

PC33

0.1U_0603_16V7K

12

PC280.1U_0603_25V7K

1 2

PQ5SI7447DP_SO8

32

4

1

5

PU5A

LM358A_SO8

3

21

84

+

-0

PG

100K

100K

PQ11DTC115EKA_SOT23

2

13

PR43

0.01_2512_1%

12

PC32

1500P_0603_50V7K

1 2

PR66499K_0603_1%

12

PC29

0.1U_0603_16V7K

12

PC38

0.01U_0603_50V7K

12

PD17

RB051L-40_SOD106

12

PR45

200K_0603_1%

12

PC310.1U_0603_25V7K

1 2

PR67

2.2K_0603_5%

12

PR184

95.3K_0603_0.1%

12

PR47

47K_0603_5%

1 2

100K

100K

PQ9DTC115EKA_SOT23

2

13

PR58

0.02_2512_1%

1 2

PC30

1000P_0603_50V7K

1 2

PR48

150K_0603_1%

12

PR46

10K_0603_5%

1 2

PR54

10K_0603_5%

1 2

PC25

0.1U_0603_25V7K

1 2

PU4

MB3887_SSOP 24

1

2

3

4

24

23

22

21

5

6

7

8

9

10

11

12

20

19

18

17

16

15

14

13

-INC2

OUTC2

+INE2

-INE2

+INC2

GND

CS

VCC(o)

FB2

VREF

FB1

-INE1

+INE1

OUTC1

OUTD

-INC1

OUT

VH

VCC

RT

-INE3

FB3

CTL

+INC1

PR55

1K_0603_5%

1 2

PR6247K_0603_5%

12

PC22

4.7U_1210_25V6K

12

PR49

0_0603_5%

12

PC21

4.7U_1210_25V6K

12

PR60

47K_0603_5%

1 2

PQ7

SI4825DY_SO8

1234

8765

SSSG

DDDD

PQ6

SI4825DY_SO8

1234

8765

SSSG

DDDD

PR57 205K_0603_1%

1 2

PR59 10K_0603_5%

12

PL4

22UH_SPC-1205P-220A_2.8A_20%

1 2

PR53

10K_0603_1%

12

PC37

@0.1U_0603_16V7K

12

PC34

4.7U_1210_25V6K

12

PD16

1SS355_SOD323

1 2

PR68

105K_0603_0.5%

12

PR63

95.3K_0603_0.1%

12

PC36

4.7U_1210_25V6K

12

PR44

10K_0603_5%

12

100K

100K

PQ12DTC115EKA_SOT23

2

13

PR61

100K_0603_1%

12

PR52

33.2K_0603_1%

12

PC26

0.1U_0603_16V7K

12

PL3

C8B BPH 853025_2P

1 2

PR513K_0603_5%

1 2

PC240.022U_0603_25V7K

1 2

PR65340K_0603_1%

12

PC27

4700P_0603_50V7K

1 2

PC35

4.7U_1210_25V6K

12

PR5668K_0603_5%

1 2

PQ8SI4835DY_SO8

365 7 8

2

4

1

G

D

S

PQ10

2N7002_SOT 23

21

3

ACOFF 37

IREF37

BATT_OVP37

FSTCHG37

ADP_I37,51

ACON45

PACIN45,48

Page 48: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE

CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT ASAUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NORTHE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY

SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE

THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,

+3.3V Ipeak = 6.66A ~ 10A+5V Ipeak = 6.66A ~ 10A

INC.

LA-1911 0.2

5V/3.3V/12V

48 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

FLYBACKSNB

PDH31

PDH51

BST51

PLX3

PDH5

PD

H3

CSH5

CSH3

PLX5

PDL3

PDL5

BST31

N4

+5VALWP

VS

B+++

B+++

VL

+12VALWP

B+

+3VALWP

VS

2.5VREF

VL

PC49

4.7U_1206_16V4Z

12

PR700_0603_5%

1 2

PR77

3.57K_0603_1%

12

PL6

10UH_SPC-1205P-100_4.5A_20%

12

PC51

47P_0603_50V8J

12

PC42

4.7U_1210_25V6K@

12

PR72

0.012_2512_1%

12

+PC58

150U_D_6.3VM@

1

2

PT1

10uH_SDT-1205P-100-118_5A_20%

14

32

PR80

47K_0603_5%

12

PC394.7U_1210_25V6K

1 2

PC59

100P_0603_50V8J

12

PR8247K_0603_1%

12

PC50

47P_0603_50V8J

12

+PC57

150U_D_6.3VM

1

2

PC55

4.7U_1206_16V4Z

12

PC56680P_0603_50V8J

12

PC54

100P_0603_50V8J

12

PC480.1U_0603_25V7K

12

PR71

0_0603_5%

1 2

PC40

470P_0805_100V7K 1

2

+PC52

150U_D_6.3VM

1

2

PC41

0.1U_0603_25V7K

1 2

PR81

10K_0603_1%

12

PR79

10K_0603_1%

12

PR73

1M_0603_1%

12

PC474.7U_1206_16V4Z

12

PD18

EC11FS2_SOD106

12

PC61

0.047U_0603_50V4Z

12

SI4814DY_SO8~D

PQ13

28

35

17

46D1

G1

G2S1/D2

D1S1/D2

S2S1/D2

PR74

2M_0603_5%

12

PD19

DAP202U_SOT 323

1

3 2

PD22

EP10QY03

21

PC45

4.7U_1210_25V6K

12

PC43

4.7U_1210_25V6K

12

SI4814DY_SO8~D

PQ14

28

35

17

46D1

G1

G2S1/D2

D1S1/D2

S2S1/D2

PR78

10.5K_0603_1%

12

PR7610K_0603_5%

1 2

PC60

0.047U_0603_50V4Z

12

PD20

1SS355_SOD323

12

PU6

MAX1902

2624

25

27

123

10

8

451816171920141312159611

23

7

28

2122

LX3DL3

BST3

DH3

CSH3CSL3FB3SKIP#

GN

D

12OUTVDD

BST5DH5LX5DL5

PGNDCSH5CSL5

FB5SEQREF

SYNCRST#

SHDN#

TIME/ON5

RUN/ON3

VL

V+

PD21

EP10QY03

21

PC46

4.7U_1210_25V6K@

12

PR69 22_1206_5%

12

+ PC53

150U_D_6.3VM@

1

2

PC44

0.1U_0603_25V7K

1 2

PL5

HCB4532K-800T90_1812

1 2

PR75

0.012_2512_1%

12

MAINPWON 45,46

PACIN45,47

Page 49: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE

CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT ASAUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NORTHE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY

SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE

THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

+2.5V

PRESCOTT

NORTHWOOD

GMCH_SEL=0

GMCH_SEL=1

VTT_GMCH=1.225V

VTT_GMCH=1.45V

+1.45V/+1.225V

*****

LA-1911 0.2

DDR_2.5V/VTT_GMCH

49 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

B+

+5VALWP

+VTT_GMC HP

+2.5VP

PR8815K_0603_1%

12

PR89 @0_0603_5%

1 2

PQ17FDS6672A_SO8

365 7 8

2

4

1

PC681U_0603_10V6K

12

PR9110K_0603_1%

12

PL7

HCB4532K-800T90_1812

1 2

PC70

0.1U_0603_25V7K

12

+PC73150U_D2_6.3V

1

2

PC74

0.22U_0805_16V7K

12

PR95220K_0603_1%

12

PR179 0_0603_5%12

PR9210K_0603_1%

12

PD26EP10QY03

21

EC31QS04

PD25

12

PR9342.2K_0603_1%

12

+PC71

220U_D2_4V

1

2

PL82.2UH_SPC-1205P-2R2B_13A_30%

1 2

PR178 0_0603_5%@1 2

PC62

4.7U_1210_25V6K

12

+PC72

220U_D2_4V

1

2

PR84

20_0603_5%

12

PR9410K_0603_1%

12

PC65

4.7U_1210_25V6K

12

PR830_0603_5%

12

PQ15

IRF7821_S08

134

8765

2

SSG

DDDD

S

PL95UH_SPC-06704-5R0_2.9A_30%

1 2

PR96

100K_0603_1%

12

PR180 0_0603_5%1 2

PD24

EP10QY03

21

PR97

100K_0603_1%

12

PR860_0603_5%

1 2

PD23

DAP202U_SOT 323

1

32

PC664.7U_1210_25V6K

12

PC64

4.7U_1210_25V6K

12

G

D

SPQ182N7002_SOT 23

2

13

PR177 0_0603_5%

@

1 2

PC67

1U_0805_25V4Z

12

PC63

4.7U_1206_16V4Z

12

SI4814DY_SO8

PQ16

28

35

17

46D1

G1

G2S1/D2

D1S1/D2

S2S1/D2

PR850_0603_5%

1 2

PU7

MAX1845EEI_QS OP28

15

19

14

16

21

9

6

423

11

26

27

13

24

22

7

2 12

3

8 10

1720

5

28

25

18

1 OUT2

BST2

FB2

CS2

VDD

UV

P

SK

IP

V+

GN

D

ON1

DH1

LX1

ILIM2

DL1

VC

C

PGOOD

FB1 ON2

ILIM1

OV

P

RE

F

LX2DL2

TON

CS1

BST1

DH2

OUT1

PC690.1U_0603_25V7K

12

PR87

4.53K_0603_1%

12

PR90 @0_0603_5%

12 SYSON 37,40,43

GMCH_SEL52

VCORE_PWRGD24,40,52

VCORE_ENLL5,52

SUSP#31,33,37,38,43,51

VS_ON44,51

V_ON 44

Page 50: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE

CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT ASAUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NORTHE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY

SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE

THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

POWER_SEL=1

NV33M/NV34M

VOUT=1.15V

POWER_SEL=0 VOUT=1.15V

+1.5V

**

**

PR103 PR106

NV31M

NV33M

NV34M

4.53K 9.09K

3.92K 0K

3.92K 0K

NV31M

VOUT=1.0V

VOUT=1.2V

+1.15V/1.0V

LA-1911 0.2

1.5V/VGA_CORE

50 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

SUSP1

SUSP

VS_ON#

SUSP1

+5VALW

+3VALW

+VGA_COREP

+1.5VSP

PR100220K_0603_1%

12

+ PC79

220U_D2_4VM

1

2

PU9

MAX1954EUB_10UMAX

7

10

6

3

8

2

9

4

1

5

PGND

BST

DL

FB

DH

COMP

LX

GND

HSD

IN

+PC85

220U_D2_4VM @

1

2

PR1019.09K_0603_1%

12PR181 0_0603_5%

12

PR1033.92K_0603_1%

12

PC75

22U_1210_6.3V6M

12

PC81390P_0603_50V7K

12

PR998.06K_0603_1%

12

PL10

2.2UH_PLFC1235P-2R2A_6A_30%

1 2

PC770.1U_0603_16V7K

12

PD27EP10QY03

21

PR980_1206_5%

12

SI4814DY_SO8

PQ19

28

35

17

46D1

G1

G2S1/D2

D1S1/D2

S2S1/D2

PC840.1U_0603_16V7K

12

PR104180K_0603_1%

12

G

D

S

PQ22

2N7002_SOT 23

2

13

PR105

9.09K_0603_1%

12

G

D

S

PQ23

2N7002_SOT 23

2

13

PL112.2UH_SPC-1205P-2R2B_13A_30%

1 2

PU8

MAX1954EUB_10UMAX

7

10

6

3

8

2

9

4

1

5

PGND

BST

DL

FB

DH

COMP

LX

GND

HSD

IN

G

D

S

PQ20

2N7002_SOT 23

21

3

SI4814DY_SO8

PQ21

28

35

17

46D1

G1

G2S1/D2

D1S1/D2

S2S1/D2

PC88390P_0603_50V7K

12

PC83

22U_1210_6.3V6M

12

PC82

22U_1210_6.3V6M

12

PR1060K_0603_5%

12

+PC78

220U_D2_4VM @

1

2

+ PC86

220U_D2_4VM

1

2

PR1020_1206_5%

12

PC8010P_0603_50V8J

12

PD28EP10QY03

21

PR182 @0_0603_5%12

PR107

100K_0603_5%

12

PC8715P_0603_50V8J

12

PC76

22U_1210_6.3V6M

12

POWER_SEL16

SUSP19,31,43

VS_ON#44

Page 51: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE

CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT ASAUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NORTHE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY

SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE

THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

LA-1911 0.2

DDR_1.25V/THROTTLING

51 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

FB

_VD

D+

REMOTE SENSE

VL

VL

VS

+2.5VP

+3VALWP

+1.25VSP

+3VALWP

G

D

SPQ26

2N7002_SOT 23

2

13

G

D

S

PQ242N7002_SOT 23

2

13

G

D

S

PQ252N7002_SOT 23

2

13

PR121100K_0603_5%

12

PU10ALM393M_SO8

3

21

84

+

-O

PG

PC94

0.1U_0603_16V7K

12

PC960.1U_0603_16V7K

12

PR109

365K_0603_1%

12

PR118

105K_0603_0.5%

12

PR114

5.1_0603_5%

1 2

PR119

1K_0603_5%

1 2

PR116105K_0603_0.5%

12

PC98

470P_0603_50V8J

1 2

PR1130_1206_5%

12

PR117 100K_0603_5%

1 2

PR112

100K_0603_1%

12

PC901000P_0603_50V7K

12

PC89

0.1U_0603_25V7K

12

PR120

@0_0603_5%

1 2

PR111 249K_0603_1%

1 2

PR183

0_0603_5%1 2

PR108 1M_0603_1%

1 2

PR115

22K_0603_5%

1

2

PC934.7U_1206_16V4Z

12

PU11

CM3718

2

4 5

1 8763 GND

VREF VFB

VIN PVINLX

PGNDSD

PC9110P_0603_50V7K

12

PC97

1U_0603_10V6K

12

PC921U_0603_10V6K

12

PL122.2UH_SPC-06703-2R2_20%

1 2

+ PC95220U_D2_4VM

1

2

PR110 64.9K_0603_1%

1 2

PU10B

LM393M_SO8

5

67

84

+

-O

PG

ADP_I37,47

H_PROCHOT# 5,7

SUSP#31,33,37,38,43,49

VS_ON44,49

Page 52: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

Frequency Select

1. When mode control signal ishigh/ low, the VR will operate toNorthwood/ Prescott load line(Northwood="0",Prescott="1") 2. VID5(12.5) should be pulledhigh, when the VR operates toNothwood load line.

Panasonic ERTJ0EV334J (0402)Locate this NTC resistor onPCB between phase 2 and 3for thermal compensation.

Place near +VCC_CORE output capacitor

RemoteSensing

Battery FeedForward

Place close to IC

INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE

CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT ASAUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NORTHE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY

SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE

THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,LA-1911 0.2

CPU_CORE_Controller

52 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

1.2VDD

+VCCVIDP

+3VALWP

+5VALWP

B+

+5VALWP

+CPU_CORE

+5VALWP

+5VALWP

+3VALWP

PC991U_0603_10V6K

12

PC1084.7U_1206_16V4Z

12

PR136

10K_0603_1%

12

PR154

0_0603_5%

12

PR150@0_0603_5%

12

PC104

1000P_0603_50V7K@

12

PR1370_0603_5%@

12

PR13121.5K_0603_1%

12

PU13

MIC5258_SOT23-5

4

5

3

1

2

PG

OUT

EN

IN

GND

PR1421M_0603_1%

12

G

D

S

PQ292N7002_SOT 23

2

13

PR149

0_0603_5%12

PR134 0_0603_5%@1 2

PR12280.6K_0603_1%

12

G

D

S

PQ302N7002_SOT 23

2

13

PR148

27K_0603_5% 1

2

PU12

ISL6247_MLFP40

32

39123456

25

31

26

20

24

30

27

22

36

17

37

15

10

13

11

16

18

8

34

38 14

9

23

29

28

21

35

40

19

12

7

33

VCC

PGOODVID4VID3VID2VID1VID0VID12.5

PWM1

PWM4

PWM2

PWM3

ISEN1+

ISEN4+

ISEN2+

ISEN3-

FS

VSEN

DRSV

COMP

OCSET

FB

SOFT

VDIFF

VRTN

OFS

ENLL

VR-TT# NC

DSV

ISEN1-

ISEN4-

ISEN2-

ISEN3+

DSEN#

NTC

GND

GND

RAMPS

DRSEN

PR156100K_0603_5%

12

PR153

22K_0603_5%

12

PR14132.4K_0603_1%

12

PR1475.1K_0603_1% 1

2

PU5B

LM358A_SO8

5

67 +

-0

PR1240_0603_5%

12

PC10322P_0603_50V7K

12

PR1260_0603_5%

12

G

DSPQ27

2N7002_SOT 23

2

13

PQ28

TP0610T_SOT23

13

2

PC105@220P_0603_50V8J

12

PR151

0_0603_5%12

PR145340K_0603_1%

12 PC106

0.1U_0603_16V7K

12

PC1094.7U_1206_16V4Z

12

PC1011000P_0603_50V7K

12PR133

100K_0603_1%

12

PR152

@0_0603_5%

12

PR123 10K_0603_5%

12

PC102

100P_0603_50V8J

12

PR140

10K_0603_5%@

12

PR135

0_0603_5%@12

PR1392.26K_0603_1%

1 2

PR155

100K_0603_5%

12

PC107

1U_0603_10V6K

12

PC100

0.047U_0603_25V7M

12PR127

0_0603_5%@

12

PR146

0_0603_5%

12

PQ31MMBT3904_SOT23

2

31

PR13220K_0603_1%

1 2

PR138

@330K_0402_5% 1

2

PR144

45.3K_0603_1%

12 PR143

16.2K_0603_1%

12

PR129

475_0603_1%

12

PR130

69.8K_0603_1%

12

PR125 0_0603_5%

1 2

PWM1 53

ISEN1+ 53ISEN1- 53

PWM2 53

ISEN2+ 53ISEN2- 53

PWM3 54

ISEN3+ 54ISEN3- 54

ISEN4+ 54

PWM4 54

ISEN4- 54

VCORE_PWRGD 24,40,49

VCCSENSE 5

VSSSENSE 5

VCORE_ENLL5,49

H_VID45H_VID35H_VID25H_VID15H_VID05H_VID55

VR_ON37H_BOOTSELECT4

GMCH_SEL49VID_PWRGD5

Page 53: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

Panasonic ETQ-P4LR56WFC

Panasonic ETQ-P4LR56WFC

Local TransistorSwtich Decoupling

Local TransistorSwtich Decoupling

INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE

CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT ASAUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NORTHE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY

SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE

THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,

**

**

LA-1911 0.2

CPU_CORE_Power stage 1

53 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

PHASE2

PHASE1

N6

N8

N5

N7

CPU_B+

+5VALWP

+CPU_CORE

CPU_B+

CPU_DRIVE_EN

B+

PC1124.7U_1210_25V6K

12

PL15

0.56UH_ETQP4LR56WFC_21A_20%

1 2

PR161

32.4K_0603_1%

12

PR1633_0603_5%

12

PC126

0.01U_0603_50V7K

12

PR158

0_0603_5%

12

PC110

0.22U_0805_16V7K

12

PL13

C8B BPH 853025_2P

1 2

PR1601_0603_5%

12

PQ33

IRF7811W_S08

134

8765

2

SSG

DDDD

S

PQ37

IRF7811W_S08

134

8765

2

SSG

DDDD

S

PC117

1U_0805_25V4Z 12

PC121

4.7U_1210_25V6K

12

PL14

0.56UH_ETQP4LR56WFC_21A_20%

1 2

PC143

470P_0402_50V7K

1

2

PU14

ISL6207CB-T_SO8

2

3

6

7

54

8

1

BOOT

PWM

VCC

EN

LGATEGND

PHASE

UGATE

PC120

0.22U_0805_16V7K

1 2

PQ34

SI4362_SO8

134

8765

2

SSG

DDDD

S

PQ39

SI4362_SO8

134

8765

2

SSG

DDDD

S

PC144

0.1U_0603_25V7K

12

+ PC149220U_25V_M

1

2

PC1114.7U_1210_25V6K 1

2

PC119

0.01U_0603_50V7K

12

PQ38

SI4362_SO8

134

8765

2

SSG

DDDD

S

PQ35

SI4362_SO8

134

8765

2

SSG

DDDD

S

PR159499K_0603_1%

12

PC1234.7U_1210_25V6K

12

PR166

32.4K_0603_1%

12

PH3

820_0603_5%

12

PQ32IRF7811W_S08

134

8765

2

SSG

DDDD

S

PQ36

IRF7811W_S08

134

8765

2

SSG

DDDD

S

PC113

4.7U_1210_25V6K

12

PH4

820_0603_5%

12

PR164

499K_0603_1%

12

PC142

0.1U_0603_25V7K

12

PR1573_0603_5%

12

PR165

1_0603_5%

12

PC141

470P_0402_50V7K

1

2

PC122

4.7U_1210_25V6K

12

PU15

ISL6207CB-T_SO8

2

3

6

7

54

8

1

BOOT

PWM

VCC

EN

LGATEGND

PHASE

UGATE

PC125

1U_0805_25V4Z 1

2

EC31QS04

PD30

12

PC116

0.1U_0603_16V7K 12

PWM1 52

PWM2 52

ISEN1-52ISEN1+52

ISEN2-52ISEN2+52

Page 54: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

A

A

B

B

C

C

D

D

1 1

2 2

3 3

4 4

Panasonic ETQ-P4LR56WFC

Local TransistorSwtich Decoupling

Panasonic ETQ-P4LR56WFC

INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE

CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT ASAUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NORTHE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY

SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE

THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,

**

**

LA-1911 0.2

CPU_CORE_Power stage 2

54 57Friday, August 08, 2003

Compal Electronics, Inc.Title

Size Document Number Rev

Date: Sheet of

PHASE4

PHASE3

N10

N12

N9

N11

+5VALWP

CPU_DRIVE_EN

CPU_B+

CPU_B+

+CPU_CORE

PC145

470P_0402_50V7K

1

2

PQ46SI4362_SO8

134

8765

2

SSG

DDDD

S

PH5

820_0603_5%

12

PR174499K_0603_1%

12

PC128

4.7U_1210_25V6K

12

PC146

0.1U_0603_25V7K

12

PC136

4.7U_1210_25V6K

12

PR169

499K_0603_1%

12

PU17

ISL6207CB-T_SO8

2

3

6

7

54

8

1

BOOT

PWM

VCC

EN

LGATEGND

PHASE

UGATE

PL16

0.56UH_ETQP4LR56WFC_21A_20%

1 2

PC133

0.01U_0603_50V7K

12

PQ44IRF7811W_S08

134

8765

2

SSG

DDDD

S

PR1683_0603_5%

12

PQ42SI4362_SO8

134

8765

2

SSG

DDDD

S

PQ45IRF7811W_S08

134

8765

2

SSG

DDDD

S

PL17

0.56UH_ETQP4LR56WFC_21A_20%

1 2

PQ47SI4362_SO8

134

8765

2

SSG

DDDD

SPH6

820_0603_5%

12

PC147

470P_0402_50V7K

1

2

PQ41IRF7811W_S08

134

8765

2

SSG

DDDD

S

PR171

32.4K_0603_1%

12

PC1381U_0805_25V4Z

12

PR176

32.4K_0603_1%

12

PC148

0.1U_0603_25V7K

12

PC135

4.7U_1210_25V6K

12

PC137

4.7U_1210_25V6K

12

PC130

4.7U_1210_25V6K

12

PR1701_0603_5%

12

PR1733_0603_5%

12

PC140

0.01U_0603_50V7K

12

PC134

0.22U_0805_16V7K

1 2

PR1751_0603_5%

12

PC127

0.22U_0805_16V7K

1 2

PQ40IRF7811W_S08

134

8765

2

SSG

DDDD

S

PQ43SI4362_SO8

134

8765

2

SSG

DDDD

S

PC131

1U_0805_25V4Z 1

2

PC129

4.7U_1210_25V6K

12

PU16

ISL6207CB-T_SO8

2

3

6

7

54

8

1

BOOT

PWM

VCC

EN

LGATEGND

PHASE

UGATEPWM3 52

PWM4 52

ISEN3-52ISEN3+52

ISEN4-52ISEN4+52

Page 55: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PROPRIETARY NOTE

04/01/03 Written by Po

P52:Add Oz168 for reservation

P36:Swap CP4 Pin 4 <-> 1; Pin 2 <-> 3

************* Rev0.1 PIR List **************

P36:Swap RP142 Pin 10 <-> 6; Pin 7 <-> 804/09/13 Written by Jei

POWER PIR LISTEVT2

DAL00 PIR LISTpage Reason for change Modify list

49,50,51 Modify power sequence for H/W request Delete PR89,PR90,PR120 and add PR179,PR180,PR181,PR183

Design change VTT_GMCH OCP point Change PR95 from 75K to 220K49

Design change charger voltage Change PR63 from 47.5K to 95.3K and add PR184

Increase throttling speed

Change VGA_CORE voltage for H/W request

Change PC91 from 1000P to 10P

Change PR106 from 13.3K to 6.49K;PR103 from 5.62K to 3.92K

Add 470P at location PC141,PC143,PC145,PC147

47

51

50

Update BOM

Add 0.1U at location PC142,PC144,PC146,PC148

53,54

53,54 Change PQ34,PQ35,PQ38,PQ39,PQ42,PQ43,PQ46,PQ47 from IRF7832 to SI4362

Change PC100 from 0.033U to 0.056U; delete PR138

Delete PC37; change PR43 from SD021100D00 to SD036100D00

Change PC60,PC61 from SE026473K06 to SE023473NT1

52

47

48

53,54

Solve CPU_CORE noise for EMI request

To prevent shortage Change PC142,PC144,PC146,PC148 from SE072104K00 to SE042104K01

PVT

53

Update BOM47,52

add PR149,PR151(0ohm),delete PC105,change PC100 from 0.056U to 0.047U

Change high side MOSFET and add gate/boot

resistor for EMI request

53,54 Change PQ32,PQ33,PQ36,PQ37,PQ40,PQ41,PQ44,PQ45 from IRF7821

to IRF7811W, change PR157,PR163,PR168,PR173 from 0ohm to 3ohm,

change PR160,PR165,PR170,PR175 from 0ohm to 1ohm

Solve power sequency problem for H/W request

Change VGA_CORE voltage for H/W request

Change CPU/Battery's OTP point for Thermal

team request

Solve LAN transmission has high frequency

noise issue

Delete PR180 and add PR177(0ohm)

Change PR39 from 16.9K to 14.7K, PR32 from 2.8K to 3.32K

Change PR106 from 6.49K to 0ohm (for X6326251001_NV33M/34M)

PR41 from 3.24K to 3.48K

Add PC149

Change PD17 from SC1B051L000 to SC11QS04000, delete PR150,PR152 and

49

50

46

PVT(memo) 50 Change VGA_CORE voltage for H/W request Change PR103 from 3.4K to 4.53K, PR106 from 4.53K to 9.09K (for X6326251002_NV31M)

52 Change CPU_CORE OCP point for QAD request Change PR131 from 27.4K to 21.5K

PVT(memo) 50 Modify CPU_CORE load line Change PR139 from 1.87K to 2.26K

52 Solved CPU_CORE shutdown issue Add PC103

LA-1911 0.2

DAL00 PIR LIST

Compal Electronics, Inc.

B

55 57Friday, August 08, 2003

Title

Size Document Number Rev

Date: Sheet of

Page 56: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Rev 0.2Location From To Location From To

Modify L5,L6Page Page5 10U 4.7U

6 DEL C20,C21 22U X

6 DEL 470U X470U

11 0.82U 4.7U

26 MODIFY C49,C488 0.1U0.01U

26 DEL C50 0.01U X

26 ADD C787 1000PX

26 ADD C788

27 ADD D21

4.7U

RB751V

X

X

28ADD C83

ADD C797,C7980.1UX

0.1U

31 DEL L42,L43 CHB2012U170 XADD L10,L11 X

ADD U57 XADD R617,R618

XR619,R620 1M

31 MODIFY C781 0.01U 0.1U

32 1.3K 1.5K

38 CHANGE U50 SN74HCT273PW

CHANGE C729 R542

38 ADD L54 FCM2012C-800

ADD C789 X 1U

38 SST39VF080-70ADD U56

29F040 X

39 MODIFY Q6 2N7002DTA114YKA

40 ADD R625 X 10K

40 MODIFY R464 20K 33K

0.33U 1U

100K 68K

ADD L55,L56 X CHB1608U301

43ADD Q23,Q38

X 2N7002

43 R457,R452ADD R450,R516

R272X 470 Ohm

43 ADD R612,R613 10K

BLM11A601S

ADD C794,C795 1U

Modify L15

C528

27C799 X

L44

31 L12 CHB2012U170

31

31

74HCT4066

R621,R622R623,R624

MODIFY R238,R241

SN74HCT374PW

38

38 CHANGE R542 C729

3838

ADD C793 X 100PADD C790,C791

C792 X 220P

X

38X

38 DEL U13

MODIFY C629

MODIFY R465

404040

Q39,Q40Q46

X

43 ADD L55,L56L57 X

44 X

LA-1911 0.2

PIR

Compal Electronics, Inc.

56 57Friday, August 08, 2003

Custom

Title

Size Document Number Rev

Date: Sheet of

Page 57: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Rev 1.0Location From To Location From ToADD U61

Page Page31 SI9182DH

X

X

X

X

31 ADD C809,C811 4.7U

31 ADD C810,C812 0.1U

3131

ADD R637

ADD R638

69.8K

X 24K

LA-1911 1.0

PIR

Compal Electronics, Inc.

57 57Friday, August 08, 2003

Custom

Title

Size Document Number Rev

Date: Sheet of

Page 58: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Rev 0.3Location From To Location From ToADD R627

Page Page22 0 Ohm

X

X

22 ADD U58 TC7SH08FU

22 ADD C806 X 0.1U

22 X 10KADD R628

31 ADD C807 X 1U

44 DEL C795 1U X

44 MODIFY R606 68K 0 Ohm

40 Modify R445 180K 820K

3131

DEL Q15 SI2302DS X

ADD U59 SI4800DYX

32 ADD R629,R630 X 0 Ohm

4040

ADD R631

ADD R632

X

X 0 Ohm

0 Ohm

32 ADD R633 X 10K

31 ADD R634,R635 X 0 Ohm

40 ADD R625 X 10K

LA-1911 0.3

PIR

Compal Electronics, Inc.

57 57Friday, August 08, 2003

Custom

Title

Size Document Number Rev

Date: Sheet of

Page 59: usermanual.wiki · A A B B C C D D E E 4 4 3 3 2 2 1 1 PAGE 37 Embedded Controller PAGE 47 SO-DIMM x 2(DDR) FSB PAGE 7,8,9,10,11 PAGE 4,5,6 PAGE 16,17,18,19 PAGE 23,24,25 FCBGA-932

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