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B O L E T Í N DE LA S O C I E D A D ESPAÑOLA DE
Cerámica y Vidrio A R T I C U L O
• • •
Ferroelectric thin films for memory applications
P.K. LARSEN, M. DE KEIjSER, G.A.C.M. SPIERINGS
Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands.
M . KLEE Philips GmbH Forschungslaboratorien, Weishausstr. 2, 53066 Aachen, Germany.
In this paper an overview will be given of the field of non-volatile ferroelectric memories with the emphasis on material aspects. The deposition of thin films of Pb(ZrTi)03, electrodes and electrical characterization methods are treated in detail.
Key words: Ferroeledrics, Thin films, Memory applications.
Películas delgadas ferroelectricas para memorias.
En el presente trabajo se ofrece una ampha visión de las memorias ferroelectricas no volátiles, resaltando los aspectos del material. Se describen con especial detalle los métodos de deposición de láminas de PZT, los electrodos y los métodos de caracterización eléctrica.
Palabras clave: Ferroeléctricos, lámina delgada, memorias.
1. INTRODUCTION
Ferroelectric materials exhibit a spontaneous electrical polarization (P) which is caused by the fact that these materials crystallize in a non-centrosymmetric cyrstal structure having a polar axis (1). If the ferroelectric material is placed between electrodes in a capacitor geometry, one can switch between two polarizations which correspond to the two opposite directed dipole states in a unit cell by applying a proper electric field. Because the polarization state remains after the electric field has been removed, this principle can be applied for non-volatile data storage (2).
The electrical properties of ferroelectrics which are most relevant for memory applications can be visualized by means of the hysteresis loop of the polarization versus the electric field. This is shown in Fig. la for a ferroelectric capacitor. P" ^ and P' are the positive and negative remanent polarizations (at zero field), respectively, and E^ and E ' are the coercive fields. Voltage pulses applied over the capacitor are used to write and read the stored information. Figure la shows that by the onset of a positive pulse two type of polarization changes can occur depending on the polarization state before the pulse is applied. If the initial state is V_^ then the applied pulse reverses the polarization giving rise to a switching polarization change (AP^). If the initial state is P^ there is no switching. The change in polarization (AP g is reflecting the dielectric nature of the material.
In Fig. lb the transient current response of the capacitor to an applied voltage pulse is shown for a switching and a non-switching case. The switched and non-switched charges, AQg= APg Apg and AQ^g= AP ^ Apg, respectively, can be determined by integrating the currents. PTere Agp is the area of the capacitor. The difference between AQ and AQ is used to discriminate betwe
en the two polarization states and thus to read the ferroelectric memory.
In the late 1980s the interest in the application of ferroelectric materials in memories as a part of a silicon-based memory cell raised (2). Each capacitor is combined with a transistor which serves the purposes of either selecting the capacitor or, in the case of non-selected, to shield the capacitor from unwanted signals. In Fig. 2 the layout of the one transistor/one capacitor (IT/IC) memory cell is shown. By applying films of submicron thickness the switching voltage can be kept at a level below the standard IC supply voltages.
The marriage of ferroelectric thin film technology with silicon-based technologies offers the potential of combining non-volatility with fast read/write characteristics and a small cell size, essential for making high density memories. The ferroelectric memory is superior in some ways to other existing non-volatile memories; in
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Fig. 1: Measurements for a P^Zr^^^Tig^yO^ capacitor prepared by sol-gel and using Pt electrodes, a) Hysteresis loop. The polarization changes (AP^ AP^^J caused by a positive voltage pulse is indicated, b) The trasient currents caused by a positive voltage pulse for the cases of switching (s) and non-switching (ns).
-Ml Bol. Soc. Esp. Cerám. Vidrio, 34 [5-6] 322-330 (1995)
FERROELECTRIC THIN FILMS FOR MEMORY APPLICATIONS
Bitline TABLE I: REQUIREMENTS FOR FERROELECTRIC RAM MEMORIES
Wordline
Plate
Fig. 2: Schematic diagram of an one transistor/one capacitor (IT/IC) ferroelectric memory cell.
particular it has a faster writing, a better write endurance and can be operated at low voltages. For some applications (military, satellite) the radiation hardness of ferroelectric materials is a very attractive feature (2). Presently the research concentrates on FerroElectric Random Access Memories (FERAMs) using transistor/capacitor structures and MOS processes. Reference (3) contains a number of papers devoted processing, characterization and applications of ferroelectric thin films. In this paper the emphasis will be put on materials aspects for FERAMs.
Memories combining ferroelectric capacitors with MOS (metal-oxide-silicon) transistors can be fabricated with different memory cell lay outs (4). The highest density is obtained with the lay-out shown in Fig. 2. This IT/IC cell puts rather stringent requirements on the ferroelectric layers, especially with respect to the endurance. This is caused by the destructive reading, i.e., depending on the initial state the read operation might reverse the polarization and therefore has to be followed by a re-write operation. For rehable reading, the ferroelectric properties, i.e. AP have to remain within specified limits. The number of accesses to the cells, i.e. number of switching operations, for which this is possible determines the endurance. In Table 1 the requirements are summarized. Applications for specific products are still possible with memories that do no fulfil all requirements. For instance, present commercial memories are specified with an endurance of 10 ^ cycles with a 10-year data retention.
2. THE FERROELECTRIC CAPACITOR
Most work in the ferroelectric memory field up to now has been directed towards materials in the lead zirconate titanate PbZr^Ti^_^03 (PZT) system in combination with Pt-based electrodes (2,4). Bulk ceramics with compositions having the tetragonal structure (x <0.53) have high remanent polarizations (P . ~ 50|LLC/cm2), low coercive fields (E^ ~ 10 kV/cm) and high Curie temperatures (T^= 490 °C for x= O and 350 °C for x= 0.53) (5). These tetragonal compositions are in principle all suitable for non-volatile memory applications. For thin PZT films one finds generally lower values of polarization (15-40 |iC/cm^ ) and higher coercive fields (50-100 kV/cm). The dependence of the properties on the composition is in general rather small. Because it is relatively easy to prepare thin films which have good or acceptable properties
Switching charge ÛQ, - AQ,, ^ 1-2 10" ^ C (For ApE * 1 m^ this means P, ^ 5-10 fjCicvn^) \
1 Switching voltage 3.5V(V,c = 5V) ;2V(V ,c = 3.3V) 1
1 Switching speed < 10 ns 1
1 Endurance (fatigue) virtually unlimited (lO^'* -10^^ cycles) |
1 Retention (aging) > 10 years |
Temperature stability commercial applications 0 - 70 °C; military and automotive applications -40 - 125 °C, |
Silicon IC compatibility No loss of transistor properties
with compositions near the morphotropic phase boundary (x=:0.53) many studies concentrate on this composition. For memory applications it is necessary that the polarization can be switched with a few volts (see Table I) and this determines the film thickness. In general, thicknesses in the range 0.1-0.3 jim are applied.
Besides the PZT system other ferroelectric ompounds such as layered pervoskites are considered for memory applications. These are treated in section 2.2.2.
In the following subsections we discuss the preparation and properties of ferroelectric capacitors in detail. For memory applications the capacitors have to be processed on siHcon wafers and to be compatible with the requirements for production of integrated circuits. This means that the deposition methods should be able to produce homogeneous and uniform films on wafers of 10-15 cm diameter, and in the future on even larger wafers. There are three main deposition techniques available, i.e. sputtering, spin-coating and chemical vapour deposition which subsequently will be discussed. The deposition has to take place on polycrystalline electrodes. These are an integral part of the capacitor having a strong influence on the capacitor properties. Here platinum as well as oxidic electrodes are described.
2.1. Sputter deposition of ferroelectric thin films
The first sputter deposition of an ferroelectric oxide, BÍ4TÍ30^2/ was made by Takei et al. (6) using rf-diode sputtering. Since the early 1970's all the different sputter methods (rf-sputtering, dc- an rf-magnetron sputtering, ion-beam suputtering) have been appHed for the deposition of ferroelectric thin films. Recent overviews of the sputter deposition of ferroelectric films have been given by Roy et al. (7), by Francombre (8) and by Bruchhaus et al. (9). It was shown by Lijima et al. (10) that it was possible to deposit highly-oriented or epitaxial PbTi03 on a MgO substrate at 600 °C using rf-sputtering with a single target composed of pressed PbTi03 and PbO powder. At higher substrate temperatures a second phase was formed, presumable due to depletion of Pb. This demonstrates that the high volatility of PbO is one of the inherent difficulties in the sputtering of PbTi03 and PZT and that an excess of PbO is needed during deposition. In order to overcome this problem, multi-element metal targets (11) or multi metal target magnetron sputtering (9) have been tried. The latter method allows the Zr/Ti stoichiometry to be varied. Plasma damage can be a problem as well. This can be reduced by the recently developed technique of facing target rf sputtering (12). The ion-beam sputtering technique offers advantages such as low background pressure and low plasma damage, independent control of the sputtered species and the possibihty to use reactive oxygen ions. It is able to provide uniform thickness and composition over 10 cm diameter wafers (13).
Boletín de la Sociedad Española de Cerámica y Vidrio. Vol. 34 Num. 5-6 Septiembre-Diciembre 1995 323
p. K. LARSEN, M. DE KEIJER, G.A.C.M. SPIERINGS, M. KLEE
High quality PZT films can be prepared on polycrystalline Pt-coated silicon wafers with all these techniques at substrate temperatures in a temperature window within the range 450-700 °C. This requires a careful optimization of the growth conditions under difficult conditions, eg. a high oxygen partial pressure in essentially a vacuum deposition technique.
An alternative to the deposition at high substrate temperatures is to deposit an amorphous PZT film at room temperature and subsequently crystallize it by an anneal treatment. The anneal procedure then strongly influences the film properties. Considering the high costs of sputtering, eg. the equipment, and that PZT films can be produced via the amorphous route by spin-coating techniques this alternative is not very attractive.
2.2. Spin-coating deposition
Spin-coating techniques to produce thin films of PZT and layered ferroelectric compounds have in the last five years found widespread use due to an easy and cheap procedure which is able to produce high quality films.
2.2.1. LEAD ZIRCONATE TITANATE FILMS
In the spin-coating process a solution of metallo-organic compounds is deposited on the substrate and spun (at room temperature) into a thin film. This is followed by a drying process on a hotplate at temperatures in the range between 200 and 400 °C at which an amorphous film is formed. This is crystallized into the perovskite phase by heating in an oxygen atmosphere at temperatures between 500 and 700 °C.
One spin-on technique makes use of sol-gel solutions. The first data on PZT sol-gel processes were reported in the 1980^s (14).The solutions were made by reaction of dehydrated lead acetate with titanium-zirconium methoxyethoxides followed by a hydrolysis with aqueous nitride acid solutions. Since These early studies of the sol-gel deposition of PZT a large number of modifications of this technique have been studied. A recent overview can be found in Ref. 15. In addition to the various sol-gel solutions the drying and firing procedures give rise to a large number of possible variables. The optimization of the film properties can therefore be demanding.
An alternative spin-coating method is the metallo-organic decomposition (MOD) technique. Metallo-organic compounds, eg. metal alkoxides such as titanium-n-butoxide and zirconium-n-butoxide, together with Pb-compounds, eg. Pb-2-ethylhexanoate, are dissolved in organic solvents. By firing the spin-coated film the compounds are decomposed and the perovskite phase is formed (16,17).
The film thickness per coating depends on the molarity and viscosity of the solution, spin rate etc. A typical thickness in one spin-coating run is 50-100 nm so that a total film thickness of 0.1-0.3 jum is obtained by 2-4 coatings. It should be noted that the rather lengthy process times (>30 mins) needed for furnace annealings can be largely reduced by rapid thermal annealing (18). This reduces the total time-temperature budget considerably. If the substrate is not flat but contains topography, e.g. from earlier (MOS) processing steps, spin-coating deposition leads to variations in the film thickness, i.e. the deposition is non-conformal. This forms a major drawback for the use of spin-coating techniques for memory applications, since planarization of the substrate previous to coating is then required. In order to overcome this problem misted deposition techniques Hke aero-sol are applied.
The microstructure of the film influences the switching process
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and it is of utmost importance to control it. One of the important factors for doing so is to choose an appropriate firing procedure. This has been studied for PbZr Ji^_^03 and PbTiOg films by Klee et al. (17) using a modified sol-gel process and MOD. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) investigations in plan-view (normal to the sample surface) and cross-section (XTEM) were carried out to characterize the grain size, the film morphology and the defect structures. The TEM studies have shown that two types of thin films can be grown dependent on the processing (19,20). High temperature pre-treatments at 550-600 °C after each spin-on process give rise to a columnar growth of thin PbTiOg and PbZr^Ti^_^03 films with column width of 70-250 nm. Each layer is found to crystallize epitaxially on the preceding layer (19). In these columnar films typically a lamellar domain configuration predominates. This is shown in the plan-view TEM image in Fig. 3b. These films have a high remanent polarization and can ben switched very fast (see Fig.l).
The standard firing process for PZT thin films reported by many groups consists of only a low temperature pre-treatment at 200-350 °C between successive spin-on processes. The stack of amorphous layer formed in this way is crystallized into the perovskite phase during the final annealing. This gives rise to films with a coarse-grained morphology. The grains within these films show grain sizes of 200-900 nm. Within the larger PZT grains a banded domain configuration similar to the domain configurations reported for bulk ceramics is found. This is shown in Fig. 3a.
2.2.2. LAYERED PEROVSKITES
Although thin PZT films have been the preferred ferroelectric
324 Boletín de la Sociedad Española de Cerámica y Vidrio. Vol. 34 Num. 5-6 Septiembre-Diciembre 1995
FERROELECTRIC THIN FILMS FOR MEMORY APPLICATIONS
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Fig. 4: X-ray diffraction pattern of a SrBÍ2Ta20gfilm deposited by an MOD process on a Pt coated silicon substrate.
compound for FERAM applications the limited switching endurance observed with Pt electrodes has stimulated the interest in other ferroelectric systems. During several years the so-called «Yl» family of compounds has been claimed to be fatigue-free (21). Recently, it was released that SrBÍ2Ta209 and related compounds, known since 1961(5), belongs to the «Yl» family (29). Thin films can be deposited with spin-coating techniques and a more complex misted aerosol deposition technique. No details about the used solutions have been given by these authors. Remanent polarizations are in the range ó-lOjuC/cm^.
Another layered compound, BÍ4TÍ30^2/ ^^^ ^^^^ extensively prepared by sputtering (8). It has its polarization lying in the monoclinic a-c plane having polarizations of about 50 and 4|iC/cm^ along the a and c-axes, respectively.
We have investigated the spin-on processes for the layered perovskites BÍ4TÍ30- 2 (22) as well as SrBÍ2Ta209 and SrBÍ2TaNb09 (15,23) by means of MOD processes on Si substrates with a Ti/Pt bottom electrode. Bismuth and alkaline earth salts of long chain carboxylic acids such as Sr-and Bi-ethylhexanoates were dissolved in alcohols together with titanium, niobium and tantalum alkoxi-des. Polycrystalline layered perovskite films were formed after spin-coating and firing at 650-800 °C. A random growth of the crystals on top of the Ti/Pt electrode with an orthorhombic primitive cell was found for the Bi TÍ30- 2 films. The Sr BÍ2Ta209 layers crystallize also orthorhombically (see Fig. 4).
2.3. Organometallic chemical vapour deposition
Chemical vapour deposition (CVD) is widely used in IC-pro-cessing and is capable of growing films of high purity uniformly over large areas with high growth rates. Further advantages of the method is that a good step coverage can be obtained and, particularly important for the deposition of multicomponent oxidic films, that CVD is compatible with high oxygen partial pressures during the growth.
In CVD processes precursors are evaporated and transported (by a carrier gas) into *the reaction chamber containing a heated substrate. Here the precursors are decomposed either thermally or by other means (plasma, UV-Hght) and react to form the desired
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compound on the substrate. This process is in general very complex and strongly temperature dependent (24). It is desired that the precursors can be easily evaporated and transported. This means that they should have relatively high vapour pressures at temperatures in the range 0-150 °C so that excessive heating of the evaporators (bubblers) and transport lines can be avoided. Generally, organometallic compounds fulfil this requirement and CVD using such compounds is termed OMCVD (or sometimes MOCVD). The first studies of this method were made in the early 1980's. A recent overview has been given by M. de Keijser et al. (25). In the following the technique will be shortly discussed based on results from our laboratories.
In this method precursors such as titanium-tetra-isopropoxide (Ti( OC3h7)4, zirconium-tetra-butoxide Zr{^OC¿^^)^ and tetra-ethyl-lead Pb(C2H3)4 are introduced as gases in a heated reactor together with oxygen. The liquid precursors are evaporated in a bubbler system and transported to the reactor through heated tubes. Figure 5 shows an example of the OMCVD set-up equipped with a single-wafer horizontal reactor cell operated at reduced pressure (<20 mbar). It contains a rotating susceptor which supports wafers with diameters up to 150 mm and it appHes heating by IR lamps. Typical PZT growth temperatures range from 550 to 700 °C with growth rates in the order of 1 |im/hour. The uniformity of the composition of PZT over 10 and 15 cm diameter Pt coated substrates can be kept within 5% with respect to stoichiometry (e.g. typical the ratio of Pb to (Zr+Ti) is 1 ± 0.05). Similarly, the variation in thickness is below 5%. Furthermore, PZT can be formed conformai to the surface topography of a processed wafer resulting in a good step coverage. The OMCVD technology can also be used for depositing materials such as RUO2 (26) and other conductive oxides. The limitation of thermal OMCVD is the scarcity of metalorganic precursors with sufficiently high vapour pressures to be evaporated and transported to the reaction chamber. In order to overcome such problems CVD systems applying a liquid delivery technique which allows a controlled introduction of (low vapour pressure) precursors are being developed (27).
2.4. Electrodes
2.4.1. PLATINUM ELECTRODES
Platinum electrodes are widely applied in integrated ferroelectric capacitors. They are normally deposited by sputtering. On oxidized sihcon wafers a thin Ti (or Ta) films is used as an adhesion promoter. The thicknesses of the Pt and Ti films are typically 70-200 nm and 5-10 nm, respectively. When the Pt bottom electrodes are annealed in an oxygen ambient or heated after deposition of a PZT film, hillocks can be formed at the surface. In addition, the Ti adhesion film can be oxidized to TiO^ (28). Both
Boletín de la Sociedad Española de Cerámica y Vidrio. Vol. 34 Num. 5-6 Septiembre-Diciembre 1995 325
p. K. LARSEN, M. DE KEIJER, C.A.C.M. SPIERJNCS, M. KLEE
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Fig. 6: SEM cross-sectional view of a Pt/PZT/Pt capacitor after dry etching. (From Ref. 34).
Fig. 7: Hysteresis curves of 5000 jirrp- Pt/PZT(300 nm)/Pt ferroelectric capacitors prepared by OMCVD. The left and right hand panels show hysteresis curves after structuring and after an additional anneal, respectively. The hysteresis curves were measured at 1 kHz with amplitudes of3V,5V and 8 V, respectively.
processes have to be Hmited to avoid both short-circuiting and the possible formation of non-ferroelectric interface films. This can be done by reducing the thicknesses of the Pt and Ti layers as much as possible while maintaining a good adhesion and pinhole free layers (28,29). When imperfections such as pinholes are present in the Pt film, the PZT can react with the underlying SÍO2 or silicon and lead siUcates will be formed. The morphology of the bottom electrode has been found to strongly influence the microstructure of the PZT films. In sol-gel technology nuclei are necessary to obtain well-crystallized films, and the hillocks can serve as such.
Compared to the bottom electrode, the top electrode is less affected by subsequent processing. This gives more freedom in the choice of top electrode material. However, for FERAM applications a symmetry in the two switching directions is desirable, so for this reason the use of the same material for both top and bottom electrodes is strongly preferred. Furthermore, it has been found that a rapid thermal anneal after deposition of the top electrode to a temperature higher than T improves the ferroelectric properties. This can be ascribed to stress related effects (30).
2.4.2. OXIDIC ELECTRODES
The (di)oxides of (noble) transition metals such as Ru, Rh, Ir and Os combine a low resistivity with a high thermal stability. Their bulk resistance ranges from 20-100 ¡Liil.cm. Besides the oxides, the metals themselves can also be used as electrodes for ferroelectric materials, either in the elemental state or as alloys. As a consequence a number of different combinations of the noble transition metals and their oxides have been investigated in ferroelectric capacitor structures. A recent overview has been given by O. Auciello et al. (31). The interest in these types of electrodes compared to Pt is due to the improved endurance properties (see sect. 3.2.3.). Sputter deposited RUO2 is widely applied. Deposition processes for RUO2 using OMCVD (26) as well as sol-gel (15) have also been developed. It is also possible to use hybrid (Pt, RUO2) electrodes (32).
2.5. Etching of the ferroelectric stack
In order to prepare capacitors on a micron or submicron scale it is necessary to use dry, anisotropic etching techniques. Wet chemical etching leads to underetching and is therefore not applicable for very small lateral dimensions. For the chemically inert Pt only sputter-etching or ion-beam milling are available. This makes Pt a less attractive material in IC processing. Plasma etching and reactive ion etching (RIE) techniques for PZT and Ru/Ru02 have been demonstrated, making use of fluorine-and chlorine-containing plasmas (33,34). As an example Fig. 6 shows a Pt/PZT/Pt capacitor prepared by dry etching. Presently, these etching techniques are reaching a technology level compatible to that of today IC technologies.
3. ELECTRICAL CHARACTERIZATION OF FERROELECTRIC CAPACITORS
The design and fabrication of ferroelectric memories should be based on proper electrical data using test capacitors prepared by the same processing as the memory capacitors. In this section the characterization method and the relevant properties of the Pt/PZT/Pt capacitors are described. These have to be compared with the requirements from a device point of view which we will discuss briefly.
In the following sections results obtained for capacitors prepared in our laboratory are presented.
3.1. Hysteresis loop
Hysteresis loop measurements are used for the evaluation of the general properties of ferroelectric capacitors and the relation of these properties with the preparation of the capacitor (deposition method, type of electrodes, etc.). Information about the remanent and saturation polarizations and the coercive and saturation fields (or voltages) are acquired by such measurements. As an example. Fig. 7 shows the hysteresis curves for capacitors with a 300 nm thick PZT layer prepared by OMCVD before and after an anneal treatment. This treatment is seen to influence the switching properties (eg. E^,Pp.
It should be noted that the values of E here are substantially higher than the bulk value of 10-20 kV/cm. The generally observed increase in E with decreasing film thickness reflects electrode and interface effects. Here, the improvements in the properties caused by the anneal can be ascribed to a decrease in the thickness of an apparent non-ferroelectric interface layer between the PZT and the electrodes (35). As mentioned above changes in the stress conditions in the capacitor during processing have been found as well (30).
The polarization values of these capacitors are rather large P ^ 30-40 )iC/cm^ ), and comparable to bulk values. By comparison the polarization values obtained for films prepared by sol-gel (see Fig. la) are in general somewhat smaller (P . ^ 15-25 |LiC/cm ) and the loops are less squared. Such differences can be related to the microstructure of the material, the presence of second phases, defects (lead deficiencies, oxygen vacancies) and the just mentioned presence of ferroelectrically inactive layers at the Pt-PZT interface.
Hysteresis measurements are carried out at relatively low frequencies (typically in the range 100 Hz to 10 kHz) while memory apphcations use cycling frequencies of 10-100 MHz. In this respect hysteresis measurements are inadequate in providing relevant data for memory applications.
326 Boletín de la Sociedad Española de Cerámica y Vidrio. Vol. 34 Num. 5-6 Septiembre-Diciembre 1995
FERROELECTRIC THIN FILMS FOR MEMORY APPLICATIONS
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Fig. 8: Schematic diagram of the circuit for pulse measurements. The inset shows the probe circuit.
3.2. Pulse measurements
The evaluation of the suitabihty of ferroelectric capacitors for memory applications requires measurements in an appropriate time domain, e.g., 5-200 ns. This can be done with pulse measuring techniques (36).
3.2.1. MEASURING TECHNIQUE
Figure 8 shows the schematic lay-out of the electrical circuit for switching measurements in the time domain down to the nanosecond range (46,47). The three main elements are the pulse generator, the probing circuit and the signal analyzer which are connected with coaxial transmission Unes. With this circuit the measurements shown in Fig. lb were carried out. The pulse generator makes pulse trains consisting of, e.g., a negative (voltage) write use followed by two consecutive positive read pulses. The first read pulse switches the ferroelectric capacitor. The switching current is measuredly the voltage across the small load resistor (R). By integration the switched charge and thus AP is determined. The response to the second positive pulse is given by the non-switching polarization AP^ . For proper measurements a number of points has to be considered. Impedance matching is important to minimize reflections. Oscillatory responses can occur due to the self-inductance (L) of the probe circuit (in series with the ferroelectric capacitor). It is also important to understand the circuit time constants in order not to misinterpret observed switching times, i.e. is the measured switching time caused by a physical switching mechanism or is it related to the circuit parameters. In the example of Fig. lb the response is completely determined by the circuit. A detailed discussion of these experimental aspects can be found in Ref. 36.
3.2.2. INFLUENCE OF PULSE AMPLITUDE AND WIDTH
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An example of the switched and non-switched polarization as a function of the switching amplitude is shown in Fig. 9 for PZT capacitors having a thickness of 210 nm. The difference AP -AP^g(=2Pp at 2 V is already about lOjLiC/cm . Saturation of the remanent polarization occurs at about 4 V with a value of 25|iC/cm^. The data meets the requirements for high-density integration at low operational voltages.
In order for a capacitor to function in a high density memory the rate at which the polarization reverses has to be very high. The level of the voltage response corresponding with 10' ^ C has to be reached within a short time (<5-20 ns). This can be studied by transient current switching time is instrumentally limited in this case.
This limitation is related to the time necessary for the power supply to deliver the charge AQ^ (^AP^Apg). By reducing Ap^ (AP is constant) one finds a decrease of the switching time; even down in the subnanosecond range switching times are in most cases determined by the experimental set-up (36).
If the switching process is characterized by a wide distribution of switching times, the method just described will determine only the components within the integration time of the switching current. Furthermore the pulse width may be too short to completely switch the capacitor. This means that the polarization values determined by pulse switching can be markedly lower than those
Boletín de la Sociedad Española de Cerámica y Vidrio. Vol. 34 Num. 5-6 Septiembre-Diciembre 1995 327
p. K. LARSEN, M. DE KEIJER, G.A.C.M. SPIERINGS, M. KLEE
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Number of cycles
Fig. 11: Fatigue behaviour of PZT capacitors prepared by OMCVD with (a) Pt capacitors and (b) RuOj/Ru electrodes.
obtained by hysteresis measurements. Such effects can be investigated by varying the pulse width and measuring AP and AP^ . Figure 10 shows this dependency for sol-gel films prepared with low and high temperature pre-treatments. Clearly, the film with the high temperature pre-treatment is best suited for memory applications. The cause of these differences can be related to the microstructure and corresponding domain formation (37). By optimizing the microstructure and electrode/ferroelectric interface the width dependence can be kept small. The results discussed above show that a memory operation using pulse widths below 10 ns will certainly be feasible.
3.2.3. ENDURANCE (EATIGUE)
The switched polarization of ferroelectric capacitors decreases with the number of polarization reversals. This effect is called fatigue. The maximum number (N) at which the polarization values remain within specified limits defines the endurance. Ideally this should be virtually unlimited (see Table I).
Figure 11a shows for a Pt/PZT/Pt capacitor how the switched and non switched polarization degrade by repeated switching for different pulse amplitudes. Generally, there is an initial phase during which the AP^ remains almost constant. At a certain number of cycles AP starts to decay. The value of N at which this almost logarithmic decay strats depends on the material properties (ferroelectric film, electrodes) as well as the measuring conditions (pulse amplitude). The endurance lifetime is determined by the number of polarization reversals at which the difference between AP^ and AP^ gets below a threshold value, eg. 50% of the maximum value. The dependence of the lifetime
on the pulse amplitude has been investigated in ref. (35). A very large increase of lifetime of more than 6 orders of magnitude was found by decreasing the pulse amplitude. This can largely be ascribed to a reduction of the switched polarization (i.e. non-saturated switching). These effects are seen in Fig. l i b . It should be noted that the difference signal AP -AP g is large even with 1.5 V, allowing very small capacitor areas at low operational voltages.
For PZT with Pt electrodes a plausible explanation of the cause of fatigue is given in terms of defect entrapment (oxygen vacancies) at the PZT-Pt interfaces (38). The much better fatigue properties of PZT with Ru/Ru02 electrodes, as shown in Fig. l i b , can be explained by the variable oxygen stoichiometry of these electrodes. This means that oxygen vacancies are easily accommodated. Although the lifetime is thus much improved fatigue can still be observed. From studies of Scanning Auger Microprobe (SAM) and SEM investigations on fresh and fatigued capacitors there are indications that Ru form the electrodes diffuse into the PZT film (39). In Fig. 12 SEM images are shown of a fresh and a fatigued capacitor. It seems that the local forming of channel-Hke structures in the PZT is the cause of the fatigue.
3.2.4. RETENTION
Retention is the ability to keep the polarization with time and it is a fundamental feature of a nonvolatile memory. A minimum value for a memory is 10 years.
The charge of polarization with time, which is called aging, can be investigated by pulse measurements. The write pulse is, after a variable delay, followed by a single read pulse. Fig. 13 shows a result of APg for a Pt/PZT/Pt capacitor as a function of the time elapsed between writing and reading the capacitor. The result shows that the aging caused by deposing or backstitching effects over many decades is smaller than 5%. The figure indicates that a 10-year retention is not a problem.
4. INTEGRATION ASPECTS
The integration of ferroelectric capacitors with CMOS devices is an essential and very demanding task in producing ferroelectric memories. In this paper we shortly discuss some of the issues which have been treated in more depth in Ref. 40.
In Fig. 14 two examples are shown how a IT/IC memory cell can be made. In both cases a two level metallization with plug filling is used. In Fig. 14a the capacitors are deposited on the field oxide areas. A higher density might be realized by positioning the capacitors above the polysilicon gates or by positioning the capacitors on top of the drain, e.g. on top of the metal plug (Fig. 14b). The shorter distance between the capacitor and the transistor in the latter case increases the risk of diffusion of harmful ions to the transistor areas. The option in Fig. 14b requires the possibility to deposit PZT, or the bottom electrode, either on the conducting metal plug (e.g. W, TiN) or directly on the mono-crystalline silicon.
The fabrication process of ferroelectric memories can be separated into three subsequent processing phases, the order of with is determined by decreasing processing temperatures: first the transistor structure, then the capacitor processing and finally the interconnection and protection (back-end). Standard fabrication methods can be apphed for producing the CMOS devices. The capacitor fabrication has been discussed in the preceding sec-
328 Boletín de la Sociedad Española de Cerámica y Vidr io. Vo l . 34 Num. 5-6 Septiembre-Diciembre 1995
FERROELECTRIC THIN FILMS FOR MEMORY APPLICATIONS
Fig. 12: SEM images ofPZT with Ru/Ru02 electrodes after the top electrode and part of the PZT layer have been sputtered away of (a) a fresh capacitor and (b) a fatigued capacitor.
O
0 6 4 2 2 2 4 6 8 10
log (t/seconds) •
Fig. 13: Retention of the polarization of a PZT capacitor.
Fig. 14: Schematic ilustration of ferroelectric capacitors integrated with MOS transistors with two level metallization, (a) Top contact cell (capacitor on field oxide); (b) bottom contact cell (capacitor above drain).
Fig io: SbM imciugiaphbliowuig a Uajibiblonto llie left) iniegraded witliajetroelectric capacitor (to the right).
tions. In the back-end processing the first step is to cover the capacitor with a insulating film such as SÍO2 or SÍ3N4. Next, contact holes have to be etched in this insulating film to contact the capacitor electrodes and to contact the sihcon and polysilicon of the transistors. A conductor film (TiW/Al or TiN/Al) is deposited and patterned to interconnect the transistors and to connect the transistors with the capacitors. As is standard in the CMOS technology, multiple interconnect layers as shown in Fig. 14 may be appUed. Finally an insulator is deposited over the completed circuity for scratch protection. The maximum temperature during the back-end processing is about 450 °C. Before device fabrication the processing procedure has to be carefully investigated regarding its feasibility and the effects it might have on properties. This is normally done by processing test structures containing a large variety of test modules. In the case of ferroelectric memories such test structures will contain standard CMOS test modules (e.g. transistors, diodes and resistance chains), ferroelectric modules (capacitors, contact resistance modules) as well as integrated structures (memory cells). Figure 15 shows as an example a SEM micrograph of an integrated MOS transistor and ferroelectric capacitors.
5. OUTLOOK
In this paper the preparation and properties of ferroelectric capacitors for non-volatile memories have been treated. The electrical performance of various material systems can be regarded as very satisfying for a number of appHcations. The high ongoing level of activities at a number of industrial firms within this field strongly indicate that ferroelectric capacitors will be a key-part of many future non-volatile memories.
ACKNOWLEDGEMENTS
We thank H. Achard for the use of Fig. 6. The overview is partly based on work a Philips and we thank R. Cuppens, G. Dormans, R. Janssen, J. Geerse, D. Taylor, M. Ulenaers, A. De Veirman and P. van Veldhoven for their contributions. •
Boletín de la Sociedad Española de Cerámica y Vidrio. Vol. 34 Num. 5-6 Septiembre-Diciembre 1995 329
p. K. LARSEN, M. DE KEIJER, G.A.C.M. SPIERINGS, M. KLEE
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