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Gem5
l Abstractl Basics of gem5l Simulation modes
- SE & FS
l Benchmarks on gem5- A Mickey mouse benchmark- PAESEC benchmark- Obtained Statistics
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Abstract
l gem5 Simulator- The gem5 simulation is the merger of the best aspects of the M5 and GEMS simulators.
l M5 Simulator- M5 provides a configurable simulation framework , multiple ISAs, diverse CPU models.
l GEMS simulator- GEMS complements these features with a detailed and flexible memory system, including support for multiple cache coherence protocols and interconnect models.
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Abstract
l Gem5 has been a multi-‐year effort from both academy and industry.
l Main goals- Open source tool focused on architectural modeling- Flexibility
p Multiple CPU models, memory systems, and device modelsp Across the speed vs accuracy spectrum
- Availabilityp For both academic and corporate researchersp No dependence on proprietary codep BSD license
- Collaborationp Combined effort of many with different specialtiesp Active community leveraging collaborative technologies
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High-‐level Features
l Configurable CPU models- Simple one-‐IPC (SimpleAtomic/Timing)- Detailed in-‐order execution (InOrder)- Detailed out-‐of-‐order execution (O3)
l Pluggable memory system- Classic memory model- Ruby memory model
l Device Models- Enough device models to boot Linux
l Boot real operating systems- Linux, Android
l Many ISAs- ARM, ALPHA, MIPS, SPARC, POWER, X86
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Basic of gem5
l Compile targets- scons build/<isa>/<binary>- ISAs: ARM, ALPHA, MIPS, SPARC, POWER, X86
l Binaries- gem5.debug debug build, symbols, tracing, assert- gem5.opt optimized build, symbols, tracing, assert- gem5.fastoptimized build, no debugging, no symbols, no tracing, no assertions
- gem5.prof gem5.fast + profiling support
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Simulation modes
l Syscall emulation (SE)- For running individual applications, or set of applications on MP- Models user-‐visible ISA plus common system calls- System calls emulated, typically by calling host OS- Simplified address translation model, no scheduling
l Full system (FS)- For booting operating systems- Models bare hardware, including devices- Interrupts, exceptions, privileged instructions, fault handlers- Simulated UART output- Simulated frame buffer output
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Simulation mods -‐ System Call Emulation
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Simulation modes -‐ Full System (Linux on ARM)
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Benchmarks on gem5 -‐ PARSEC
l The Princeton Application Repository for Shared-‐Memory Computers (PARSEC) is a benchmark suite composed of multithreaded programs.
l The suite focuses on emerging workloads and was designed to contain a diverse selection of applications that is representative of next-‐generation shared-‐memory programs for chip-‐multiprocessors.
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Benchmarks on gem5 -‐ configuration
l CPU: x86, 4-‐core, in-‐orderl L1 I-‐Cache
- 32 KB, 2-‐way set-‐associative, latency 3 cyclesl L1 D-‐Cache
- 64 KB, 2-‐way set-‐associative, latency 3 cyclesl L2 Cache
- Unified, 2 MB 8-‐way set-‐associative, latency 15 cycles, MESI CMP directory cache coherence protocol
l Cacheline size: 64Bl Memory size: 2GBl OS: Linux 2.6.28.4.smp
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Benchmarks on gem5 -‐ cache statistics
L1 ICache Miss Rate (%)
0
0.2
0.4
0.6
0.8
1
1.2
blacks
holes
fluida
nimate
freqm
ine
swapt
ion x264
canne
alded
up
stream
cluste
r
averag
e
Core 0
Core 1
Core 2
Core 3
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Benchmarks on gem5 -‐ cache statistics
L1 DCache Miss Rate (%)
0
1
2
3
4
5
6
7
blacks
holes
fluida
nimate
freqm
ine
swapt
ion x264
canne
alded
up
stream
cluste
r
averag
e
Core 0
Core 1
Core 2
Core 3
系统结构实验室
Benchmarks on gem5 -‐ cache statistics
L2 Cache Miss Rate (%)
0
10
20
30
40
50
60
70
blacksholes
fluidanimate
freqmine
swaption x2
64
canneal
dedup
streamcluster
average
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