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A 1.5V, 1.5GHz CMOS Low Noise Amplifier
Derek K. Shaeffer and Thomas H. Lee
Stanford University
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Outline
• LNA Architecture / RF Noise
• Experimental Results
• Summary and Conclusions
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Simple CMOS Noise Model
vg2 Rg Cgd
Cgs rovgs
+
_gmvgs id2
ChannelThermal Noise
• Channel thermal noise is dominant.
• Gate resistance minimized by good layout.i kTB gd d
204= γ
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Channel Thermal Noise
• Current HSPICE Implementation:
• BSIM-3 Implementation:
(NLEV < 3)
( )i kTB K V Va a
aGDSNOId gs T
228
3
1
1= ⋅ −
+ ++
' (NLEV = 3)
i kTBgd m2 8
3=
aV
Vds
dsat
= −1
ikT
LQd
eff
effinv
22
4=
µ
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How To Get 50Ω
Zin
Dual Feedback Resistive Termination 1/gm Termination Inductive Degeneration
Zin
Rt
Zin
Ls
RL
Zin
Rf1
Rf2
Z R Rin f f= 1 2 Z Rin t= Zgin
m
=1 [ ]Re Z
g
CLin
m
gss=
Need high gain. Poor NF. NF > 3dB
( γ > 1 )
Narrowband.
Stability problems.
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LNA Input Stage
ZinLg
Ls
M1
M2Vbias
( )Z s L LsC
g
CL Lin s g
gs
m
gss T s= + + +
≈
1ω
( )G g Qg
C R L
RL
R
R
m eff m inm
gs s T s
T
sT s
s
T
s
, = =+
=+
=
11
12
ω ω
ω
ωω
ωω
Note: Gm,eff is independent of gm1!
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• Reducing gd0, Increasing Qin lowers F!
• Achieving low F involves linearity tradeoff.
• Technology Scaling is Key.
• Problem : The Free Lunch Principle
Noise Factor
FR
R
R
Rg Rl
s
g
sd s
T
= + + +
1 0
2
γωω
V Q Vgs in s=
FR
R
R
R
g R C
gl
s
g
s
d s gs
m
= + + +10
2 2
2
γ ω
A common form A better form
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Induced Gate Effects
S D
G
Vgs
Vds
Ig
• Gate Noise Current• Real Component of Zg
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Equivalent Gate Circuit
vg2
ig2 Cgsgg -OR- Cgs
rg
+
_
Vgs
+
_
Vgs
gC
gg
gs
d
=1
5
2 2
0
ωi kTB gg g
2 4= δ rgg
d
=1
5 0
v kTB rg g2 4= δ
“Blue” Noise “White” Noise• δ (∼ 4/3) modified by hot electron effects
• partially correlated with (c = 0.395j)
• and gg not modeled in HSPICE
+ _
ig2 id
2
ig2
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Revised Noise FactorLg
Ls
Rs
Rl Rg
gg Cgs vgs
+
_gmvgs
iout2
id2
vg2vl
2
ig2
[ ]FR
R
R
Rg R Q c Ql
s
g
sd s
TL L= + + +
+ + +
1 1 2
5 510
2 2 22γ
ωω
δαγ
δαγ
vs2
(At Resonance)
AdditionalNoise Source
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Noise Factor Terms
[ ]FR
R
R
Rg R Q c Ql
s
g
sd s
TL L= + + +
+ + +
1 1 2
5 510
2 2 22γ
ωω
δαγ
δαγ
( )Q
L L
R R CQL
s g
s s gsin=
+= ≈
ωω
12 * Q of the Input Circuit
α = ≤g
gm
d 0
1 Decreases with shorter channels
ci i
i ij
g d
g d
= =*
.2 2
0 395 Gate / Drain Correlation Factor
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Minimum Noise Factor
Take to find the condition for minimum F:∂
∂F
WM1
0=
QL opt, .= + ≥15
1872
γδα
F cT T
min .= +
+ +
≥ +
1
4
51
51 133
2
δγωω
δαγ
ωω
Long ChannelValues
Note: Worst-Case Fmin = 4 (6dB) when gm= gg.
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• MOS Device has gate current noise in addition todrain current noise. Optimum Zs exists.
• Optimum Qin relatively large. Power savingsand lower F by reducing WM1 for Qin < Qopt.
• HSPICE models of MOS noise are inadequate.
• Induced gate effects are not modeled at all.
• Hot Electron effects influence the noise power spectraldensity of channel-related noise sources.
Architecture / Noise Summary
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Outline
• LNA Architecture / RF Noise
• Experimental Results
• Summary and Conclusions
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Complete LNA Schematic
Vbias
Vdd Vdd
M1
M2M3
LgndLs
Ld Lout
Lvdd Lb2 Cb2
LgTm
Cm
Rs
Lb1
Cb1
M4
Vs
Input Bias Tee
Off Chip Matching
Output Bias Tee
To SpectrumAnalyzer
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Die Photo
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S21
Peak S21 22dB
Marker 2
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S11
VSWR 1.38
Marker 2
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S12
Marker 2
Null @ 1.5GHz
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Reverse Isolation
M1
M2M3
Lgnd
Ls
Ld Lout
Lg
Substrate Node
• Substrate tied to lowestinductance signal ground.
• Parasitic capacitances fromspiral inductors and padsdegrade reverse isolation.
• Simulation with parasiticsshows null in S12 as seen inexperimental data.
Cg1+Cpad Cg2 Cd Cpad
Cgd31 2
3
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0.00
5.00
10.00
15.00
20.00
25.00
30.00
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.90
2.00
Vdd (V)
NF
/ S
21 (
dB)
Noise Figure / S21 vs. Vdd
3.5dB NF / 22dB S21
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Linearity - IP3
-70.00
-60.00
-50.00
-40.00
-30.00
-20.00
-10.00
0.00
10.00
20.00
30.00
-36.
00
-34.
00
-32.
00
-30.
00
-28.
00
-26.
00
-24.
00
-22.
00
-20.
00
-18.
00
-16.
00
-14.
00
-12.
00
-10.
00
-8.0
0
-6.0
0
Source Power (dBm)
Out
put P
ower
(dB
m)
IP3 = -9.3dBm (Input)
1dB Comp. = -22dBm (Input)
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Outline
• LNA Architecture / RF Noise
• Experimental Results
• Summary and Conclusions
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Performance SummaryFrequency 1.5GHzNoise Figure 3.5dBS21 22dBIP3 (Input) -9.3dBm1dB Compression (Input) -22dBm
Supply Voltage 1.5VPower Dissipation 30mW
First Stage 7.5mW
Technology 0.6µm CMOSDie Area 0.12 mm2
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Conclusions
• CMOS is suitable for low noise above 1GHz.
• 3.5dB NF is lowest to date for CMOS above 1GHz.
• 1dB NF can be expected with current generation.
• Current CMOS noise models, as in HSPICE, areinadequate for accurate simulation of RF noise.
• Significant noise contributors are absent from the models.
• Short channel effects have not been properly accounted for.
• More research is required.
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Acknowledgments
Stanford Center for Integrated Systems
Air Force Office of Scientific Research
Howard Swain of Hewlett Packard
for many helpful discussions on CMOS noise
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