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How to use Xilinx ISE and insert ICON,

ILA, VIO cores to work on Chipscope

We use ISE 12.2 and Virtex-5 family board XUPV5-LX110T.

Step1 - Connect Power and Jtag usb to the board also computer and open our ISE

work station.

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Step2 - We are going to open a new project by clicking File -> New project.

Its going to show this window, type in the Name of project and click Next,

since were using a ADPCM encoder for this example, we will type in

ADPCM_encoder .

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Make sure the family, device, package and speed is chosen correct then click on

Next -> Finish .

Step3 Click the device on the Hierarchy tree then click add source at th e left of the

button, or from the tag on the top Source -> Add Source. ADPCMEncoder.v is

the source code we want to add, After adding click OK.

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Step4 From Source -> New Source and get this window, now we re going to

insert a core by using IP (core generator). Type in the name of the core, then click on

Next.

Step5 Now to insert a ICON core we follow the tree Debug & Verification ->

ChipScope Pro -> ICON, then click Next and Finish.

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Select two on the Control Ports since we re going to insert one ILA and one VIO core,

and press Generate.

Step6 Follow Step5 and the setup shown on the figure below to create an ILA and

VIO core. Click Next and make sure the width of each Trigger is correct for ILA then

click Generate, also check the width for the input and output of VIO core.

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Step7 From ICON we double click on View HDL Instantiation Template we can

copy the template on the right window and make connection with ADPCM. Follow

this step again for ILA and VIO. From the source code we can see the changes, file

ADPCM_encoder is the origin source code, and ADPCM_encoder(core) is the

source code after inserting the three cores.

Step8 Create a new source by Source -> New Source -> Implementation

Constraints File, type in the name and click Next then Finish.

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Step9 To generate a clock, we type in the following code in the .ucf file, also in

the PDF file ml50x_schematics, we can find all the address for the IO on the FPGA

board.

Next we click right button on Generate Programming File, under Startup

Options we set FPGA Start-Up Clock to JTAG Clock. After setting up we can

Implement the module by clicking the green arrow at the top.

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Step10 We open iMPACT from Tools -> iMPACT.

After iMPACT window is opened, we click on Initialize Chain, and select

the .bit file for the Virtex-5 FPGA. Then we chose the FPGA device and click

Program, when all the steps are finished we can close iMPACT.

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Step11 We can open chipscope by double clicking Analyze Design Using

ChipScope.

After opening chipscope pro, we click on the icon Open cable/Search for

JTAG chain on the left top of the window. Then on the left window right click on

Device4 then click on Configure -> Select New File and chose the .bit file and

click OK.

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Step12 Double click on VIO Console, set bus for the input and output then

rename it. Then we can provide input from the VIO core and see the chages of the

output as the figure below.

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Step13 Click on the ILA unit and set Data Prot to bus and rename it. If we click on

the arrow on the top of the window, we can get the waveforms according to our

settings.