Reul Thesis

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New Architectures in Computer ChessiiNew Architectures in Computer ChessPROEFSCHRIFTter verkrijging van de graad van doctoraan de Universiteit van Tilburg,op gezag van de rector magnicus,prof. dr. Ph. Eijlander,in het openbaar te verdedigen ten overstaan van eendoor het college voor promoties aangewezen commissiein de aula van de Universiteitop woensdag 17 juni 2009 om 10.15 uurdoorFritz Max Heinrich Reulgeboren op 30 september 1977 te Hanau, DuitslandPromotor: Prof. dr. H.J. van den HerikCopromotor: Dr. ir. J.W.H.M. UiterwijkPromotiecommissie: Prof. dr. A.P.J. van den BoschProf. dr. A. de BruinProf. dr. H.C. BuntProf. dr. A.J. van ZantenDr. U. LorenzDr. A. PlaatDissertation Series No. 2009-16The research reported in this thesis has been carried out under the auspices ofSIKS, the Dutch Research School for Information and Knowledge Systems.ISBN 9789490122249Printed by Gildeprint 2009 Fritz M.H. ReulAll rights reserved. No part of this publication may be reproduced, stored in aretrieval system, or transmitted, in any form or by any means, electronically,mechanically, photocopying, recording or otherwise, without prior permission ofthe author.PrefaceAbout ve years ago I completed my diploma project about computer chess atthe University of Applied Sciences in Friedberg, Germany. Immediately after-wards I continued in 2004 with the R&D of my computer-chess engine Loop.In 2005 I started my Ph.D. project New Architectures in Computer Chess atthe Maastricht University. In the rst year of my R&D I concentrated on theredesign of a computer-chess architecture for 32-bit computer environments. Ideveloped more ecient search methods and more precise evaluation functionsin order to carry out my R&D within the scope of a state-of-the-art computer-chess environment.In fall 2006 the development of my new 32-bit computer-chess architecture wascompleted. With the opening book by Gerhard Sonnabend and the hardwareprovided by Clemens Keck my computer-chess engine Loop Leiden achievedthe 2ndplace behind Rybka and before Hiarcs X MP at the 26thOpen DutchComputer-Chess Championship 2006 in Leiden (NL) (see Appendix C.1).In 2007, I started the next R&D phase on the basis of this computer-chess engine.The focus of this phase was on the development of a 64-bit computer-chessarchitecture that should be used within the scope of a quad-core computer-chessengine. The new 64-bit computer-chess engine, Loop Amsterdam, achievedthe 3rdplace behind Rybka and Zappa but before Shredder at the 15thWorldComputer-Chess Championship 2007 in Amsterdam (NL) (see Appendix C.2).For the persons who continuously supported me some words of gratitude are ap-propriate. In particular, I am grateful to my supervisor Professor Jaap van denHerik who brought me with rm guidance to this success. He stimulated me tocontinue the R&D of my computer-chess engine Loop Chess and motivated meto write this thesis. In addition, he set up the contact to the company Nintendoin 2007 which implemented my source codes successfully in their commercialproduct Wii Chess. Moreover, I would like to thank my daily advisor dr. JosUiterwijk for the many crucial suggestions and tips during the reading of mythesis.My thanks goes also to Dr. Christian Donninger (Chrilly) for his advisory inputduring the development of a parallel search engine and to Tord Romstad for hisassistance in generating magic multipliers. Gerhard Sonnabend and ClemensKeck helped me in the experiments that lasted many months and particularly inthe preparation for two important computer-chess championships, Great Work!vvi PREFACEFinally, I am grateful to Viktoria for her endurance and for her help on trans-lating the contents of the thesis. I feel great to my parents: in the thesis theysee the results of their education.Fritz Reul, 2009ContentsPreface vContents viiList of Figures xiList of Tables xiii1 Introduction 11.1 Architectures in Computer Chess . . . . . . . . . . . . . . . . . . 11.2 Preliminary Considerations . . . . . . . . . . . . . . . . . . . . . 31.3 Problem Statement and Research Questions . . . . . . . . . . . . 41.4 Research Methodology . . . . . . . . . . . . . . . . . . . . . . . . 61.5 Background of the Engine . . . . . . . . . . . . . . . . . . . . . . 61.6 Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Non-Bitboard Architectures 92.1 Implementation in Two External Projects . . . . . . . . . . . . . 112.1.1 The Chess Machine Hydra . . . . . . . . . . . . . . . . . . 112.1.2 Nintendo Wii Chess . . . . . . . . . . . . . . . . . . . . . 112.2 Computer Chessboard Design . . . . . . . . . . . . . . . . . . . . 122.2.1 Computer Chessboard Representation . . . . . . . . . . . 142.2.2 Distances and Increments . . . . . . . . . . . . . . . . . . 142.2.3 Minimal Board Borders . . . . . . . . . . . . . . . . . . . 162.2.4 One-dimensional Look-up Tables . . . . . . . . . . . . . . 172.3 Managing Information with Piece Lists . . . . . . . . . . . . . . . 212.3.1 Pieces and Piece Flags . . . . . . . . . . . . . . . . . . . . 212.3.2 Sequential and Recursive Piece Lists . . . . . . . . . . . . 222.3.3 Light and Dark Squares . . . . . . . . . . . . . . . . . . . 232.3.4 Forward | Reverse Piece-list Scan . . . . . . . . . . . . . . 242.3.5 Incremental Piece-list Update . . . . . . . . . . . . . . . . 242.3.6 Random Piece Arrangement . . . . . . . . . . . . . . . . . 272.4 Experiments with Pieces in Lists . . . . . . . . . . . . . . . . . . 282.4.1 The Experiment . . . . . . . . . . . . . . . . . . . . . . . 292.4.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292.5 Blocker Loops for Sliding Pieces . . . . . . . . . . . . . . . . . . . 312.5.1 The Sliding-direction Blocker Loop . . . . . . . . . . . . . 312.5.2 The Destination-Source Blocker Loop . . . . . . . . . . . 31viiviii CONTENTS2.6 Experiments with Loop Iterations . . . . . . . . . . . . . . . . . . 322.6.1 The Experiment . . . . . . . . . . . . . . . . . . . . . . . 332.6.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332.7 Answer to Research Question 1 . . . . . . . . . . . . . . . . . . . 343 Magic Hash Functions for Bitboards 393.1 Representation and Orientation of Bitboards . . . . . . . . . . . 413.1.1 8-bit Bitboards . . . . . . . . . . . . . . . . . . . . . . . . 413.1.2 16-bit Bitboards . . . . . . . . . . . . . . . . . . . . . . . 423.1.3 64-bit Bitboards . . . . . . . . . . . . . . . . . . . . . . . 423.2 Hash Functions based on Magic Multiplications . . . . . . . . . . 433.2.1 The Magic Multiplication . . . . . . . . . . . . . . . . . . 443.2.2 The Magic Multiplication by a Power of Two . . . . . . . 453.2.3 The Magic Multiplication by an n-bit Integer . . . . . . . 463.3 The Unique Magic Index . . . . . . . . . . . . . . . . . . . . . . . 483.3.1 Index Mapping for a Bit Scan . . . . . . . . . . . . . . . . 493.3.2 Index Mapping for Sliding Directions . . . . . . . . . . . . 493.4 Construction of 8-bit Magic Multipliers . . . . . . . . . . . . . . 513.5 The Magic Hash Function for a Bit Scan . . . . . . . . . . . . . . 533.5.1 Bit Scan Forward | Reverse . . . . . . . . . . . . . . . . . 533.5.2 Bit Scan Forward Implementation . . . . . . . . . . . . . 543.6 Magic Hash Functions for Sliding Directions . . . . . . . . . . . . 553.6.1 The Minimal Array Access Implementation . . . . . . . . 563.6.2 The Homogeneous Array Access Implementation . . . . . 573.7 Generation of Magic Multipliers . . . . . . . . . . . .