PIC16F886 DataSheet

7/31/2019 PIC16F886 DataSheet

1/327

2009 Microchip Technology Inc. DS41291F

PIC16F882/883/884/886/887Data Sheet

28/40/44-Pin, Enhanced Flash-Based 8-Bit

CMOS Microcontrollers with

nanoWatt Technology


2/327

DS41291F-page ii 2009 Microchip Technology Inc.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

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OTHERWISE, RELATED TO THE INFORMATION,

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conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

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All other trademarks mentioned herein are property of their

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2009, Microchip Technology Incorporated, Printed in the

U.S.A., All Rights Reserved.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as unbreakable.

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

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Microchip received ISO/TS-16949:2002 certification for its worldwideheadquarters, design and wafer fabrication facilities in Chandler andTempe, Arizona; Gresham, Oregon and design centers in Californiaand India. The Companys quality system processes and proceduresare for its PICMCUs and dsPICDSCs, KEELOQcode hoppingdevices, Serial EEPROMs, microperipherals, nonvolatile memory andanalog products. In addition, Microchips quality system for the designand manufacture of development systems is ISO 9001:2000 certified.


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2009 Microchip Technology Inc. DS41291F-page 1

PIC16F882/883/884/886/887

High-Performance RISC CPU:

Only 35 Instructions to Learn:

- All single-cycle instructions except branches

Operating Speed:

- DC 20 MHz oscillator/clock input

- DC 200 ns instruction cycle

Interrupt Capability

8-Level Deep Hardware Stack

Direct, Indirect and Relative Addressing modes

Special Microcontroller Features:

Precision Internal Oscillator:- Factory calibrated to 1%

- Software selectable frequency range of

8 MHz to 31 kHz

- Software tunable

- Two-Speed Start-up mode

- Crystal fail detect for critical applications

- Clock mode switching during operation for

power savings

Power-Saving Sleep mode

Wide Operating Voltage Range (2.0V-5.5V)

Industrial and Extended Temperature Range

Power-on Reset (POR)

Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST) Brown-out Reset (BOR) with Software Control

Option

Enhanced Low-Current Watchdog Timer (WDT)

with On-Chip Oscillator (software selectable

nominal 268 seconds with full prescaler) with

software enable

Multiplexed Master Clear with Pull-up/Input Pin

Programmable Code Protection

High Endurance Flash/EEPROM Cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM retention: > 40 years

Program Memory Read/Write during run time

In-Circuit Debugger (on board)

Low-Power Features:

Standby Current:

- 50 nA @ 2.0V, typical

Operating Current:

- 11 A @ 32 kHz, 2.0V, typical- 220 A @ 4 MHz, 2.0V, typical

Watchdog Timer Current:

- 1 A @ 2.0V, typical

Peripheral Features:

24/35 I/O Pins with Individual Direction Control:

- High current source/sink for direct LED drive

- Interrupt-on-Change pin

- Individually programmable weak pull-ups

- Ultra Low-Power Wake-up (ULPWU)

Analog Comparator Module with:

- Two analog comparators

- Programmable on-chip voltage reference

(CVREF) module (% of VDD)

- Fixed voltage reference (0.6V)

- Comparator inputs and outputs externallyaccessible

- SR Latch mode

- External Timer1 Gate (count enable)

A/D Converter:

- 10-bit resolution and 11/14 channels

Timer0: 8-bit Timer/Counter with 8-bit

Programmable Prescaler

Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Dedicated low-power 32 kHz oscillator

Timer2: 8-bit Timer/Counter with 8-bit Period

Register, Prescaler and Postscaler

Enhanced Capture, Compare, PWM+ Module:- 16-bit Capture, max. resolution 12.5 ns

- Compare, max. resolution 200 ns

- 10-bit PWM with 1, 2 or 4 output channels,

programmable dead time, max. frequency

20 kHz

- PWM output steering control

Capture, Compare, PWM Module:

- 16-bit Capture, max. resolution 12.5 ns

- 16-bit Compare, max. resolution 200 ns

- 10-bit PWM, max. frequency 20 kHz

Enhanced USART Module:

- Supports RS-485, RS-232, and LIN 2.0

- Auto-Baud Detect

- Auto-Wake-Up on Start bit In-Circuit Serial ProgrammingTM (ICSPTM) via Two

Pins

Master Synchronous Serial Port (MSSP) Module

supporting 3-wire SPI (all 4 modes) and I2C

Master and Slave Modes with I2C Address Mask

28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers withnanoWatt Technology


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PIC16F882/883/884/886/887

DS41291F-page 2 2009 Microchip Technology Inc.

Device

Program

MemoryData Memory

I/O10-bit A/D

(ch)

ECCP/

CCPEUSART MSSP Comparators

Timers

8/16-bitFlash

(words)

SRAM

(bytes)

EEPROM

(bytes)

PIC16F882 2048 128 128 24 11 1/1 1 1 2 2/1

PIC16F883 4096 256 256 24 11 1/1 1 1 2 2/1

PIC16F884 4096 256 256 35 14 1/1 1 1 2 2/1

PIC16F886 8192 368 256 24 11 1/1 1 1 2 2/1

PIC16F887 8192 368 256 35 14 1/1 1 1 2 2/1


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PIC16F882/883/884/886/887

Pin Diagrams PIC16F882/883/886, 28-Pin PDIP, SOIC, SSOP

TABLE 1: PIC16F882/883/886 28-PIN SUMMARY (PDIP, SOIC, SSOP)I/O Pin Analog Comparators Timers ECCP EUSART MSSP Interrupt Pull-up Basic

RA0 2 AN0/ULPWU C12IN0-

RA1 3 AN1 C12IN1-

RA2 4 AN2 C2IN+ VREF-/CVREF

RA3 5 AN3 C1IN+ VREF+

RA4 6 C1OUT T0CKI

RA5 7 AN4 C2OUT SS

RA6 10 OSC2/CLKOUT

RA7 9 OSC1/CLKIN

RB0 21 AN12 IOC/INT Y

RB1 22 AN10 C12IN3- P1C IOC Y

RB2 23 AN8 P1B IOC Y

RB3 24 AN9 C12IN2- IOC Y PGM

RB4 25 AN11 P1D IOC Y

RB5 26 AN13 T1G IOC Y

RB6 27 IOC Y ICSPCLK

RB7 28 IOC Y ICSPDAT

RC0 11 T1OSO/T1CKI

RC1 12 T1OSI CCP2

RC2 13 CCP1/P1A

RC3 14 SCK/SCL

RC4 15 SDI/SDA

RC5 16 SDO RC6 17 TX/CK

RC7 18 RX/DT

RE3 1 Y(1) MCLR/VPP

20 VDD

8 VSS

19 VSS

Note 1: Pull-up activated only with external MCLR configuration.

10

11

2

3

4

5

6

1

8

7

9

12

13

14 15

16

17

18

19

20

23

24

25

26

27

28

22

21

PIC16F882/883/886

RE3/MCLR/VPP

RA0/AN0/ULPWU/C12IN0-

RA1/AN1/C12IN1-

RA2/AN2/VREF-/CVREF/C2IN+

RA3/AN3/VREF+/C1IN+

RA4/T0CKI/C1OUT

RA5/AN4/SS/C2OUT

VSS

RA7/OSC1/CLKIN

RA6/OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/P1A/CCP1

RC3/SCK/SCL

RB7/ICSPDAT

RB6/ICSPCLK

RB5/AN13/T1G

RB4/AN11/P1D

RB3/AN9/PGM/C12IN2-

RB2/AN8/P1B

RB1/AN10/P1C/C12IN3-

RB0/AN12/INT

VDD

VSS

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

28-pin PDIP, SOIC, SSOP


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PIC16F882/883/884/886/887


Pin Diagrams PIC16F882/883/886, 28-Pin QFN

16

2

7

1

3

6

5

4

15

21

19

20

17

18

22

28

26

27

23

24

25

14

8 10

9 13

12

11

PIC16F882/883/886

RA1/AN1/C12IN1-


RE3/MCLR/VPP

RB7/ICSPDAT

RB6/ICSPCLK

RB5/AN13/T1G

RB4/AN11/P1D

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC

2/P1A/CCP1

RC3/SCK/SCL

R

C4/SDI/SDA

RC5/SDO

RC6/TX/CK


RA3/AN3/VREF+/C1IN+

RA4/T0CKI/C1OUTRA5/AN4/SS/C2OUT

VSS

RA7/OSC1/CLKIN

RA6/OSC2/CLKOUT

RB3/AN9/PGM/C12IN2-

RB2/AN8/P1B

RB1/AN10/P1C/C12IN3-RB0/AN12/INT

VDD

VSS

RC7/RX/DT

28-pin QFN


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PIC16F882/883/884/886/887

TABLE 2: PIC16F882/883/886 28-PIN SUMMARY (QFN)

I/O Pin Analog Comparators Timers ECCP EUSART MSSP Interrupt Pull-up Basic


RA1 28 AN1 C12IN1-



RA4 3 C1OUT T0CKI

RA5 4 AN4 C2OUT SS

RA6 7 OSC2/CLKOUT

RA7 6 OSC1/CLKIN


RB1 19 AN10 C12IN3- P1C IOC Y

RB2 20 AN8 P1B IOC Y


RB4 22 AN11 P1D IOC Y




RC0 8 T1OSO/T1CKI

RC1 9 T1OSI CCP2

RC2 10 CCP1/P1A

RC3 11 SCK/SCL

RC4 12 SDI/SDA

RC5 13 SDO

RC6 14 TX/CK

RC7 15 RX/DT

RE3 26 Y(1) MCLR/VPP

17 VDD

5 VSS

16 VSS



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PIC16F882/883/884/886/887


Pin Diagrams PIC16F884/887, 40-Pin PDIP

1

2

3

4

5

6

7

8

9

10

11

12

13

14

1516

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

2625

24

23

22

21

PIC16F884/887

RE3/MCLR/VPP


RA1/AN1/C12IN1-


RA3/AN3/VREF+/C1IN+

RA4/T0CKI/C1OUT

RA5/AN4/SS/C2OUT

RE0/AN5

RE1/AN6

RE2/AN7

VDD

VSS

RA7/OSC1/CLKIN

RA6/OSC2/CLKOUT

RC0/T1OSO/T1CKIRC1/T1OSI/CCP2

RC2/P1A/CCP1

RC3/SCK/SCL

RD0

RD1

RB7/ICSPDAT

RB6/ICSPCLK

RB5/AN13/T1G

RB4/AN11

RB3/AN9/PGM/C12IN2-

RB2/AN8

RB1/AN10/C12IN3-

RB0/AN12/INT

VDD

VSS

RD7/P1D

RD6/P1C

RD5/P1B

RD4

RC7/RX/DTRC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3

RD2

40-pin PDIP


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PIC16F882/883/884/886/887

TABLE 3: PIC16F884/887 40-PIN SUMMARY (PDIP)



RA1 3 AN1 C12IN1-



RA4 6 C1OUT T0CKI

RA5 7 AN4 C2OUT SS

RA6 14 OSC2/CLKOUT

RA7 13 OSC1/CLKIN


RB1 34 AN10 C12IN3- IOC Y

RB2 35 AN8 IOC Y


RB4 37 AN11 IOC Y




RC0 15 T1OSO/T1CKI

RC1 16 T1OSI CCP2

RC2 17 CCP1/P1A

RC3 18 SCK/SCL

RC4 23 SDI/SDA

RC5 24 SDO

RC6 25 TX/CK

RC7 26 RX/DT

RD0 19

RD1 20

RD2 21

RD3 22 RD4 27

RD5 28 P1B

RD6 29 P1C

RD7 30 P1D

RE0 8 AN5

RE1 9 AN6

RE2 10 AN7

RE3 1 Y(1) MCLR/VPP

11 VDD

32 VDD

12 VSS

31 VSS



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PIC16F882/883/884/886/887


Pin Diagrams PIC16F884/887, 44-Pin QFN

44-pin QFN

1011

2

3

6

1

1819

202122

12131415

38

87

444342414039

1617

293031

3233

232425262728

36

34

35

9

37

54

PIC16F884/887

RA6/OSC2/CLKOUTRA7/OSC1/CLKINVSSVSSNCVDDRE2/AN7RE1/AN6RE0/AN5RA5/AN4/SS/C2OUTRA4/T0CKI/C1OUT

RC7/RX/DTRD4

RD5/P1BRD6/P1CRD7/P1D

VSSVDDVDD

RB0/AN12/INTRB1/AN10/C12IN3-

RB2/AN8

RB3/AN9/PGM/C12IN2-NC

R

B4/AN11

RB5/AN13/T1G

RB6/ICSPCLK

RB7/ICSPDAT

RE3/MCLR/VPP


RA1/AN1/C12IN1-


RA3/AN3//VREF+/C1IN+

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3

RD2

RD1

RD0

RC3/SCK/SCL

RC2/P1A/CCP1

RC1/T1OSCI/CCP2

RC0/T1OSO/T1CKI


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PIC16F882/883/884/886/887

TABLE 4: PIC16F884/887 44-PIN SUMMARY (QFN)



RA1 20 AN1 C12IN1-



RA4 23 C1OUT T0CKI

RA5 24 AN4 C2OUT SS

RA6 33 OSC2/CLKOUT

RA7 32 OSC1/CLKIN



RB2 11 AN8 IOC Y


RB4 14 AN11 IOC Y




RC0 34 T1OSO/T1CKI

RC1 35 T1OSI CCP2

RC2 36 CCP1/P1A

RC3 37 SCK/SCL

RC4 42 SDI/SDA

RC5 43 SDO

RC6 44 TX/CK

RC7 1 RX/DT

RD0 38

RD1 39

RD2 40

RD3 41 RD4 2

RD5 3 P1B

RD6 4 P1C

RD7 5 P1D

RE0 25 AN5

RE1 26 AN6

RE2 27 AN7


7 VDD

8 VDD

28 VDD

6 VSS

30 VSS

31 VSS

13 NC (no connect)

29 NC (no connect)



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PIC16F882/883/884/886/887


Pin Diagrams PIC16F884/887, 44-Pin TQFP

44-pin TQFP

1011

2

3

6

1

1819

202122

12131415

38

87

444342414039

1617

293031

3233

232425262728

36

34

35

9

37

54

PIC16F884/887

NCRC0/T1OSO/T1CKIRA6/OSC2/CLKOUTRA7/OSC1/CLKINVSSVDDRE2/AN7RE1/AN6RE0/AN5RA5/AN4/SS/C2OUTRA4/T0CKI/C1OUT

RC7/RX/DTRD4

RD5/P1BRD6/P1CRD7/P1D

VSSVDD

RB0/AN12/INTRB1/AN10/C12IN3-

RB2/AN8RB3/AN9/PGM/C12IN2-

NCNC

RB4/A

N11

RB5/AN13/T1G

RB6/ICSP

CLK

RB7/ICSP

DAT

RE3/MCLR

/VPP

RA0/AN0/ULPWU/C12

IN0-

RA1/AN1/C12

IN1-


RA3/AN3//VREF+/C1IN+

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3

RD2

RD1

RD0

RC3/SCK/SCL

RC2/P1A/CCP1

RC1/T1OSCI/CCP2

NC


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PIC16F882/883/884/886/887

TABLE 5: PIC16F884/887 44-PIN SUMMARY (TQFP)



RA1 20 AN1 C12IN1-



RA4 23 C1OUT T0CKI

RA5 24 AN4 C2OUT SS

RA6 31 OSC2/CLKOUT

RA7 30 OSC1/CLKIN



RB2 10 AN8 IOC Y


RB4 14 AN11 IOC Y




RC0 32 T1OSO/T1CKI

RC1 35 T1OSI CCP2

RC2 36 CCP1/P1A

RC3 37 SCK/SCL

RC4 42 SDI/SDA

RC5 43 SDO

RC6 44 TX/CK

RC7 1 RX/DT

RD0 38

RD1 39

RD2 40

RD3 41 RD4 2

RD5 3 P1B

RD6 4 P1C

RD7 5 P1D

RE0 25 AN5

RE1 26 AN6

RE2 27 AN7


7 VDD

28 VDD

6 VSS

13 NC (no connect)

29 VSS

34 NC (no connect)

33 NC (no connect)

12 NC (no connect)



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PIC16F882/883/884/886/887


Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 13

2.0 Memory Organization ................................................................................................................................................................. 21

3.0 I/O Ports ..................................................................................................................................................................................... 39

4.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 61

5.0 Timer0 Module ........................................................................................................................................................................... 73

6.0 Timer1 Module with Gate Control............................................................................................................................................... 76

7.0 Timer2 Module ........................................................................................................................................................................... 818.0 Comparator Module.................................................................................................................................................................... 83

9.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 99

10.0 Data EEPROM and Flash Program Memory Control............................................................................................................... 111

11.0 Enhanced Capture/Compare/PWM Module ............................................................................................................................. 123

12.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 151

13.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 179

14.0 Special Features of the CPU.................................................................................................................................................... 209

15.0 Instruction Set Summary .......................................................................................................................................................... 231

16.0 Development Support............................................................................................................................................................... 241

17.0 Electrical Specifications............................................................................................................................................................ 245

18.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 273

19.0 Packaging Information.............................................................................................................................................................. 301

Appendix A: Data Sheet Revision History....... ............... ................ ............... ............... ................ ................. ............... ............... ....... 313

Appendix B: Migrating from other PIC Devices ............. .................. ............... ............... ............... .................. ............... ............... ... 313

Index .................................................................................................................................................................................................. 315

The Microchip Web Site ............... ............... ................ ............... ............... ............... .................... ............... ............... ............... ......... 323

Customer Change Notification Service ............. ............... ................ ................. ............... ............... .................. ............... ............... ... 323

Customer Support ............... ............... ............... ............... ................ ............... ............... ................. ................ ............... ............... ..... 323

Reader Response ............... ............... ............... ............... ................ ............... ............... ................. ................ ............... ............... ..... 324

Product Identification System............... ............... ............... ................ ............... ............... ................... ............... ................ ............... . 325

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PIC16F882/883/884/886/887

1.0 DEVICE OVERVIEW

The PIC16F882/883/884/886/887 is covered by this

data sheet. The PIC16F882/883/886 is available in 28-

pin PDIP, SOIC, SSOP and QFN packages. The

PIC16F884/887 is available in a 40-pin PDIP and 44-

pin QFN and TQFP packages. Figure 1-1 shows the

block diagram of PIC16F882/883/886 and Figure 1-2shows a block diagram of the PIC16F884/887 device.Table 1-1 and Table 1-2 show the corresponding pinout

descriptions.


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PIC16F882/883/884/886/887


FIGURE 1-1: PIC16F882/883/886 BLOCK DIAGRAM

Flash

ProgramMemory

13Data Bus

8

Program

Bus

Instruction Reg

Program Counter

RAM

FileRegisters

Direct Addr 7

RAM Addr9

Addr MUX

IndirectAddr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

InstructionDecode and

Control

TimingGeneration

OSC1/CLKIN

OSC2/CLKOUT

8

8

8

3

8-Level Stack 128(2)/256(1)/

2K(2)/4K(1)/

(13-Bit)

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

MCLR VSS

Brown-out

Reset

Timer0 Timer1

Data

EEPROM

128(2)/

EEDATA

EEADDR

T0CKI T1CKI

Configuration

InternalOscillator

T1G

VDD

8

Timer2 ECCP

Block

2 Analog ComparatorsVREF+

and Reference

Analog-To-Digital Converter(ADC)

AN0

AN1

AN2

AN3

AN4

AN8

AN9

AN10

AN11

AN12

AN13

C1IN+

C12IN0-

C12IN1-

C12IN2-

C12IN3-

C1OUT

C2IN+

C2OUT

CCP1/P1A

P1B

P1C

P1D

PORTA

PORTC

RC0

RC1RC2

RC3RC4

RC5RC6

RC7

PORTB

EUSART

TX/CK

RX/DT

PORTE

RE3

RA0RA1

RA2

RA3

RA4

RA5RA6

RA7

RB0

RB1

RB2

RB3RB4

RB5

RB6

RB7

Timer132 kHz

Oscillator

Master Synchronous

Serial Port (MSSP)

CCP2

CCP2

SDO

SDI/SDA

SCK/SCL

SS

VREF-

14

Note 1: PIC16F883 only.

2: PIC16F882 only.

VREF+

VREF-

CVREF

In-CircuitDebugger

(ICD)

T1OSI

T1OSO

8K X 14

368 Bytes

256 Bytes


17/327


PIC16F882/883/884/886/887

FIGURE 1-2: PIC16F884/PIC16F887 BLOCK DIAGRAM

PORTD

RD0

RD1

RD2

RD3RD4

RD5

RD6

RD7

Flash

Program

Memory

13Data Bus

8

Program

Bus

Instruction Reg

Program Counter

RAM

File

Registers

Direct Addr 7

RAM Addr9

Addr MUX

IndirectAddr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

InstructionDecode and

Control

TimingGeneration

OSC1/CLKIN

OSC2/CLKOUT

8

8

8

3

8-Level Stack 256(1)/368 Bytes

4K(1)/8K X 14

(13-Bit)

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

MCLR VSS

Brown-out

Reset

Timer0 Timer1

Data

EEPROM

256 Bytes

EEDATA

EEADDR

T0CKI T1CKI

Configuration

InternalOscillator

T1G

VDD

8

Timer2 ECCP

Block

2 Analog Comparators

and Reference

Analog-To-Digital Converter(ADC)

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN12

AN13

PORTA

PORTC

RC0

RC1RC2

RC3RC4

RC5RC6

RC7

PORTB

EUSART

PORTE

RA0

RA1

RA2

RA3

RA4

RA5RA6

RA7

RB0

RB1

RB2

RB3RB4

RB5

RB6

RB7

Timer132 kHz

Oscillator

Master Synchronous

Serial Port (MSSP)

CCP2

CCP2

14

Note 1: PIC16F884 only.

RE0RE1

RE2

RE3

SDO

SDI/SDA

SCK/SCL

SS

CCP1/P1A

P1B

P1C

P1D

TX/CK

RX/DT

VREF+

VREF-

VREF+

VREF-

CVREF

C1IN+

C12IN0-

C12IN1-

C12IN2-

C12IN3-

C1OUT

C2IN+

C2OUT

In-CircuitDebugger

(ICD)

T1OSI

T1OSO


18/327

PIC16F882/883/884/886/887


TABLE 1-1: PIC16F882/883/886 PINOUT DESCRIPTION

Name FunctionInput

Type

Output

TypeDescription

RA0/AN0/ULPWU/C12IN0- RA0 TTL CMOS General purpose I/O.

AN0 AN A/D Channel 0 input.

ULPWU AN Ultra Low-Power Wake-up input.C12IN0- AN Comparator C1 or C2 negative input.

RA1/AN1/C12IN1- RA1 TTL CMOS General purpose I/O.


C12IN1- AN Comparator C1 or C2 negative input.

RA2/AN2/VREF-/CVREF/C2IN+ RA2 TTL CMOS General purpose I/O.

AN2 AN A/D Channel 2.

VREF- AN A/D Negative Voltage Reference input.

CVREF AN Comparator Voltage Reference output.

C2IN+ AN Comparator C2 positive input.

RA3/AN3/VREF+/C1IN+ RA3 TTL General purpose I/O.


VREF+ AN Programming voltage.C1IN+ AN Comparator C1 positive input.

RA4/T0CKI/C1OUT RA4 TTL CMOS General purpose I/O.

T0CKI ST Timer0 clock input.

C1OUT CMOS Comparator C1 output.

RA5/AN4/SS/C2OUT RA5 TTL CMOS General purpose I/O.


SS ST Slave Select input.


RA6/OSC2/CLKOUT RA6 TTL CMOS General purpose I/O.

OSC2 XTAL Master Clear with internal pull-up.

CLKOUT CMOS FOSC/4 output.

RA7/OSC1/CLKIN RA7 TTL CMOS General purpose I/O.OSC1 XTAL Crystal/Resonator.

CLKIN ST External clock input/RC oscillator connection.

RB0/AN12/INT RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.


INT ST External interrupt.

RB1/AN10/P1C/C12IN3- RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.



P1C CMOS PWM output.


RB2/AN8/P1B RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.



P1B CMOS PWM output.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels

HV = High Voltage XTAL = Crystal


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PIC16F882/883/884/886/887

RB3/AN9/PGM/C12IN2- RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.



PGM ST Low-voltage ICSP Programming enable pin.C12IN2- AN Comparator C1 or C2 negative input.

RB4/AN11/P1D RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.



P1D CMOS PWM output.

RB5/AN13/T1G RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.



T1G ST Timer1 Gate input.

RB6/ICSPCLK RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.


ICSPCLK ST Serial Programming Clock.

RB7/ICSPDAT RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.Individually enabled pull-up.

ICSPDAT ST CMOS ICSP Data I/O.

RC0/T1OSO/T1CKI RC0 ST CMOS General purpose I/O.

T1OSO CMOS Timer1 oscillator output.


RC1/T1OSI/CCP2 RC1 ST CMOS General purpose I/O.

T1OSI ST Timer1 oscillator input.

CCP2 ST CMOS Capture/Compare/PWM2.

RC2/P1A/CCP1 RC2 ST CMOS General purpose I/O.

P1A CMOS PWM output.


RC3/SCK/SCL RC3 ST CMOS General purpose I/O.SCK ST CMOS SPI clock.

SCL ST OD I2C clock.

RC4/SDI/SDA RC4 ST CMOS General purpose I/O.

SDI ST SPI data input.

SDA ST OD I2C data input/output.

RC5/SDO RC5 ST CMOS General purpose I/O.

SDO CMOS SPI data output.

RC6/TX/CK RC6 ST CMOS General purpose I/O.

TX CMOS EUSART asynchronous transmit.

CK ST CMOS EUSART synchronous clock.

RC7/RX/DT RC7 ST CMOS General purpose I/O.

RX ST EUSART asynchronous input.

DT ST CMOS EUSART synchronous data.

RE3/MCLR/VPP RE3 TTL General purpose input.

MCLR ST Master Clear with internal pull-up.

VPP HV Programming voltage.

VSS VSS Power Ground reference.

VDD VDD Power Positive supply.

TABLE 1-1: PIC16F882/883/886 PINOUT DESCRIPTION (CONTINUED)

Name FunctionInput

Type

Output

TypeDescription





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PIC16F882/883/884/886/887


TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION

Name FunctionInput

Type

Output

TypeDescription

RA0/AN0/ULPWU/C12IN0- RA0 TTL CMOS General purpose I/O.


ULPWU AN Ultra Low-Power Wake-up input.C12IN0- AN Comparator C1 or C2 negative input.

RA1/AN1/C12IN1- RA1 TTL CMOS General purpose I/O.



RA2/AN2/VREF-/CVREF/C2IN+ RA2 TTL CMOS General purpose I/O.


VREF- AN A/D Negative Voltage Reference input.

CVREF AN Comparator Voltage Reference output.


RA3/AN3/VREF+/C1IN+ RA3 TTL CMOS General purpose I/O.


VREF+ AN A/D Positive Voltage Reference input.


RA4/T0CKI/C1OUT RA4 TTL CMOS General purpose I/O.



RA5/AN4/SS/C2OUT RA5 TTL CMOS General purpose I/O.


SS ST Slave Select input.


RA6/OSC2/CLKOUT RA6 TTL CMOS General purpose I/O.

OSC2 XTAL Crystal/Resonator.

CLKOUT CMOS FOSC/4 output.

RA7/OSC1/CLKIN RA7 TTL CMOS General purpose I/O.

OSC1 XTAL Crystal/Resonator.

CLKIN ST External clock input/RC oscillator connection.

RB0/AN12/INT RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.



INT ST External interrupt.

RB1/AN10/C12IN3- RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.




RB2/AN8 RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.AN8 AN A/D Channel 8.

RB3/AN9/PGM/C12IN2- RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.



PGM ST Low-voltage ICSP Programming enable pin.






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PIC16F882/883/884/886/887

RB4/AN11 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.



RB5/AN13/T1G RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.Individually enabled pull-up.


T1G ST Timer1 Gate input.

RB6/ICSPCLK RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.


ICSPCLK ST Serial Programming Clock.

RB7/ICSPDAT RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.


ICSPDAT ST TTL ICSP Data I/O.

RC0/T1OSO/T1CKI RC0 ST CMOS General purpose I/O.

T1OSO XTAL Timer1 oscillator output.


RC1/T1OSI/CCP2 RC1 ST CMOS General purpose I/O.

T1OSI XTAL Timer1 oscillator input.


RC2/P1A/CCP1 RC2 ST CMOS General purpose I/O.

P1A ST CMOS PWM output.

CCP1 CMOS Capture/Compare/PWM1.

RC3/SCK/SCL RC3 ST CMOS General purpose I/O.

SCK ST CMOS SPI clock.

SCL ST OD I2C clock.

RC4/SDI/SDA RC4 ST CMOS General purpose I/O.

SDI ST SPI data input.

SDA ST OD I2

C data input/output.RC5/SDO RC5 ST CMOS General purpose I/O.

SDO CMOS SPI data output.

RC6/TX/CK RC6 ST CMOS General purpose I/O.

TX CMOS EUSART asynchronous transmit.

CK ST CMOS EUSART synchronous clock.

RC7/RX/DT RC7 ST CMOS General purpose I/O.

RX ST EUSART asynchronous input.

DT ST CMOS EUSART synchronous data.

RD0 RD0 TTL CMOS General purpose I/O.





RD5/P1B RD5 TTL CMOS General purpose I/O.

P1B CMOS PWM output.

RD6/P1C RD6 TTL CMOS General purpose I/O.

P1C CMOS PWM output.

TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION (CONTINUED)

Name FunctionInput

Type

Output

TypeDescription





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PIC16F882/883/884/886/887


RD7/P1D RD7 TTL CMOS General purpose I/O.

P1D AN PWM output.

RE0/AN5 RE0 TTL CMOS General purpose I/O.






RE3/MCLR/VPP RE3 TTL General purpose input.

MCLR ST Master Clear with internal pull-up.

VPP HV Programming voltage.

VSS VSS Power Ground reference.

VDD VDD Power Positive supply.

TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION (CONTINUED)

Name FunctionInput

Type

Output

TypeDescription





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PIC16F882/883/884/886/887

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC16F882/883/884/886/887 has a 13-bit program

counter capable of addressing a 2K x 14 (0000h-07FFh)

for the PIC16F882, 4K x 14 (0000h-0FFFh) for the

PIC16F883/PIC16F884, and 8K x 14 (0000h-1FFFh) forthe PIC16F886/PIC16F887 program memory space.

Accessing a location above these boundaries will cause

a wrap-around within the first 8K x 14 space. The Reset

vector is at 0000h and the interrupt vector is at 0004h

(see Figures 2-2 and 2-3).

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F882


AND STACK FOR THEPIC16F883/PIC16F884


AND STACK FOR THEPIC16F886/PIC16F887

PC

13

0000h

0004h

0005h

07FFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

CALL, RETURN

RETFIE, RETLW

Stack Level 2

Page 0

On-ChipProgramMemory

PC

13

0000h

0004h

0005h

07FFh0800h

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

CALL, RETURN

RETFIE, RETLW

Stack Level 2

Page 0

Page 1

0FFFh


PC

13

0000h

0004h

0005h

07FFh

0800h

17FFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

CALL, RETURN

RETFIE, RETLW

Stack Level 2

Page 0

Page 1

Page 2

Page 3

0FFFh1000h

1FFFh

1800h



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PIC16F882/883/884/886/887


2.2 Data Memory Organization

The data memory (see Figures 2-2 and 2-3) is

partitioned into four banks which contain the General

Purpose Registers (GPR) and the Special Function

Registers (SFR). The Special Function Registers are

located in the first 32 locations of each bank. The

General Purpose Registers, implemented as static RAM,are located in the last 96 locations of each Bank.

Register locations F0h-FFh in Bank 1, 170h-17Fh in

Bank 2 and 1F0h-1FFh in Bank 3, point to addresses

70h-7Fh in Bank 0. The actual number of General

Purpose Resisters (GPR) implemented in each Bank

depends on the device. Details are shown in Figures 2-5

and 2-6. All other RAM is unimplemented and returns 0

when read. RP of the STATUS register are the

bank select bits:

RP1 RP0

0 0 Bank 0 is selected




2.2.1 GENERAL PURPOSE REGISTERFILE

The register file is organized as 128 x 8 in the

PIC16F882, 256 x 8 in the PIC16F883/PIC16F884, and

368 x 8 in the PIC16F886/PIC16F887. Each register is

accessed, either directly or indirectly, through the File

Select Register (FSR) (see Section 2.4 Indirect

Addressing, INDF and FSR Registers).

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Table 2-1). These

registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function Registers

associated with the core are described in this section.

Those related to the operation of the peripheral

features are described in the section of that peripheral

feature.


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PIC16F882/883/884/886/887

FIGURE 2-4: PIC16F882SPECIAL FUNCTION REGISTERS

File File File File

Address Address Address Address

Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h WDTCON 105h SRCON 185h

PORTB 06h TRISB 86h PORTB 106h TRISB 186h

PORTC 07h TRISC 87h CM1CON0 107h BAUDCTL 187h

08h 88h CM2CON0 108h ANSEL 188h

PORTE 09h TRISE 89h CM2CON1 109h ANSELH 189h

PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah

INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch

PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh

TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved 18Eh

TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh

T1CON 10h OSCTUNE 90h 110h 190h

TMR2 11h SSPCON2 91h 111h 191h

T2CON 12h PR2 92h 112h 192h

SSPBUF 13h SSPADD 93h 113h 193h

SSPCON 14h SSPSTAT 94h 114h 194h

CCPR1L 15h WPUB 95h 115h 195h

CCPR1H 16h IOCB 96h 116h 196h

CCP1CON 17h VRCON 97h 117h 197h

RCSTA 18h TXSTA 98h 118h 198h

TXREG 19h SPBRG 99h 119h 199h

RCREG 1Ah SPBRGH 9Ah 11Ah 19Ah

CCPR2L 1Bh PWM1CON 9Bh 11Bh 19Bh

CCPR2H 1Ch ECCPAS 9Ch 11Ch 19Ch

CCP2CON 1Dh PSTRCON 9Dh 11Dh 19Dh

ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh

ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh

General

Purpose

Registers

96 Bytes

20h General

Purpose

Registers

32 Bytes

A0h

BFh

120h 1A0h

C0h

EFh 16Fh 1EFh

accesses

70h-7Fh

F0h accesses

70h-7Fh

170h accesses

70h-7Fh

1F0h

7Fh FFh 17Fh 1FFh

Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as 0.

Note 1: Not a physical register.


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PIC16F882/883/884/886/887


FIGURE 2-5: PIC16F883/PIC16F884 SPECIAL FUNCTION REGISTERS

File File File File










PORTD(2) 08h TRISD(2) 88h CM2CON0 108h ANSEL 188h








T1CON 10h OSCTUNE 90h 110h 190h


T2CON 12h PR2 92h 112h 192h






RCSTA 18h TXSTA 98h 118h 198hTXREG 19h SPBRG 99h 119h 199h







General

Purpose

Registers

96 Bytes

20hGeneral

Purpose

Registers

80 Bytes

A0hGeneral

Purpose

Registers

80 Bytes

120h 1A0h

EFh 16Fh 1EFh

accesses

70h-7Fh

F0h accesses

70h-7Fh

170h accesses

70h-7Fh

1F0h

7Fh FFh 17Fh 1FFh




2: PIC16F884 only.


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PIC16F882/883/884/886/887

FIGURE 2-6: PIC16F886/PIC16F887 SPECIAL FUNCTION REGISTERS

File File File File










PORTD(2) 08h TRISD(2) 88h CM2CON0 108h ANSEL 188h








T1CON 10h OSCTUNE 90h

General

Purpose

Registers

16 Bytes

110h

General

Purpose

Registers

16 Bytes

190h


T2CON 12h PR2 92h 112h 192h






RCSTA 18h TXSTA 98h 118h 198hTXREG 19h SPBRG 99h 119h 199h







General

Purpose

Registers

96 Bytes

20h

3Fh

General

Purpose

Registers

80 Bytes

A0h

General

Purpose

Registers

80 Bytes

120h

General

Purpose

Registers

80 Bytes

1A0h

40h

6Fh EFh 16Fh 1EFh

70h accesses

70h-7Fh

F0h accesses

70h-7Fh

170h accesses

70h-7Fh

1F0h

7Fh FFh 17Fh 1FFh




2: PIC16F887 only.


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PIC16F882/883/884/886/887


TABLE 2-1: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value on

POR, BORPage

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 37,217

01h TMR0 Timer0 Module Register xxxx xxxx 73,217

02h PCL Program Counters (PC) Least Significant Byte 0000 0000 37,21703h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 29,217

04h FSR Indirect Data Memory Address Pointer xxxx xxxx 37,217

05h PORTA(3) RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx 39,217

06h PORTB(3) RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 48,217

07h PORTC(3) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 53,217

08h PORTD(3,4) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 57,217

09h PORTE(3) RE3 RE2(4) RE1(4) RE0(4) ---- xxxx 59,217

0Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 37,217

0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 31,217

0Ch PIR1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 34,217

0Dh PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF CCP2IF 0000 00-0 35,217

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 76,217

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 76,217

10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 79,217

11h TMR2 Timer2 Module Register 0000 0000 81,217

12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 82,217

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 183,217

14h SSPCON(2) WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 181,217

15h CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) xxxx xxxx 126,217

16h CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) xxxx xxxx 126,217

17h CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 124,217

18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 161,217

19h TXREG EUSART Transmit Data Register 0000 0000 153,217

1Ah RCREG EUSART Receive Data Register 0000 0000 158,217

1Bh CCPR2L Capture/Compare/PWM Register 2 Low Byte (LSB) xxxx xxxx 126,217

1Ch CCPR2H Capture/Compare/PWM Register 2 High Byte (MSB) xxxx xxxx 126,218

1Dh CCP2CON DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 125,218

1Eh ADRESH A/D Resu lt Register High Byte xxxx xxxx 99,218

1Fh ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 104,218

Legend: = Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if themismatch exists.

2: When SSPCON register bits SSPM = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSKregister. See Registers and 13-4 for more detail.

3: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read 0 immediately after a Reset even though thedata latches are either undefined (POR) or unchanged (other Resets).

4: PIC16F884/PIC16F887 only.


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PIC16F882/883/884/886/887



POR, BORPage

Bank 1


81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 30,218

82h PCL Program Counters (PC) Least Significant Byte 0000 0000 37,217

83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 29,217


85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 39,218

86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 48,218

87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 53,218

88h TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 57,218

89h TRISE TRISE3 TRISE2(3) TRISE1(3) TRISE0(3) ---- 1111 59,218

8Ah PCLATH Write Buffer for the upper 5 bits of the Program Counter ---0 0000 37,217


8Ch PIE1 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 32,218

8Dh PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE CCP2IE 0000 00-0 33,218

8Eh PCON ULPWUE SBOREN POR BOR --01 --qq 36,218

8Fh OSCCON IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 62,218

90h OSCTUNE TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 66,218

91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 181,218

92h PR2 Timer2 Period Register 1111 1111 81,218

93h SSPADD(2)

Synchronous Serial Port (I2C mode) Address Register 0000 0000 189,218

93h SSPMSK(2)

MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 189,218

94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 189,218

95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 49,218

96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 49,218

97h VRCON VREN VROE VRR VRSS VR3 VR2 VR1 VR0 0000 0000 97,218

98h TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 160,218

99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 163,218

9Ah SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 163,218

9Bh PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 145,218

9Ch ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 142,218

9Dh PSTRCON STRSYNC STRD STRC STRB STRA ---0 0001 146,218

9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 99,218

9Fh ADCON1 ADFM VCFG1 VCFG0 0-00 ---- 105,218


Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if themismatch exists.

2: Accessible only when SSPCON register bits SSPM = 1001.



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POR, BORPage

Bank 2


101h TMR0 Timer0 Module Register xxxx xxxx 73,217

102h PCL Program Counter s (PC) Least Significant Byte 0000 0000 37,217103h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 29,217


105h WDTCON WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 225,218

106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 48,217

107h CM1CON0 C1ON C1OUT C1OE C1POL C1R C1CH1 C1CH0 0000 -000 88,218

108h CM2CON0 C2ON C2OUT C2OE C2POL C2R C2CH1 C2CH0 0000 -000 89,218

109h CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL T1GSS C2SYNC 0000 --10 91,219



10Ch EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 112,219

10Dh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 112,219

10Eh EEDATH EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 112,219

10Fh EEADRH EEADRH4(2) EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 112,219


Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if themismatch exists.



POR, BORPage

Bank 3


181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 30,218

182h PCL Program Counter s (PC) Least Significant Byte 0000 0000 37,217

183h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 29,217


185h SRCON SR1 SR0 C1SEN C2REN PULSS PULSR FVREN 0000 00-0 93,219

186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 48,218

187h BAUDCTL ABDOVF RCIDL SCKP BRG16 WUE ABDEN 01-0 0-00 162,219

188h ANSEL ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 40,219

189h ANSELH ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 --11 1111 99,219



18Ch EECON1 EEPGD WRERR WREN WR RD x--- x000 113,219

18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 111,219


Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if themismatch exists.



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2.2.2.1 STATUS Register

The STATUS register, shown in Register 2-1, contains:

the arithmetic status of the ALU

the Reset status

the bank select bits for data memory (GPR and

SFR)

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS, will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not affect-

ing any Status bits, see Section 15.0 Instruction SetSummary

Note 1: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction.

REGISTER 2-1: STATUS: STATUS REGISTER

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC(1) C(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown

bit 7 IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h-1FFh)

0 = Bank 0, 1 (00h-FFh)

bit 6-5 RP: Register Bank Select bits (used for direct addressing)

00 = Bank 0 (00h-7Fh)01 = Bank 1 (80h-FFh)

10 = Bank 2 (100h-17Fh)

11 = Bank 3 (180h-1FFh)

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.


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2.2.2.2 OPTION Register

The OPTION register, shown in Register 2-2, is a

readable and writable register, which contains various

control bits to configure:

Timer0/WDT prescaler

External INT interrupt

Timer0 Weak pull-ups on PORTB

Note: To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT by

setting PSA bit of the OPTION register to

1. See Section 6.3 Timer1 Prescaler.

REGISTER 2-2: OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:



bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual PORT latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin

0 = Interrupt on falling edge of INT pin

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (FOSC/4)

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 21 : 41 : 81 : 161 : 321 : 641 : 1281 : 256

1 : 11 : 21 : 41 : 81 : 161 : 321 : 641 : 128

Bit Value Timer0 Rate WDT Rate


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2.2.2.3 INTCON Register

The INTCON register, shown in Register 2-3, is a

readable and writable register, which contains the various

enable and flag bits for TMR0 register overflow, PORTB

change and external INT pin interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE(1) T0IF(2) INTF RBIF

bit 7 bit 0

Legend:



bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts

0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5 T0IE: Timer0 Overflow Interrupt Enable bit

1 = Enables the Timer0 interrupt

0 = Disables the Timer0 interrupt

bit 4 INTE: INT External Interrupt Enable bit

1 = Enables the INT external interrupt

0 = Disables the INT external interrupt

bit 3 RBIE: PORTB Change Interrupt Enable bit(1)1 = Enables the PORTB change interrupt

0 = Disables the PORTB change interrupt

bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2)

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit 1 INTF: INT External Interrupt Flag bit

1 = The INT external interrupt occurred (must be cleared in software)

0 = The INT external interrupt did not occur

bit 0 RBIF: PORTB Change Interrupt Flag bit

1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in

software)

0 = None of the PORTB general purpose I/O pins have changed state

Note 1: IOCB register must also be enabled.

2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before

clearing T0IF bit.


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2.2.2.4 PIE1 Register

The PIE1 register contains the interrupt enable bits, as

shown in Register 2-4.

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:



bit 7 Unimplemented: Read as 0

bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt

0 = Disables the ADC interruptbit 5 RCIE: EUSART Receive Interrupt Enable bit

1 = Enables the EUSART receive interrupt

0 = Disables the EUSART receive interrupt

bit 4 TXIE: EUSART Transmit Interrupt Enable bit

1 = Enables the EUSART transmit interrupt

0 = Disables the EUSART transmit interrupt

bit 3 SSPIE: Master Synchronous Serial Port (MSSP) Interrupt Enable bit

1 = Enables the MSSP interrupt

0 = Disables the MSSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interruptbit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt

0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt

0 = Disables the Timer1 overflow interrupt


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2.2.2.5 PIE2 Register

The PIE2 register contains the interrupt enable bits, as


Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0OSFIE C2IE C1IE EEIE BCLIE ULPWUIE CCP2IE

bit 7 bit 0

Legend:



bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables oscillator fail interrupt

0 = Disables oscillator fail interrupt

bit 6 C2IE: Comparator C2 Interrupt Enable bit1 = Enables Comparator C2 interrupt

0 = Disables Comparator C2 interrupt

bit 5 C1IE: Comparator C1 Interrupt Enable bit

1 = Enables Comparator C1 interrupt

0 = Disables Comparator C1 interrupt

bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit

1 = Enables EEPROM write operation interrupt

0 = Disables EEPROM write operation interrupt

bit 3 BCLIE: Bus Collision Interrupt Enable bit

1 = Enables Bus Collision interrupt

0 = Disables Bus Collision interrupt

bit 2 ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable bit1 = Enables Ultra Low-Power Wake-up interrupt

0 = Disables Ultra Low-Power Wake-up interrupt


bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enables CCP2 interrupt

0 = Disables CCP2 interrupt


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2.2.2.6 PIR1 Register

The PIR1 register contains the interrupt flag bits, as







appropriate interrupt flag bits are clear prior

to enabling an interrupt.

REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:




bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = A/D conversion complete (must be cleared in software)

0 = A/D conversion has not completed or has not been started

bit 5 RCIF: EUSART Receive Interrupt Flag bit

1 = The EUSART receive buffer is full (cleared by reading RCREG)

0 = The EUSART receive buffer is not full

bit 4 TXIF: EUSART Transmit Interrupt Flag bit

1 = The EUSART transmit buffer is empty (cleared by writing to TXREG)

0 = The EUSART transmit buffer is full

bit 3 SSPIF: MasterSynchronous Serial Port (MSSP) Interrupt Flag bit

1 = The MSSP interrupt condition has occurred, and must be cleared in software before returning from the

Interrupt Service Routine. The conditions that will set this bit are:

SPI

A transmission/reception has taken placeI2C Slave/Master

A transmission/reception has taken place

I2C Master

The initiated Start condition was completed by the MSSP module

The initiated Stop condition was completed by the MSSP module

The initiated restart condition was completed by the MSSP module

The initiated Acknowledge condition was completed by the MSSP module

A Start condition occurred while the MSSP module was idle (Multi-master system)

A Stop condition occurred while the MSSP module was idle (Multi-master system)

0 = No MSSP interrupt condition has occurred

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare mode:1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit

1 = A Timer2 to PR2 match occurred (must be cleared in software)

0 = No Timer2 to PR2 match occurred

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = The TMR1 register overflowed (must be cleared in software)

0 = The TMR1 register did not overflow


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2.2.2.7 PIR2 Register

The PIR2 register contains the interrupt flag bits, as







appropriate interrupt flag bits are clear prior

to enabling an interrupt.

REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

OSFIF C2IF C1IF EEIF BCLIF ULPWUIF CCP2IF

bit 7 bit 0

Legend:



bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)

0 = System clock operating

bit 6 C2IF: Comparator C2 Interrupt Flag bit

1 = Comparator output (C2OUT bit) has changed (must be cleared in software)

0 = Comparator output (C2OUT bit) has not changed

bit 5 C1IF: Comparator C1 Interrupt Flag bit

1 = Comparator output (C1OUT bit) has changed (must be cleared in software)

0 = Comparator output (C1OUT bit) has not changed

bit 4 EEIF: EE Write Operation Interrupt Flag bit

1 = Write operation completed (must be cleared in software)

0 = Write operation has not completed or has not startedbit 3 BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision has occurred in the MSSP when configured for I2C Master mode

0 = No bus collision has occurred

bit 2 ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag bit

1 = Wake-up condition has occurred (must be cleared in software)

0 = No Wake-up condition has occurred


bit 0 CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare mode:1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode


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2.2.2.8 PCON Register

The Power Control (PCON) register (see Register 2-8)

contains flag bits to differentiate between a:

Power-on Reset (POR)

Brown-out Reset (BOR)

Watchdog Timer Reset (WDT)

External MCLR Reset

The PCON register also controls the Ultra Low-Power

Wake-up and software enable of the BOR.

REGISTER 2-8: PCON: POWER CONTROL REGISTER

U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x

ULPWUE SBOREN(1) POR BOR

bit 7 bit 0

Legend:



bit 7-6 Unimplemented: Read as 0

bit 5 ULPWUE: Ultra Low-Power Wake-up Enable bit

1 = Ultra Low-Power Wake-up enabled

0 = Ultra Low-Power Wake-up disabled

bit 4 SBOREN: Software BOR Enable bit(1)

1 = BOR enabled

0 = BOR disabled

bit 3-2 Unimplemented: Read as 0

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: BOREN = 01 in the Configuration Word Register 1 for this bit to control the BOR.


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2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 2-7 shows the two

situations for the loading of the PC. The upper examplein Figure 2-7 shows how the PC is loaded on a write to

PCL (PCLATH PCH). The lower example inFigure 2-7 shows how the PC is loaded during a CALL or

GOTO instruction (PCLATH PCH).

FIGURE 2-7: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the ProgramCounter PC bits (PCH) to be replaced by the

contents of the PCLATH register. This allows the entire

contents of the program counter to be changed by

writing the desired upper 5 bits to the PCLATH register.

When the lower 8 bits are written to the PCL register, all

13 bits of the program counter will change to the values

contained in the PCLATH register and those being

written to the PCL register.

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). Care should be

exercised when jumping into a look-up table or

program branch table (computed GOTO) by modifying

the PCL register. Assuming that PCLATH is set to the

table start address, if the table length is greater than255 instructions or if the lower 8 bits of the memory

address rolls over from 0xFF to 0x00 in the middle of

the table, then PCLATH must be incremented for each

address rollover that occurs between the table

beginning and the target location within the table.

For more information refer to Application Note AN556,

Implementing a Table Read (DS00556).

2.3.2 STACK

The PIC16F882/883/884/886/887 devices have an

8-level x 13-bit wide hardware stack (see Figures 2-2

and 2-3). The stack space is not part of either program

or data space and the Stack Pointer is not readable or

writable. The PC is PUSHed onto the stack when a

CALL instruction is executed or an interrupt causes a

branch. The stack is POPed in the event of a RETURN,

RETLW or a RETFIE instruction execution. PCLATH is

not affected by a PUSH or POP operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

2.4 Indirect Addressing, INDF andFSR Registers

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF

register. Any instruction using the INDF register actually

accesses data pointed to by the File Select Register

(FSR). Reading INDF itself indirectly will produce 00h.

Writing to the INDF register indirectly results in a no

operation (although Status bits may be affected). An

effective 9-bit address is obtained by concatenating the

8-bit FSR and the IRP bit of the STATUS register, as

shown in Figure 2-8.

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESSING

PC

12 8 7 0

5PCLATH

PCLATH

Instruction with

ALU Result

GOTO, CALL

OPCODE

8

PC

12 11 10 0

11PCLATH

PCH PCL

8 7

2

PCLATH

PCH PCL

PCL asDestination

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of theCALL, RETURN, RETLW and RETF

PIC16F886 DataSheet

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