OrCAD Sigrity ERC - Graser · Josh Moore – Product Management Director Cadence OrCAD Solutions...

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Josh Moore – Product Management Director Cadence OrCAD Solutions OrCAD Sigrity ERC Graser User Conference Only

Transcript of OrCAD Sigrity ERC - Graser · Josh Moore – Product Management Director Cadence OrCAD Solutions...

Page 1: OrCAD Sigrity ERC - Graser · Josh Moore – Product Management Director Cadence OrCAD Solutions OrCAD Sigrity ERC Graser User Conference Only

Josh Moore – Product Management Director Cadence OrCAD Solutions

OrCAD Sigrity ERC

Graser User Conference Only

Page 2: OrCAD Sigrity ERC - Graser · Josh Moore – Product Management Director Cadence OrCAD Solutions OrCAD Sigrity ERC Graser User Conference Only

2 © 2014 Cadence Design Systems, Inc..

Frequency domain SI, PI and EMC

• Product of choice for power and signal integrity analysis – Integration with full wave 3D EM

solver

• Layout-based frequency-domain SI / PI simulation – Highly accurate modeling of PCB

structures

• Single-ended and mixed-mode results and post-processing

• Unique capability for ensuring accuracy down to DC

• Targeted workflows to streamline setup operations

Cadence Sigrity – Industry-leading SI / PI Solution Graser User Conference Only

Page 3: OrCAD Sigrity ERC - Graser · Josh Moore – Product Management Director Cadence OrCAD Solutions OrCAD Sigrity ERC Graser User Conference Only

3 © 2014 Cadence Design Systems, Inc..

• Simulations and analysis can be done at four levels – Based on considerations of trace / via couplings,

non-ideal PDN, etc.

• Both layout-based and model-based analysis

Different SI / PI / EMI Levels for Different Needs Graser User Conference Only

Page 4: OrCAD Sigrity ERC - Graser · Josh Moore – Product Management Director Cadence OrCAD Solutions OrCAD Sigrity ERC Graser User Conference Only

4 © 2014 Cadence Design Systems, Inc..

• SPEED2000™ is industry’s only layout-based, time-domain SI / PI solution

• Five workflows for SI / PI analysis from level 1 to 3

Layout-based, Time-domain SI / PI Simulation Graser User Conference Only

Page 5: OrCAD Sigrity ERC - Graser · Josh Moore – Product Management Director Cadence OrCAD Solutions OrCAD Sigrity ERC Graser User Conference Only

5 © 2014 Cadence Design Systems, Inc..

Electrical Rules Checks

Geometry- and Simulation-based Layout Checks

Coupling overlay in

layout

Coupling plot

Coupling table

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6 © 2014 Cadence Design Systems, Inc..

SI Barriers for PCB Designers

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7 © 2014 Cadence Design Systems, Inc..

BRD

• Comprehensive SI / PI simulation and analysis relies on experienced, well trained engineers with sophisticated tools

Complex Flow for Simulation and Verification

S Parameter Extraction with

PowerSI

SPICE Netlist

MCM

SPICE Netlist

RLC model Extaction with

XtractIM

LEF/DEF GDS

IO Model Extraction with

XcitePI

SPICE Netlist

Transistors model

IBIS model Conversion with

T2B

IBIS 5.0 model

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Page 8: OrCAD Sigrity ERC - Graser · Josh Moore – Product Management Director Cadence OrCAD Solutions OrCAD Sigrity ERC Graser User Conference Only

8 © 2014 Cadence Design Systems, Inc..

• Reflections (ringing) – Impedance mismatch

• Crosstalk

– Electromagnetic coupling between adjacent signal lines

• Return path discontinuity

– Layer transitions or plane split crosses

Common SI Analysis Needs to be Simple Graser User Conference Only

Page 9: OrCAD Sigrity ERC - Graser · Josh Moore – Product Management Director Cadence OrCAD Solutions OrCAD Sigrity ERC Graser User Conference Only

9 © 2014 Cadence Design Systems, Inc..

• Ideally, designs should be 100% driven and validated by simulation

• Typically, pre-layout simulation results drive design rules

• Only small portion covered by simulation

• PCB DRCs usually contain only dimension information such as length, width, distance, spacing, etc.

• What do constraints / DRCs forget to tell you?

Simulation and Design Rule Check

Designs Simulations Design Rule Check

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Page 10: OrCAD Sigrity ERC - Graser · Josh Moore – Product Management Director Cadence OrCAD Solutions OrCAD Sigrity ERC Graser User Conference Only

10 © 2014 Cadence Design Systems, Inc..

• Simple design rule checks for dimension will not validate electrical characteristics

DRC Correct or Electrically Correct?

5mil

3mil

5mil

6mil

Case 1: Case 2:

Question: 1. Are the DRC results of these 2 structures

the same or different? 2. Do these 2 structures have the same or

different electrical properties? 3. Do these 2 structures have the same

impedance or not?

Same

Different

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11 © 2014 Cadence Design Systems, Inc..

PWR 1 GND

DRC Correct or Electrically Correct?

5 mil

1. Reference change 2. Cross plane split

PWR1

PWR1

1. Layer Transition

TOP Bottom

1. Coplanar reference

• Pre-layout simulation, defines a trace width to be 5 mils for a target impedance – The following routed trace results in no DRC violation

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12 © 2014 Cadence Design Systems, Inc..

DRC Correct or Electrically Correct?

Impedance mismatch 1

Impedance mismatch 2

Impedance mismatch 3

Impedance mismatch 4

Radiation Radiation

PWR 1 GND 5 mil

PWR1

PWR1

TOP Bottom

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13 © 2014 Cadence Design Systems, Inc..

• To minimize crosstalk, many follow the ‘3W’ rule – set the spacing between critical adjacent traces to 3 times the width of the trace – The following routed trace results in no DRC violation

DRC Correct or Electrically Correct?

5mil

5mil

15mil

‘3W’ rule works for the following structure

5mil 5mil 15mil

3.5mil

No DRC violation No Xtalk issue

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14 © 2014 Cadence Design Systems, Inc..

• What if the stack-up looks like the following, will ‘3W’ rule still work?

DRC Correct or Electrically Correct?

5mil 5mil 15mil

3.5mil

35mil

No DRC violation Still no Xtalk issue?

How do you know?

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15 © 2014 Cadence Design Systems, Inc..

• DRCs only validate MINIMUM, PHYSICAL requirements of design constraints

• Do no DRCs mean a good, quality design? • Can PCB designers identify and

address signal quality issues?

DRC Correct or Electrically Correct?

How difficult is it to setup? Is it easy to use?

Do I have to be an SI expert? Is it expensive?

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OrCAD Sigrity Technology for PCB Designers

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17 © 2014 Cadence Design Systems, Inc..

• ERCs are better than DRCs for signal quality validation – Go beyond MINIMUM, GEOMETRY-BASED constraint validation

• Easy to use, minimal setup • PCB designers can identify and address signal quality issues

Electrical Rule Checks with OrCAD Sigrity ERC Graser User Conference Only

Page 18: OrCAD Sigrity ERC - Graser · Josh Moore – Product Management Director Cadence OrCAD Solutions OrCAD Sigrity ERC Graser User Conference Only

18 © 2014 Cadence Design Systems, Inc..

• No complex modeling / setup required • Electrical checks include

– SI Metrics (Level 1 & Level 2) – Differential Pair Serial Link Screening

– Trace impedance check – Trace return path check – Via return path check – Trace coupling check – Net coupling check – Additional future checks

• OrCAD FloorPlanner

– Place and route edits only – Cross-probe (pan / highlight / zoom) between analysis & layout

OrCAD Sigrity ERC (coming 2015 / 17.0 & QIRs) Graser User Conference Only

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Coupling / metrics

Design modification

Trace Impedance / return path

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20 © 2014 Cadence Design Systems, Inc..

0 1 2 3

0 1 2

3

Trace Impedance Check

Visually or tabular results for trace impedance check shows trace segment(s) mismatch vs. target impedance

• This check helps identify – Wrong trace width spacing (e.g. diff. pair)

102Ω 85Ω

Visual plot

Cross probing

– Plane split cross – Trace impedance variances

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21 © 2014 Cadence Design Systems, Inc..

Trace Impedance Check

Cross probing allows issues to be quickly identified

0 1 2 3

0 1 2

3

Cross Probing Graser User Conference Only

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22 © 2014 Cadence Design Systems, Inc..

Tabular Results

• Any trace segment mismatch? Cross plane split? • Too much breakout neck length? • Too much MS/SL routing difference in a group?

• Cross plane split?

• The same trace length means the same trace delay? • Routing on MS/SL has different trace delay.

Trace Impedance Check Graser User Conference Only

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23 © 2014 Cadence Design Systems, Inc..

Cross probing helps to easily resolve issues

Trace Coupling Check Graser User Conference Only

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24 © 2014 Cadence Design Systems, Inc..

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Trace Coupling Check

Tight coupling pairs Max coupling aggressor Dangerous vs. safe coupling ( = 2.81% / 0.156%)

18X

18X

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25 © 2014 Cadence Design Systems, Inc..

Trace Reference Check

Trace cross layer reference shows the net names for the reference plane shapes directly above and below the corresponding trace segment

Trace coplanar reference shows the net names for the reference plane shapes next to the corresponding trace segment on the same layer

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Page 26: OrCAD Sigrity ERC - Graser · Josh Moore – Product Management Director Cadence OrCAD Solutions OrCAD Sigrity ERC Graser User Conference Only

26 © 2014 Cadence Design Systems, Inc..

• ERCs are better than DRCs for signal quality validation – Identify issues geometry-based DRCs miss

• OrCAD Sigrity ERC specifically designed for PCB

designers leveraging industry-leading Cadence Sigrity technology – Easy to use, minimal setup – Cross-probing

• Actionable results to identify and quickly address signal

quality issues

Summary / Benefits Graser User Conference Only

Page 27: OrCAD Sigrity ERC - Graser · Josh Moore – Product Management Director Cadence OrCAD Solutions OrCAD Sigrity ERC Graser User Conference Only

27 © 2014 Cadence Design Systems, Inc..

©2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Sigrity, and OrCAD are registered trademarks and the OrCAD logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

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