Jaya Seminar

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    A HIGH PERFORMANCE VLSI FFT

    ARCHITECTURE

    ByM.Jaya Lakshmi

    10B01D5705

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    Agenda

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    y Signal processing and telecommunication applicationsrequire FFT implementations that can perform

    y large size

    y

    low latency computations whileexhibitinglow powerconsumption

    y computational tasks areexecutedeither by

    y a single, high frequencyembedded processor

    y

    using anApplicationSpecific Integrated Circuit (ASIC).

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    contd

    y Previous FFT architectures

    y Fully unfolded FFT architectures

    y Cascade FFT topologies

    y Higher Radix techniques

    y Advantages of present architecture compared toprevious

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    Analysis of RADIX-43 Algorithm

    The linear index mapping is transforms into a 4D index mapping as follows

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    R4Architecture

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    a.R43 Engine

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    Architecture

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    B. Architecture Performancey

    This architecture realizes a 4096-point FFT, by cascading twosuccessive R43 stages. An additional stage ofR43 would result in a256K-point

    y cascade FFT architectures requires 6- R22 or R4 stages to performa 4K-point FFT or9 stages for a 256K-point FFT

    y improved latency compared to the other casscade architecturesbecause it requires data buffering only between the two R43 stagesinstead of 6 plain R4 stages.

    y unfolded FFT implementations require memory of size 4K62(points, stages, dual bank) to perform a 4K-point FFT, while our

    proposed architecture requires only 1/3 ofthat memory.

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    Advantagesy 20% oflogicareautilization

    y 25 % BlocksRAMutilization

    y Through the use of optimized CoreLib multipliers

    components area reduced to to 13% ofthe total resources

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    Comparison to previous works

    y Some implemented a 2K complex point FFT processorperforms at 76MHz and sustaines throughput of 2Kpoints/26us.

    y Some implemented 1-D and

    2-D FFTs of 10

    24-point FFTat 80 MHz, at a computation time of 68us.

    y Some implemented a 64-point Fourier transform chip,operates at 20 MHz with 3.85 us latency.

    y Comparatively, the architecture of the R43 processorpresented in this work performs a 64 complex point FFToperating at the frequency of 200 MHz with a 0.32uslatency.

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    conclusiony very high operating frequencies and the low latencies

    of both the FPGAand VLSI implementations

    yreduceddata memory

    y improved multiplier utilization

    y occupying a smaller silicon area ,consuming less powercompared to similar solutions

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    Referencesy A. Oppenheim, R. Schafer Digital Signal Processing, Prentice Hall

    1975.

    y Clark D. ThompsonFourier Transform in VLSI, IEEETransactions

    on Computers,1983.y E.H. Wold andA.M. Despain Pipeline and ParallelFFT Processors

    for VLSI Implementations, IEEETransactions on Computers, vol.C-33, 1984.

    y J. Y. OH and M. S. Lim,New Radix-2 to the 4th Power Pipeline FFT

    Processor, IEICETrans.Electron., VOL.E88-C, NO.8,August 2005.

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