Io Controller Hub 9 Datasheet

7/29/2019 Io Controller Hub 9 Datasheet

1/882

Document Number: 316972-004

I nt el I / O Controlle r Hub 9 ( I CH9)Family

Datasheet

For the I nte l

8 2 8 0 1 I B I CH9 , 8 2 8 0 1 I R I CH9 R, 8 2 8 0 1 I H I CH9 DH,8 2 8 0 1 I O I CH9 DO, 8 2 8 0 1 I BM I CH9 M a nd 8 2 8 0 1 I EM I CH9 M-E,and I CH9M-SFF I CH9- I / O Control le r Hubs

August 20 08


2/882

2 Intel I/O Controller Hub 9 (ICH9) Family Datasheet

LegalL ines and Disclaimers

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL

PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OROTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONSOF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATINGTO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended foruse in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these forfuture definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel I/O Controller Hub 9 (ICH9) Family chipset component may contain design defects or errors known as errata which may cause the product todeviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American PhilipsCorporation.

Intel Active Management Technology requires the computer system to have an Intel AMT-enabled chipset, network hardware and software, as well asconnection with a power source and a corporate network connection. Setup requires configuration by the purchaser and may require scripting with themanagement console or further integration into existing security frameworks to enable certain functionality. It may also require modifications ofimplementation of new business processes. With regard to notebooks, Intel AMT may not be available or certain capabilities may be limited over a hostOS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off. For more information, see www.intel.com/technology/platform-technology/intel-amt/

Intel Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and for some uses, certainplatform software enabled for it. Functionality, performance or other benefit will vary depending on hardware and software configurations and mayrequire a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.

Intel, Intel SpeedStep, Intel V iiv, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United Statesand other countries.

*Other names and brands may be claimed as the property of others.

Copyright 20072008, Intel Corporation


3/882

Intel I/O Controller Hub 9 (ICH9) Family Datasheet 3

Contents

1 I ntroduct ion ............................................................................................................ 431.1 About This Document......................................................................................... 43

1.2 Overview ......................................................................................................... 47

1.2.1 Capability Overview................................................................................ 49

1.3 Intel ICH9 Family High-Level Component Differences ........................................... 54

2 Signal Descr ipt ion ................................................................................................... 55

2.1 Direct Media Interface (DMI) to Host Controller ..................................................... 582.2 PCI Express* .................................................................................................... 59

2.3 LAN Connect Interface ....................................................................................... 59

2.4 Gigabit LAN Connect Interface ............................................................................ 60

2.5 Firmware Hub Interface...................................................................................... 61

2.6 PCI Interface .................................................................................................... 62

2.7 Serial ATA Interface........................................................................................... 64

2.8 LPC Interface.................................................................................................... 67

2.9 Interrupt Interface ............................................................................................ 68

2.10 USB Interface ................................................................................................... 69

2.11 Power Management Interface.............................................................................. 71

2.12 Processor Interface............................................................................................ 74

2.13 SMBus Interface................................................................................................ 75

2.14 System Management Interface............................................................................ 762.15 Real Time Clock Interface................................................................................... 78

2.16 Other Clocks..................................................................................................... 78

2.17 Miscellaneous Signals ........................................................................................ 78

2.18 Intel High Definition Audio Link ......................................................................... 80

2.19 Serial Peripheral Interface (SPI) .......................................................................... 81

2.20 Controller Link .................................................................................................. 82

2.21 Intel Quiet System Technology (Desktop Only)................................................... 83

2.22 General Purpose I/O Signals ............................................................................... 832.23 Power and Ground Signals.................................................................................. 86

2.24 Pin Straps ........................................................................................................ 88

2.24.1 Functional Straps ................................................................................... 88

2.24.2 External RTC Circuitry............................................................................. 90

3 I ntel I CH9 Pin States ............................................................................................. 91

3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 91

3.2 Output and I/O Signals Planes and States............................................................. 92

3.3 Power Planes for Input Signals.......................................................................... 101

4 I ntel I CH9 a nd System Clock Dom ains................................................................. 107

5 Funct ional De scr ipt ion ........................................................................................... 109

5.1 DMI-to-PCI Bridge (D30:F0) ............................................................................. 109

5.1.1 PCI Bus Interface ................................................................................. 109

5.1.2 PCI Bridge As an Initiator ...................................................................... 1095.1.2.1 Memory Reads and Writes........................................................ 1105.1.2.2 I/O Reads and Writes .............................................................. 1105.1.2.3 Configuration Reads and Writes ................................................ 1105.1.2.4 Locked Cycles ........................................................................ 1105.1.2.5 Target / Master Aborts............................................................. 1105.1.2.6 Secondary Master Latency Timer............................................... 1105.1.2.7 Dual Address Cycle (DAC) ........................................................ 1105.1.2.8 Memory and I/O Decode to PCI................................................. 111


4/882


5.1.3 Parity Error Detection and Generation......................................................111

5.1.4 PCIRST# .............................................................................................112

5.1.5 Peer Cycles..........................................................................................112

5.1.6 PCI-to-PCI Bridge Model ........................................................................112

5.1.7 IDSEL to Device Number Mapping ...........................................................113

5.1.8 Standard PCI Bus Configuration Mechanism..............................................1135.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) ................................................113

5.2.1 Interrupt Generation .............................................................................113

5.2.2 Power Management...............................................................................114

5.2.2.1 S3/S4/S5 Support ...................................................................1145.2.2.2 Resuming from Suspended State...............................................1145.2.2.3 Device Initiated PM_PME Message ............................................. 1145.2.2.4 SMI/SCI Generation.................................................................115

5.2.3 SERR# Generation................................................................................115

5.2.4 Hot-Plug..............................................................................................1165.2.4.1 Presence Detection..................................................................1165.2.4.2 Message Generation ................................................................1165.2.4.3 Attention Button Detection .......................................................1175.2.4.4 SMI/SCI Generation.................................................................117

5.3 Gigabit Ethernet Controller (B0:D25:F0) .............................................................1175.3.1 Gigabit Ethernet PCI Bus Interface ..........................................................118

5.3.1.1 Transaction Layer....................................................................1185.3.1.2 Data Alignment.......................................................................1185.3.1.3 Configuration Request Retry Status ........................................... 119

5.3.2 Error Events and Error Reporting ............................................................119

5.3.2.1 Data Parity Error .....................................................................1195.3.2.2 Completion with Unsuccessful Completion Status.........................119

5.3.3 Ethernet Interface ................................................................................119

5.3.3.1 MAC/LAN Connect Interface......................................................119

5.3.4 PCI Power Management .........................................................................120

5.3.4.1 Wake-Up................................................................................120

5.3.5 Configurable LEDs.................................................................................121

5.3.6 Function Level Reset Support (FLR).........................................................122

5.3.6.1 FLR Steps...............................................................................1225.4 LPC Bridge (w/ System and Management Functions) (D31:F0) ...............................123

5.4.1 LPC Interface .......................................................................................123

5.4.1.1 LPC Cycle Types......................................................................1245.4.1.2 Start Field Definition................................................................ 1245.4.1.3 Cycle Type / Direction (CYCTYPE + DIR).....................................1255.4.1.4 Size.......................................................................................1255.4.1.5 SYNC.....................................................................................1265.4.1.6 SYNC Time-Out.......................................................................1265.4.1.7 SYNC Error Indication ..............................................................1265.4.1.8 LFRAME# Usage......................................................................1275.4.1.9 I/O Cycles ..............................................................................1275.4.1.10 Bus Master Cycles ...................................................................1275.4.1.11 LPC Power Management ...........................................................1275.4.1.12 Configuration and Intel ICH9 Implications................................. 128

5.5 DMA Operation (D31:F0) ..................................................................................1285.5.1 Channel Priority....................................................................................129

5.5.1.1 Fixed Priority ..........................................................................1295.5.1.2 Rotating Priority......................................................................129

5.5.2 Address Compatibility Mode ...................................................................129

5.5.3 Summary of DMA Transfer Sizes.............................................................130

5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words130

5.5.4 Autoinitialize ........................................................................................130

5.5.5 Software Commands.............................................................................131


5/882


5.6 LPC DMA........................................................................................................ 131

5.6.1 Asserting DMA Requests........................................................................ 131

5.6.2 Abandoning DMA Requests .................................................................... 132

5.6.3 General Flow of DMA Transfers............................................................... 132

5.6.4 Terminal Count .................................................................................... 133

5.6.5 Verify Mode ......................................................................................... 1335.6.6 DMA Request Deassertion...................................................................... 133

5.6.7 SYNC Field / LDRQ# Rules..................................................................... 134

5.7 8254 Timers (D31:F0) ..................................................................................... 135

5.7.1 Timer Programming.............................................................................. 135

5.7.2 Reading from the Interval Timer............................................................. 136

5.7.2.1 Simple Read........................................................................... 1365.7.2.2 Counter Latch Command.......................................................... 1375.7.2.3 Read Back Command .............................................................. 137

5.8 8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 138

5.8.1 Interrupt Handling................................................................................ 139

5.8.1.1 Generating Interrupts.............................................................. 1395.8.1.2 Acknowledging Interrupts ........................................................ 1395.8.1.3 Hardware/Software Interrupt Sequence ..................................... 140

5.8.2 Initialization Command Words (ICWx)..................................................... 1405.8.2.1 ICW1 .................................................................................... 1405.8.2.2 ICW2 .................................................................................... 1415.8.2.3 ICW3 .................................................................................... 1415.8.2.4 ICW4 .................................................................................... 141

5.8.3 Operation Command Words (OCW)......................................................... 141

5.8.4 Modes of Operation .............................................................................. 141

5.8.4.1 Fully Nested Mode................................................................... 1415.8.4.2 Special Fully-Nested Mode........................................................ 1425.8.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 1425.8.4.4 Specific Rotation Mode (Specific Priority).................................... 1425.8.4.5 Poll Mode............................................................................... 1425.8.4.6 Cascade Mode ........................................................................ 1435.8.4.7 Edge and Level Triggered Mode ................................................ 1435.8.4.8 End of Interrupt (EOI) Operations ............................................. 143

5.8.4.9 Normal End of Interrupt........................................................... 1435.8.4.10 Automatic End of Interrupt Mode .............................................. 143

5.8.5 Masking Interrupts ............................................................................... 144

5.8.5.1 Masking on an Individual Interrupt Request................................ 1445.8.5.2 Special Mask Mode.................................................................. 144

5.8.6 Steering PCI Interrupts ......................................................................... 144

5.9 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 145

5.9.1 Interrupt Handling................................................................................ 145

5.9.2 Interrupt Mapping ................................................................................ 145

5.9.3 PCI / PCI Express* Message-Based Interrupts.......................................... 146

5.9.4 Front Side Bus Interrupt Delivery ........................................................... 146

5.9.4.1 Edge-Triggered Operation ........................................................ 1475.9.4.2 Level-Triggered Operation........................................................ 1475.9.4.3 Registers Associated with Front Side Bus Interrupt Delivery.......... 147

5.9.4.4 Interrupt Message Format........................................................ 1475.9.5 IOxAPIC Address Remapping ................................................................. 148

5.9.6 External Interrupt Controller Support ...................................................... 148

5.10 Serial Interrupt (D31:F0) ................................................................................. 149

5.10.1 Start Frame......................................................................................... 1495.10.2 Data Frames........................................................................................ 150

5.10.3 Stop Frame ......................................................................................... 150

5.10.4 Specific Interrupts Not Supported via SERIRQ.......................................... 150


6/882


5.10.5 Data Frame Format...............................................................................151

5.11 Real Time Clock (D31:F0) .................................................................................152

5.11.1 Update Cycles ......................................................................................152

5.11.2 Interrupts............................................................................................153

5.11.3 Lockable RAM Ranges............................................................................153

5.11.4 Century Rollover...................................................................................1535.11.5 Clearing Battery-Backed RTC RAM...........................................................153

5.12 Processor Interface (D31:F0) ............................................................................155

5.12.1 Processor Interface Signals ....................................................................155

5.12.1.1 A20M# (Mask A20)..................................................................1555.12.1.2 INIT# (Initialization)................................................................1565.12.1.3 FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore

Numeric Error)........................................................................ 1565.12.1.4 NMI (Non-Maskable Interrupt) ..................................................1575.12.1.5 Stop Clock Request (STPCLK#) .................................................1575.12.1.6 CPU Power Good (CPUPWRGD)..................................................1575.12.1.7 Deeper Sleep (DPSLP#) (Mobile Only)........................................157

5.12.2 Dual-Processor Issues (Desktop Only) .....................................................158

5.12.2.1 Signal Differences ...................................................................158

5.12.2.2 Power Management .................................................................1585.13 Power Management (D31:F0)............................................................................159

5.13.1 Features..............................................................................................159

5.13.2 Intel ICH9 and System Power States ..................................................... 159

5.13.3 System Power Planes ............................................................................162

5.13.4 SMI#/SCI Generation............................................................................162

5.13.4.1 PCI Express* SCI ....................................................................1655.13.4.2 PCI Express* Hot-Plug .............................................................165

5.13.5 Dynamic Processor Clock Control ............................................................165

5.13.5.1 Slow C4 and C5 Exit (Mobile Only).............................................1665.13.5.2 Transition Rules among S0/Cx and Throttling States ....................1675.13.5.3 Deferred C3/C4 (Mobile Only) ...................................................1675.13.5.4 POPUP (Auto C3/C4 to C2) (Mobile Only)....................................1675.13.5.5 POPDOWN (Auto C2 to C3/C4) (Mobile Only)...............................1685.13.5.6 C5 and C6 Entry/Exit (Mobile Only)............................................168

5.13.5.7 C5 Exit (Mobile Only) ...............................................................1685.13.6 Dynamic PCI Clock Control (Mobile Only) .................................................168

5.13.6.1 Conditions for Checking the PCI Clock ........................................1695.13.6.2 Conditions for Maintaining the PCI Clock.....................................1695.13.6.3 Conditions for Stopping the PCI Clock ........................................1695.13.6.4 Conditions for Re-Starting the PCI Clock.....................................1695.13.6.5 LPC Devices and CLKRUN#.......................................................169

5.13.7 Sleep States ........................................................................................170

5.13.7.1 Sleep State Overview...............................................................1705.13.7.2 Initiating Sleep State ...............................................................1705.13.7.3 Exiting Sleep States.................................................................1705.13.7.4 PCI Express* WAKE# Signal and PME Event Message...................1725.13.7.5 Sx-G3-Sx, Handling Power Failures............................................172

5.13.8 Thermal Management............................................................................1735.13.8.1 THRM# Signal.........................................................................1735.13.8.2 Software Initiated Passive Cooling .............................................1735.13.8.3 THRM# Override Software Bit ...................................................1745.13.8.4 Active Cooling.........................................................................174

5.13.9 Event Input Signals and Their Usage .......................................................174

5.13.9.1 PWRBTN# (Power Button) ........................................................1745.13.9.2 RI# (Ring Indicator) ................................................................1755.13.9.3 PME# (PCI Power Management Event) .......................................1765.13.9.4 SYS_RESET# Signal ................................................................176


7/882


5.13.9.5 THRMTRIP# Signal.................................................................. 176

5.13.10ALT Access Mode.................................................................................. 177

5.13.10.1Write Only Registers with Read Paths in ALT Access Mode ............ 1785.13.10.2PIC Reserved Bits ................................................................... 1805.13.10.3Read Only Registers with Write Paths in ALT Access Mode ............ 180

5.13.11System Power Supplies, Planes, and Signals ............................................ 1815.13.11.1Power Plane Control with SLP_S3#, SLP_S4#, SLP_S5#

and SLP_M# .......................................................................... 1815.13.11.2SLP_S4# and Suspend-To-RAM Sequencing ............................... 1815.13.11.3PWROK Signal ........................................................................ 1825.13.11.4CPUPWRGD Signal .................................................................. 1825.13.11.5VRMPWRGD Signal.................................................................. 1825.13.11.6BATLOW# (Battery Low) (Mobile Only) ...................................... 182

5.13.12Clock Generators.................................................................................. 183

5.13.12.1Clock Control Signals from Intel ICH9 to ClockSynthesizer (Mobile Only) ........................................................ 183

5.13.13Legacy Power Management Theory of Operation ....................................... 184

5.13.13.1APM Power Management (Desktop Only) .................................... 1845.13.13.2Mobile APM Power Management (Mobile Only) ............................ 184

5.13.14Reset Behavior..................................................................................... 184

5.14 System Management (D31:F0).......................................................................... 186

5.14.1 Theory of Operation.............................................................................. 186

5.14.1.1 Detecting a System Lockup ...................................................... 1865.14.1.2 Handling an Intruder ............................................................... 1865.14.1.3 Detecting Improper Firmware Hub Programming ......................... 1875.14.1.4 Heartbeat and Event Reporting via SMLink/SMBus....................... 187

5.14.2 TCO Modes.......................................................................................... 187

5.14.2.1 TCO Legacy/Compatible Mode .................................................. 1875.14.2.2 Advanced TCO Mode ............................................................... 189

5.15 General Purpose I/O (D31:F0) .......................................................................... 190

5.15.1 Power Wells......................................................................................... 190

5.15.2 SMI# and SCI Routing .......................................................................... 190

5.15.3 Triggering ........................................................................................... 191

5.15.4 Serial POST Codes Over GPIO ................................................................ 191

5.15.4.1 Theory of operation................................................................. 1915.15.4.2 Serial Message Format ............................................................ 192

5.15.5 Controller Link GPIOs (Digital Office Only) ............................................... 193

5.16 SATA Host Controller (D31:F2, F5) .................................................................... 193

5.16.1 SATA Feature Support........................................................................... 1945.16.2 Theory of Operation.............................................................................. 195

5.16.2.1 Standard ATA Emulation .......................................................... 1955.16.2.2 48-Bit LBA Operation............................................................... 195

5.16.3 SATA Swap Bay Support ....................................................................... 195

5.16.4 Hot Plug Operation ............................................................................... 1955.16.4.1 Low Power Device Presence Detection ....................................... 195

5.16.5 Function Level Reset Support (FLR) ........................................................ 196

5.16.5.1 FLR Steps .............................................................................. 196

5.16.6 Intel Matrix Storage Technology Configuration (Intel ICH9R, ICH9DH,

ICH9DO, ICH9M and ICH9M-E Only) ....................................................... 1975.16.6.1 Intel Matrix Storage Manager RAID Option ROM........................ 197

5.16.7 Power Management Operation................................................................ 198

5.16.7.1 Power State Mappings ............................................................. 1985.16.7.2 Power State Transitions ........................................................... 1995.16.7.3 SMI Trapping (APM) ................................................................ 200

5.16.8 SATA Device Presence........................................................................... 200

5.16.9 SATA LED............................................................................................ 200


8/882


5.16.10AHCI Operation .................................................................................... 201

5.16.11Serial ATA Reference Clock Low Power Request (SATACLKREQ#) ................201

5.16.12SGPIO Signals ...................................................................................... 201

5.16.12.1Mechanism ............................................................................. 2025.16.12.2Message Format...................................................................... 202

5.16.12.3LED Message Type ..................................................................2035.16.12.4SGPIO Waveform .................................................................... 205

5.16.13External SATA ...................................................................................... 206

5.17 High Precision Event Timers ..............................................................................206

5.17.1 Timer Accuracy ....................................................................................206

5.17.2 Interrupt Mapping.................................................................................206

5.17.3 Periodic vs. Non-Periodic Modes..............................................................207

5.17.4 Enabling the Timers ..............................................................................208

5.17.5 Interrupt Levels....................................................................................208

5.17.6 Handling Interrupts...............................................................................2085.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors ..............................209

5.18 USB UHCI Host Controllers (D29:F0, F1, F2, F3 and D26:F0, F1 and F2) .................209

5.18.1 Data Structures in Main Memory.............................................................209

5.18.2 Data Transfers to/from Main Memory ......................................................209

5.18.3 Data Encoding and Bit Stuffing ...............................................................2105.18.4 Bus Protocol......................................................................................... 210

5.18.4.1 Bit Ordering............................................................................ 2105.18.4.2 SYNC Field .............................................................................2105.18.4.3 Packet Field Formats................................................................2105.18.4.4 Address Fields......................................................................... 2105.18.4.5 Frame Number Field ................................................................2105.18.4.6 Data Field ..............................................................................2105.18.4.7 Cyclic Redundancy Check (CRC) ................................................210

5.18.5 Packet Formats ....................................................................................210

5.18.6 USB Interrupts ..................................................................................... 211

5.18.6.1 Transaction-Based Interrupts....................................................2115.18.6.2 Non-Transaction Based Interrupts .............................................213

5.18.7 USB Power Management........................................................................213

5.18.8 USB Legacy Keyboard Operation.............................................................2145.18.9 Function Level Reset Support (FLR).........................................................216

5.18.9.1 FLR Steps...............................................................................216

5.19 USB EHCI Host Controllers (D29:F7 and D26:F7) .................................................217

5.19.1 EHC Initialization ..................................................................................217

5.19.1.1 BIOS Initialization ...................................................................2175.19.1.2 Driver Initialization..................................................................2175.19.1.3 EHC Resets ............................................................................218

5.19.2 Data Structures in Main Memory.............................................................2185.19.3 USB 2.0 Enhanced Host Controller DMA ...................................................218

5.19.4 Data Encoding and Bit Stuffing ...............................................................218

5.19.5 Packet Formats ....................................................................................219

5.19.6 USB 2.0 Interrupts and Error Conditions ..................................................219

5.19.6.1 Aborts on USB 2.0-Initiated Memory Reads.................................219

5.19.7 USB 2.0 Power Management ..................................................................220

5.19.7.1 Pause Feature.........................................................................2205.19.7.2 Suspend Feature.....................................................................2205.19.7.3 ACPI Device States..................................................................2205.19.7.4 ACPI System States.................................................................2215.19.7.5 Mobile Considerations ..............................................................221

5.19.8 Interaction with UHCI Host Controllers.....................................................221

5.19.8.1 Port-Routing Logic...................................................................2225.19.8.2 Device Connects .....................................................................223


9/882


5.19.8.3 Device Disconnects ................................................................. 2245.19.8.4 Effect of Resets on Port-Routing Logic........................................ 224

5.19.9 USB 2.0 Legacy Keyboard Operation ....................................................... 224

5.19.10USB 2.0 Based Debug Port .................................................................... 225

5.19.10.1 Theory of Operation ............................................................... 225

5.19.11USB Pre-Fetch Based Pause ................................................................... 2295.19.12Function Level Reset Support (FLR) ........................................................ 230

5.19.12.1FLR Steps .............................................................................. 230

5.20 SMBus Controller (D31:F3) ............................................................................... 230

5.20.1 Host Controller..................................................................................... 231

5.20.1.1 Command Protocols ................................................................ 231

5.20.2 Bus Arbitration..................................................................................... 235

5.20.3 Bus Timing.......................................................................................... 235

5.20.3.1 Clock Stretching ..................................................................... 2355.20.3.2 Bus Time Out (Intel ICH9 as SMBus Master)............................. 235

5.20.4 Interrupts / SMI#................................................................................. 236

5.20.5 SMBALERT# ........................................................................................ 237

5.20.6 SMBus CRC Generation and Checking...................................................... 237

5.20.7 SMBus Slave Interface .......................................................................... 237

5.20.7.1 Format of Slave Write Cycle ..................................................... 2385.20.7.2 Format of Read Command........................................................ 2405.20.7.3 Slave Read of RTC Time Bytes .................................................. 2425.20.7.4 Format of Host Notify Command ............................................... 243

5.21 Intel High Definition Audio Overview................................................................ 244

5.21.1 Intel High Definition Audio Docking (Mobile Only) ................................... 244

5.21.1.1 Dock Sequence....................................................................... 2445.21.1.2 Exiting D3/CRST# when Docked ............................................... 2455.21.1.3 Cold Boot/Resume from S3 When Docked .................................. 2465.21.1.4 Undock Sequence ................................................................... 2465.21.1.5 Interaction Between Dock/Undock and Power Management States. 2475.21.1.6 Relationship between HDA_DOCK_RST# and HDA_RST# ............. 247

5.21.2 Function Level Reset Support (FLR) ........................................................ 248

5.21.2.1 FLR Steps .............................................................................. 248

5.22 Intel

Active Management Technology (Intel

AMT) (Digital Office Only)................ 2485.22.1 Intel AMT Features ............................................................................. 249

5.22.2 Intel AMT Requirements ...................................................................... 249

5.23 Serial Peripheral Interface (SPI) ........................................................................ 249

5.23.1 SPI Supported Feature Overview ............................................................ 249

5.23.1.1 Non-Descriptor Mode............................................................... 2505.23.1.2 Descriptor Mode ..................................................................... 2505.23.1.3 Device Partitioning.................................................................. 251

5.23.2 Flash Descriptor ................................................................................... 251

5.23.2.1 Descriptor Master Region ......................................................... 253

5.23.3 Flash Access ........................................................................................ 254

5.23.3.1 Direct Access Security ............................................................. 2545.23.3.2 Register Access Security.......................................................... 254

5.23.4 Serial Flash Device Compatibility Requirements ........................................ 254

5.23.4.1 Intel ICH9 SPI Based BIOS Requirements ................................ 2555.23.4.2 Integrated LAN Firmware SPI Flash Requirements ....................... 2555.23.4.3 Intel Management Engine Firmware SPI Flash Requirements....... 2555.23.4.4 Hardware Sequencing Requirements.......................................... 256

5.23.5 Multiple Page Write Usage Model ............................................................ 257

5.23.5.1 Soft Flash Protection ............................................................... 2575.23.5.2 BIOS Range Write Protection .................................................... 2575.23.5.3 SMI# Based Global Write Protection .......................................... 258

5.23.6 Flash Device Configurations ................................................................... 258


10/882


5.23.7 SPI Flash Device Recommended Pinout....................................................258

5.23.8 Serial Flash Device Package ...................................................................259

5.23.8.1 Common Footprint Usage Model ................................................2595.23.8.2 Serial Flash Device Package Recommendations ...........................259

5.24 Intel Quiet System Technology (Intel QST) (Desktop Only) ...............................260

5.24.1 PWM Outputs .......................................................................................2605.24.2 TACH Inputs ........................................................................................260

5.25 Thermal Sensors..............................................................................................260

5.26 Feature Capability Mechanism ...........................................................................261

5.27 Integrated Trusted Platform Module (Mobile Only)................................................261

5.27.1 Integrated TPM Hardware Requirements ..................................................261

5.27.2 Enabling integrated TPM ........................................................................261

6 Ballout Definit ion ................................................................................................... 263

6.1 Intel ICH9 Ballout (Desktop Only) .................................................................... 263

6.2 Intel 82801IBM ICH9M and 82801IEM ICH9M-E Ballout (Mobile Only)................... 272

6.3 Intel ICH9M-SFF Ballout (Mobile Only).............................................................. 281

7 Package I n form at ion ............................................................................................. 289

7.1 Intel ICH9 Package (Desktop Only) .................................................................. 289

7.2 Intel ICH9 Mobile Package (Mobile Only)........................................................... 291

7.2.1 Intel 82801IBM ICH9M and 82801IEM ICH9M-E Package..........................291

7.2.2 Intel ICH9M-SSF Package .................................................................... 293

8 Ele ct rica l Cha ra ct erist ics ........................................................................................295

8.1 Thermal Specifications......................................................................................295

8.2 Absolute Maximum Ratings ...............................................................................295

8.3 DC Characteristics ...........................................................................................295

8.4 AC Characteristics............................................................................................308

8.5 Timing Diagrams .............................................................................................321

9 Regist er and M em or y Mapping ............................................................................... 333

9.1 PCI Devices and Functions ................................................................................334

9.2 PCI Configuration Map......................................................................................335

9.3 I/O Map..........................................................................................................3359.3.1 Fixed I/O Address Ranges......................................................................335

9.3.2 Variable I/O Decode Ranges...................................................................338

9.4 Memory Map ...................................................................................................339

9.4.1 Boot-Block Update Scheme ....................................................................340

10 Ch ip se t Con f ig ur a t io n Reg iste r s .............................................................................343

10.1 Chipset Configuration Registers (Memory Space) .................................................343

10.1.1 VCHVirtual Channel Capability Header Register ......................................346

10.1.2 VCAP1Virtual Channel Capability #1 Register .........................................346

10.1.3 VCAP2Virtual Channel Capability #2 Register .........................................347

10.1.4 PVCPort Virtual Channel Control Register...............................................347

10.1.5 PVSPort Virtual Channel Status Register................................................347

10.1.6 V0CAPVirtual Channel 0 Resource Capability Register..............................348

10.1.7 V0CTLVirtual Channel 0 Resource Control Register .................................349

10.1.8 V0STSVirtual Channel 0 Resource Status Register ..................................34910.1.9 V1CAPVirtual Channel 1 Resource Capability Register..............................350

10.1.10V1CTLVirtual Channel 1 Resource Control Register .................................350

10.1.11V1STSVirtual Channel 1 Resource Status Register .................................. 35110.1.12PATPort Arbitration Table ....................................................................351

10.1.13CIR1Chipset Initialization Register 1 ..................................................... 352

10.1.14RECRoot Error Command Register ........................................................ 352

10.1.15RCTCLRoot Complex Topology Capabilities List Register ..........................352


11/882


10.1.16ESDElement Self Description Register................................................... 353

10.1.17ULDUpstream Link Descriptor Register ................................................. 353

10.1.18ULBAUpstream Link Base Address Register ........................................... 353

10.1.19RP1DRoot Port 1 Descriptor Register .................................................... 354

10.1.20RP1BARoot Port 1 Base Address Register .............................................. 354

10.1.21RP2DRoot Port 2 Descriptor Register .................................................... 35410.1.22RP2BARoot Port 2 Base Address Register .............................................. 355





10.1.27HDDIntel High Definition Audio Descriptor Register .............................. 356

10.1.28HDBAIntel High Definition Audio Base Address Register ........................ 357





10.1.33ILCLInternal Link Capabilities List Register ............................................ 35810.1.34LCAPLink Capabilities Register............................................................. 359

10.1.35LCTLLink Control Register................................................................... 359

10.1.36LSTSLink Status Register .................................................................... 359

10.1.37CIR2 Chipset Initialization Register 2................................................... 360

10.1.38CIR3 Chipset Initialization Register 3................................................... 360

10.1.39BCR Backbone Configuration Register.................................................. 360

10.1.40RPCRoot Port Configuration Register .................................................... 361

10.1.41DMICDMI Control Register .................................................................. 362

10.1.42RPFNRoot Port Function Number and Hide for PCI Express* Root Ports ..... 362

10.1.43FLRSTATFLR Pending Status Register ................................................... 363

10.1.44CIR13Chipset Initialization Register 13 ................................................. 364

10.1.45CIR5Chipset Initialization Register 5..................................................... 36410.1.46TRSRTrap Status Register ................................................................... 364

10.1.47TRCRTrapped Cycle Register ............................................................... 365

10.1.48TWDRTrapped Write Data Register ....................................................... 365

10.1.49IOTRn I/O Trap Register (0-3)............................................................ 366

10.1.50DMCDMI Miscellaneous Control Register ............................................... 367

10.1.51CIR6Chipset Initialization Register 6..................................................... 367

10.1.52CIR7Chipset Initialization Register 7..................................................... 368

10.1.53CIR11Chipset Initialization Register 11 (Mobile Only).............................. 368

10.1.54CIR12Chipset Initialization Register 12 (Mobile Only).............................. 368

10.1.55TCTLTCO Configuration Register .......................................................... 369

10.1.56D31IPDevice 31 Interrupt Pin Register.................................................. 369






10.1.62D25IPDevice 25 Interrupt Pin Register.................................................. 37510.1.63D31IRDevice 31 Interrupt Route Register ............................................. 37510.1.64D30IRDevice 30 Interrupt Route Register ............................................. 376

10.1.65D29IRDevice 29 Interrupt Route Register ............................................. 377





10.1.70OICOther Interrupt Control Register..................................................... 382


12/882


10.1.71SBEMC3Scheduled Break Event C3 Exit Latency (Mobile Only)..................382

10.1.72SBEMC4Scheduled Break Event C4 Exit Latency (Mobile Only)..................383

10.1.73RCRTC Configuration Register .............................................................. 383

10.1.74HPTCHigh Precision Timer Configuration Register ...................................384

10.1.75GCSGeneral Control and Status Register ............................................... 385

10.1.76BUCBacked Up Control Register ........................................................... 38710.1.77FDFunction Disable Register ................................................................388

10.1.78CGClock Gating.................................................................................. 390

10.1.79FDSWFunction Disable SUS Well ..........................................................392



10.1.82PPO - Port Power Off ............................................................................. 392

10.1.83CIR10 - Chipset Initialization Register 10 .................................................393

10.1.84MAP - Remap Control Register ................................................................ 393

1 1 PCI - t o- PCI B r id ge Re gi st e rs ( D 3 0 :F0 ) .................................................................... 395

11.1 PCI Configuration Registers (D30:F0) .................................................................395

11.1.1 VID Vendor Identification Register (PCI-PCID30:F0)............................. 396

11.1.2 DID Device Identification Register (PCI-PCID30:F0).............................396

11.1.3 PCICMDPCI Command (PCI-PCID30:F0) .............................................39711.1.4 PSTSPCI Status Register (PCI-PCID30:F0)..........................................397

11.1.5 RIDRevision Identification Register (PCI-PCID30:F0)............................399

11.1.6 CCClass Code Register (PCI-PCID30:F0).............................................399

11.1.7 PMLTPrimary Master Latency Timer Register (PCI-PCID30:F0) ...............400

11.1.8 HEADTYPHeader Type Register (PCI-PCID30:F0) ................................. 400

11.1.9 BNUMBus Number Register (PCI-PCID30:F0) ......................................400

11.1.10SMLTSecondary Master Latency Timer Register (PCI-PCID30:F0)...........401

11.1.11IOBASE_LIMITI/O Base and Limit Register (PCI-PCID30:F0) .................401

11.1.12SECSTSSecondary Status Register (PCI-PCID30:F0) ............................402

11.1.13MEMBASE_LIMITMemory Base and Limit Register(PCI-PCID30:F0)................................................................................403

11.1.14PREF_MEM_BASE_LIMITPrefetchable Memory Baseand Limit Register (PCI-PCID30:F0) .....................................................403

11.1.15PMBU32Prefetchable Memory Base Upper 32 BitsRegister (PCI-PCID30:F0) ................................................................... 404

11.1.16PMLU32Prefetchable Memory Limit Upper 32 BitsRegister (PCI-PCID30:F0) ................................................................... 404

11.1.17CAPPCapability List Pointer Register (PCI-PCID30:F0) ..........................404

11.1.18INTRInterrupt Information Register (PCI-PCID30:F0) ........................... 40411.1.19BCTRLBridge Control Register (PCI-PCID30:F0) ................................... 405

11.1.20SPDHSecondary PCI Device Hiding Register (PCI-PCID30:F0)................ 406

11.1.21DTCDelayed Transaction Control Register (PCI-PCID30:F0)...................407

11.1.22BPSBridge Proprietary Status Register (PCI-PCID30:F0) .......................408

11.1.23BPCBridge Policy Configuration Register (PCI-PCID30:F0) ..................... 409

11.1.24SVCAPSubsystem Vendor Capability Register (PCI-PCID30:F0) .............. 410

11.1.25SVIDSubsystem Vendor IDs Register (PCI-PCID30:F0) ......................... 410

12 Gigab it LAN Co nf ig ur a tion Reg iste rs ...................................................................... 411

12.1 Gigabit LAN Configuration Registers (Gigabit LAN D25:F0).................................411

12.1.1 VIDVendor Identification Register(Gigabit LAND25:F0) .......................................................................... 412

12.1.2 DIDDevice Identification Register(Gigabit LAND25:F0) .......................................................................... 412

12.1.3 PCICMDPCI Command Register(Gigabit LAND25:F0) .......................................................................... 413


13/882


12.1.4 PCISTSPCI Status Register(Gigabit LAND25:F0).......................................................................... 414

12.1.5 RIDRevision Identification Register(Gigabit LAND25:F0).......................................................................... 415

12.1.6 CCClass Code Register

(Gigabit LAND25:F0).......................................................................... 41512.1.7 CLSCache Line Size Register

(Gigabit LAND25:F0).......................................................................... 415

12.1.8 PLTPrimary Latency Timer Register(Gigabit LAND25:F0).......................................................................... 415

12.1.9 HTHeader Type Register(Gigabit LAND25:F0).......................................................................... 415

12.1.10MBARAMemory Base Address Register A(Gigabit LAND25:F0).......................................................................... 416

12.1.11MBARBMemory Base Address Register B(Gigabit LAND25:F0).......................................................................... 416

12.1.12MBARCMemory Base Address Register C(Gigabit LAND25:F0).......................................................................... 417

12.1.13SVIDSubsystem Vendor ID Register(Gigabit LAND25:F0).......................................................................... 417

12.1.14SIDSubsystem ID Register(Gigabit LAND25:F0).......................................................................... 417

12.1.15ERBAExpansion ROM Base Address Register(Gigabit LAND25:F0).......................................................................... 417

12.1.16CAPPCapabilities List Pointer Register(Gigabit LAND25:F0).......................................................................... 418

12.1.17INTRInterrupt Information Register(Gigabit LAND25:F0).......................................................................... 418

12.1.18MLMGMaximum Latency/Minimum Grant Register(Gigabit LAND25:F0).......................................................................... 418

12.1.19CLIST 1Capabilities List Register 1(Gigabit LAND25:F0).......................................................................... 418

12.1.20PMCPCI Power Management Capabilities Register(Gigabit LAND25:F0).......................................................................... 419

12.1.21PMCSPCI Power Management Control and StatusRegister (Gigabit LAND25:F0) ............................................................. 420

12.1.22DRData Register(Gigabit LAND25:F0).......................................................................... 421

12.1.23CLIST 2Capabilities List Register 2(Gigabit LAND25:F0).......................................................................... 421

12.1.24MCTLMessage Control Register(Gigabit LAND25:F0).......................................................................... 421

12.1.25MADDLMessage Address Low Register(Gigabit LAND25:F0).......................................................................... 422

12.1.26MADDHMessage Address High Register(Gigabit LAND25:F0).......................................................................... 422

12.1.27MDATMessage Data Register(Gigabit LAND25:F0).......................................................................... 422

12.1.28FLRCAPFunction Level Reset Capability(Gigabit LAND25:F0).......................................................................... 422

12.1.29FLRCLVFunction Level Reset Capability Length and Version(Gigabit LAND25:F0).......................................................................... 423

12.1.30DEVCTRLDevice Control (Gigabit LAND25:F0) ..................................... 423

12.2 MBARAGigabit LAN Base Address A Registers ................................................... 424

12.2.1 LDR4LAN Device Initialization Register 4(Gigabit LAN Memory Mapped Base Address Register) ............................... 424


14/882


12.2.2 LDR3LAN Device Initialization Register 3(Gigabit LAN Memory Mapped Base Address Register) ...............................424

12.2.3 LDCR2LAN Device Control Register 2(Gigabit LAN Memory Mapped Base Address Register) ...............................425

12.2.4 LDCR4LAN Device Control Register 4

(Gigabit LAN Memory Mapped Base Address Register) ...............................42512.2.5 LDR5LAN Device Control Register 5

(Gigabit LAN Memory Mapped Base Address Register) ...............................425

12.2.6 LDR2LAN Device Initialization Register 1(Gigabit LAN Memory Mapped Base Address Register) ...............................425

13 LPC I n ter face Br id ge Reg iste r s (D31 :F0 ) ............................................................... 427

13.1 PCI Configuration Registers (LPC I/FD31:F0) ....................................................42713.1.1 VIDVendor Identification Register (LPC I/FD31:F0) ..............................428

13.1.2 DIDDevice Identification Register (LPC I/FD31:F0)...............................428

13.1.3 PCICMDPCI COMMAND Register (LPC I/FD31:F0).................................429

13.1.4 PCISTSPCI Status Register (LPC I/FD31:F0)........................................430

13.1.5 RIDRevision Identification Register (LPC I/FD31:F0) ............................431

13.1.6 PIProgramming Interface Register (LPC I/FD31:F0) .............................43113.1.7 SCCSub Class Code Register (LPC I/FD31:F0) .....................................431

13.1.8 BCCBase Class Code Register (LPC I/FD31:F0)....................................431

13.1.9 PLTPrimary Latency Timer Register (LPC I/FD31:F0) ............................431

13.1.10HEADTYPHeader Type Register (LPC I/FD31:F0) .................................. 432

13.1.11SSSub System Identifiers Register (LPC I/FD31:F0) .............................432

13.1.12CAPPCapability List Pointer (LPC I/FD31:F0) .......................................432

13.1.13PMBASEACPI Base Address Register (LPC I/FD31:F0) ........................... 432

13.1.14ACPI_CNTLACPI Control Register (LPC I/F D31:F0) .............................433

13.1.15GPIOBASEGPIO Base Address Register (LPC I/F D31:F0) .....................434

13.1.16GCGPIO Control Register (LPC I/F D31:F0) ........................................435

13.1.17PIRQ[n]_ROUTPIRQ[A,B,C,D] Routing Control Register(LPC I/FD31:F0) ................................................................................ 436

13.1.18SIRQ_CNTLSerial IRQ Control Register(LPC I/FD31:F0) ................................................................................ 437

13.1.19PIRQ[n]_ROUTPIRQ[E,F,G,H] Routing Control Register(LPC I/FD31:F0) ................................................................................ 438

13.1.20LPC_IBDFIOxAPIC Bus:Device:Function(LPC I/FD31:F0) ................................................................................ 439

13.1.21LPC_I/O_DECI/O Decode Ranges Register(LPC I/FD31:F0) ................................................................................ 439

13.1.22LPC_ENLPC I/F Enables Register (LPC I/FD31:F0) ................................ 440

13.1.23GEN1_DECLPC I/F Generic Decode Range 1 Register(LPC I/FD31:F0) ................................................................................ 441




13.1.27FWH_SEL1Firmware Hub Select 1 Register(LPC I/FD31:F0) ................................................................................ 444

13.1.28FWH_SEL2Firmware Hub Select 2 Register(LPC I/FD31:F0) ................................................................................ 445

13.1.29FWH_DEC_EN1Firmware Hub Decode Enable Register(LPC I/FD31:F0) ................................................................................ 445

13.1.30BIOS_CNTLBIOS Control Register(LPC I/FD31:F0) ................................................................................ 449


15/882


13.1.31FDCAPFeature Detection Capability ID(LPC I/FD31:F0) ................................................................................ 450

13.1.32FDLENFeature Detection Capability Length(LPC I/FD31:F0) ................................................................................ 450

13.1.33FDVERFeature Detection Version

(LPC I/FD31:F0) ................................................................................ 45013.1.34FDVCTFeature Vector

(LPC I/FD31:F0) ................................................................................ 451

13.1.35RCBARoot Complex Base Address Register(LPC I/FD31:F0) ................................................................................ 451

13.2 DMA I/O Registers (LPC I/FD31:F0) ................................................................ 452

13.2.1 DMABASE_CADMA Base and Current AddressRegisters (LPC I/FD31:F0) .................................................................. 453

13.2.2 DMABASE_CCDMA Base and Current Count Registers(LPC I/FD31:F0) ................................................................................ 454

13.2.3 DMAMEM_LPDMA Memory Low Page Registers(LPC I/FD31:F0) ................................................................................ 454

13.2.4 DMACMDDMA Command Register (LPC I/FD31:F0).............................. 455

13.2.5 DMASTADMA Status Register (LPC I/FD31:F0).................................... 455

13.2.6 DMA_WRSMSKDMA Write Single Mask Register(LPC I/FD31:F0) ................................................................................ 45613.2.7 DMACH_MODEDMA Channel Mode Register

(LPC I/FD31:F0) ................................................................................ 457

13.2.8 DMA Clear Byte Pointer Register (LPC I/FD31:F0) .................................. 458

13.2.9 DMA Master Clear Register (LPC I/FD31:F0).......................................... 458

13.2.10DMA_CLMSKDMA Clear Mask Register (LPC I/FD31:F0) ........................ 45813.2.11DMA_WRMSKDMA Write All Mask Register

(LPC I/FD31:F0) ................................................................................ 459

13.3 Timer I/O Registers (LPC I/FD31:F0)............................................................... 460

13.3.1 TCWTimer Control Word Register (LPC I/FD31:F0) .............................. 461

13.3.2 RDBK_CMDRead Back Command (LPC I/FD31:F0)............................... 46213.3.3 SBYTE_FMTInterval Timer Status Byte Format Register

(LPC I/FD31:F0) ................................................................................ 463

13.3.4 Counter Access Ports Register (LPC I/FD31:F0) ..................................... 464

13.4 8259 Interrupt Controller (PIC) Registers(LPC I/FD31:F0) ........................................................................................... 465

13.4.1 Interrupt Controller I/O MAP (LPC I/FD31:F0) ....................................... 465

13.4.2 ICW1Initialization Command Word 1 Register(LPC I/FD31:F0) ................................................................................ 466


13.4.4 ICW3Master Controller Initialization CommandWord 3 Register (LPC I/FD31:F0)......................................................... 468

13.4.5 ICW3Slave Controller Initialization CommandWord 3 Register (LPC I/FD31:F0)......................................................... 468


13.4.7 OCW1Operational Control Word 1 (Interrupt Mask)

Register (LPC I/FD31:F0).................................................................... 46913.4.8 OCW2Operational Control Word 2 Register

(LPC I/FD31:F0) ................................................................................ 470

13.4.9 OCW3Operational Control Word 3 Register(LPC I/FD31:F0) ................................................................................ 471

13.4.10ELCR1Master Controller Edge/Level Triggered Register(LPC I/FD31:F0) ................................................................................ 472

13.4.11ELCR2Slave Controller Edge/Level Triggered Register(LPC I/FD31:F0) ................................................................................ 473


16/882


13.5 Advanced Programmable Interrupt Controller (APIC)(D31:F0)................................474

13.5.1 APIC Register Map (LPC I/FD31:F0)......................................................474

13.5.2 INDIndex Register (LPC I/FD31:F0) ...................................................474

13.5.3 DATData Register (LPC I/FD31:F0) ....................................................475

13.5.4 EOIREOI Register (LPC I/FD31:F0) ....................................................475

13.5.5 IDIdentification Register (LPC I/FD31:F0)...........................................47613.5.6 VERVersion Register (LPC I/FD31:F0) ................................................476

13.5.7 REDIR_TBLRedirection Table (LPC I/FD31:F0) .....................................477

13.6 Real Time Clock Registers .................................................................................479

13.6.1 I/O Register Address Map ......................................................................479

13.6.2 Indexed Registers.................................................................................480

13.6.2.1 RTC_REGARegister A ............................................................48113.6.2.2 RTC_REGBRegister B (General Configuration)...........................48213.6.2.3 RTC_REGCRegister C (Flag Register).......................................48313.6.2.4 RTC_REGDRegister D (Flag Register).......................................483

13.7 Processor Interface Registers (LPC I/FD31:F0)..................................................484

13.7.1 NMI_SCNMI Status and Control Register(LPC I/FD31:F0) ................................................................................ 484

13.7.2 NMI_ENNMI Enable (and Real Time Clock Index)

Register (LPC I/FD31:F0) .................................................................... 48513.7.3 PORT92Fast A20 and Init Register (LPC I/FD31:F0) .............................485

13.7.4 COPROC_ERRCoprocessor Error Register(LPC I/FD31:F0) ................................................................................ 486

13.7.5 RST_CNTReset Control Register (LPC I/FD31:F0).................................486

13.8 Power Management Registers (PMD31:F0) .......................................................487

13.8.1 Power Management PCI Configuration Registers(PMD31:F0) ......................................................................................487

13.8.1.1 GEN_PMCON_1General PM Configuration 1 Register(PMD31:F0) ......................................................................... 488



13.8.1.4 GEN_PMCON_LOCK- General Power Management

Configuration Lock Register ...................................................... 49413.8.1.5 C5_EXIT_TIMING_CNT- C5 Exit Timing Register (Mobile Only).......49513.8.1.6 Cx-STATE_CNFCx State Configuration Register

(PMD31:F0) (Mobile Only, Except Bit 2)................................... 49613.8.1.7 C4-TIMING_CNTC4 Timing Control Register

(PMD31:F0) (Mobile Only) .....................................................49713.8.1.8 BM_BREAK_EN Register (PMD31:F0) (Mobile Only) ...................49813.8.1.9 PMIRPower Management Initialization Register (PMD31:F0).....49913.8.1.10GPIO_ROUTGPIO Routing Control Register

(PMD31:F0) ......................................................................... 499

13.8.2 APM I/O Decode ...................................................................................500

13.8.2.1 APM_CNTAdvanced Power Management Control Port Register .....50013.8.2.2 APM_STSAdvanced Power Management Status Port Register ......500

13.8.3 Power Management I/O Registers ...........................................................50113.8.3.1 PM1_STSPower Management 1 Status Register.........................50313.8.3.2 PM1_ENPower Management 1 Enable Register..........................50613.8.3.3 PM1_CNTPower Management 1 Control....................................50713.8.3.4 PM1_TMRPower Management 1 Timer Register .........................50813.8.3.5 PROC_CNTProcessor Control Register......................................50813.8.3.6 LV2 Level 2 Register ............................................................51013.8.3.7 LV3Level 3 Register (Mobile Only)...........................................51013.8.3.8 LV4Level 4 Register (Mobile Only)...........................................51013.8.3.9 LV5Level 5 Register (Mobile Only)...........................................51113.8.3.10LV6Level 6 Register (Mobile Only)........................................... 511


17/882


13.8.3.11GPE0_STSGeneral Purpose Event 0 Status Register .................. 51213.8.3.12GPE0_ENGeneral Purpose Event 0 Enables Register .................. 51513.8.3.13SMI_ENSMI Control and Enable Register ................................. 51713.8.3.14SMI_STSSMI Status Register ................................................. 51913.8.3.15ALT_GP_SMI_ENAlternate GPI SMI Enable Register .................. 521

13.8.3.16ALT_GP_SMI_STSAlternate GPI SMI Status Register ................. 52213.8.3.17UPRWCUSB Per-Port Registers Write Control............................ 52213.8.3.18GPE_CNTL General Purpose Control Register............................ 52313.8.3.19DEVACT_STS Device Activity Status Register .......................... 52313.8.3.20PM2_CNTPower Management 2 Control (Mobile Only)................ 52413.8.3.21C3_RES C3 Residency Register (Mobile Only)........................... 52413.8.3.22C5_RES C5 Residency Register (Mobile Only)........................... 525

13.9 System Management TCO Registers (D31:F0) ..................................................... 526

13.9.1 TCO_RLDTCO Timer Reload and Current Value Register .......................... 526

13.9.2 TCO_DAT_INTCO Data In Register ....................................................... 527

13.9.3 TCO_DAT_OUTTCO Data Out Register .................................................. 527

13.9.4 TCO1_STSTCO1 Status Register .......................................................... 527

13.9.5 TCO2_STSTCO2 Status Register .......................................................... 529

13.9.6 TCO1_CNTTCO1 Control Register ......................................................... 531

13.9.7 TCO2_CNTTCO2 Control Register ......................................................... 532

13.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers....................................... 532

13.9.9 TCO_WDCNTTCO Watchdog Control Register......................................... 533

13.9.10SW_IRQ_GENSoftware IRQ Generation Register .................................... 533

13.9.11TCO_TMRTCO Timer Initial Value Register............................................. 53313.10 General Purpose I/O Registers (D31:F0)............................................................. 534

13.10.1GPIO_USE_SELGPIO Use Select Register [31:0] .................................... 535

13.10.2GP_IO_SELGPIO Input/Output Select Register [31:0] ............................. 535

13.10.3GP_LVLGPIO Level for Input or Output Register [31:0] ........................... 536

13.10.4GPO_BLINKGPO Blink Enable Register [31:0] ........................................ 536

13.10.5GP_SER_BLINK[31:0]GP Serial Blink [31:0] .......................................... 537

13.10.6GP_SB_CMDSTS[31:0]GP Serial Blink Command Status [31:0]................ 53813.10.7GP_SB_DATA[31:0]GP Serial Blink Data [31:0] ..................................... 538

13.10.8GPI_INVGPIO Signal Invert Register [31:0]........................................... 539

13.10.9GPIO_USE_SEL2GPIO Use Select 2 Register [60:32] .............................. 539

13.10.10GP_IO_SEL2GPIO Input/Output Select 2 Register [60:32] ..................... 540

13.10.11GP_LVL2GPIO Level for Input or Output 2 Register [63:32] ................... 540

1 4 SAT A Co nt r ol le r Re gi st e rs ( D 3 1 :F2 ) ....................................................................... 541

14.1 PCI Configuration Registers (SATAD31:F2)........................................................ 541

14.1.1 VIDVendor Identification Register (SATAD31:F2) ................................ 542

14.1.2 DIDDevice Identification Register (SATAD31:F2)................................. 543

14.1.3 PCICMDPCI Command Register (SATAD31:F2)..................................... 543

14.1.4 PCISTS PCI Status Register (SATAD31:F2)......................................... 544

14.1.5 RIDRevision Identification Register (SATAD31:F2)............................... 54514.1.6 PIProgramming Interface Register (SATAD31:F2)................................. 545

14.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h .......... 54514.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h .......... 54614.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h .......... 546

14.1.7 SCCSub Class Code Register (SATAD31:F2) ........................................ 54614.1.8 BCCBase Class Code Register (SATAD31:F2SATAD31:F2).................... 547

14.1.9 PMLTPrimary Master Latency Timer Register (SATAD31:F2)................... 547

14.1.10HTYPEHeader Type (SATAD31:F2) ..................................................... 547

14.1.11PCMD_BARPrimary Command Block Base AddressRegister (SATAD31:F2) ....................................................................... 547

14.1.12PCNL_BARPrimary Control Block Base Address Register(SATAD31:F2).................................................................................... 548


18/882


14.1.13SCMD_BARSecondary Command Block Base AddressRegister (IDE D31:F1)...........................................................................548

14.1.14SCNL_BARSecondary Control Block Base AddressRegister (IDE D31:F1)...........................................................................548

14.1.15BAR Legacy Bus Master Base Address Register

(SATAD31:F2) .................................................................................... 54914.1.16ABAR/SIDPBA1 AHCI Base Address Register/Serial ATA Index

Data Pair Base Address (SATAD31:F2)...................................................549

14.1.16.1When SCC is not 01h ............................................................... 54914.1.16.2When SCC is 01h .................................................................... 550

14.1.17SVIDSubsystem Vendor Identification Register (SATAD31:F2) ................550

14.1.18SIDSubsystem Identification Register (SATAD31:F2)............................. 550

14.1.19CAPCapabilities Pointer Register (SATAD31:F2) .................................... 550

14.1.20INT_LNInterrupt Line Register (SATAD31:F2).......................................551

14.1.21INT_PNInterrupt Pin Register (SATAD31:F2) ........................................551

14.1.22IDE_TIM IDE Timing Register (SATAD31:F2).......................................551

14.1.23PIDPCI Power Management Capability IdentificationRegister (SATAD31:F2)........................................................................551

14.1.24PCPCI Power Management Capabilities Register

(SATAD31:F2) .................................................................................... 55214.1.25PMCSPCI Power Management Control and Status

Register (SATAD31:F2)........................................................................552

14.1.26MSICIMessage Signaled Interrupt Capability Identification (SATAD31:F2) 553

14.1.27MSIMCMessage Signaled Interrupt Message Control (SATAD31:F2)......... 554

14.1.28MSIMA Message Signaled Interrupt Message Address (SATAD31:F2) ....... 555

14.1.29MSIMDMessage Signaled Interrupt Message Data (SATAD31:F2) ............555

14.1.30MAPAddress Map Register (SATAD31:F2).............................................556

14.1.31PCSPort Control and Status Register (SATAD31:F2) ..............................556

14.1.32SCLKCG - SATA Clock Gating Control Register ..........................................559

14.1.33SCLKGC - SATA Clock General Configuration Register ................................ 560

14.1.33.1SATACR0SATA Capability Register 0 (SATAD31:F2) .................56114.1.33.2SATACR1SATA Capability Register 1 (SATAD31:F2) .................561

14.1.34FLRCIDFLR Capability ID (SATAD31:F2) .............................................. 562

14.1.35FLRCLVFLR Capability Length and Version (SATAD31:F2)....................... 56214.1.36FLRCFLR Control (SATAD31:F2) .........................................................563

14.1.37ATCAPM Trapping Control Register (SATAD31:F2).................................563

14.1.38ATSAPM Trapping Status Register (SATAD31:F2).................................. 564

14.1.39SP Scratch Pad Register (SATAD31:F2) .................................................. 564

14.1.40BFCSBIST FIS Control/Status Register (SATAD31:F2) ...........................565

14.1.41BFTD1BIST FIS Transmit Data1 Register (SATAD31:F2) ........................567

14.1.42BFTD2BIST FIS Transmit Data2 Register (SATAD31:F2) ........................567

14.2 Bus Master IDE I/O Registers (D31:F2)...............................................................568

14.2.1 BMIC[P,S]Bus Master IDE Command Register (D31:F2) .

Io Controller Hub 9 Datasheet

Documents

Transcript of Io Controller Hub 9 Datasheet