InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5...

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InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth by MBE regrowth Uttam Singisetti*, Mark A. Wistey, Greg J. Burek, Erdem Arkun, Ashish K. Baraskar, Brian J. Thibeault, C. J. Palmstrøm, A.C. Gossard, and M.J.W. Rodwell ECE and Materials Departments University of California, Santa Barbara, CA, USA S d d d Sd Yanning Sun, Edward W. Kiewra, and D.K. Sadana IBM T J Watson Research Center, Yorktown Heights, NY, USA 2008 International Symposium on Compound Semiconductors ISCS 2008 Rust, Germany *[email protected]

Transcript of InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5...

Page 1: InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5 mA/μm1,2 Y (Ang.) • 1 nm EOT gate dielectric Key Challenges • 5 nm channel with back

InGaAs MOSFET with self-aligned Source/Drain by MBE regrowthby MBE regrowth

Uttam Singisetti*, Mark A. Wistey, Greg J. Burek, Erdem Arkun, Ashish K. Baraskar, Brian J. Thibeault, C. J. Palmstrøm, A.C. Gossard, and M.J.W. Rodwell

ECE and Materials DepartmentsUniversity of California, Santa Barbara, CA, USA

S d d d S dYanning Sun, Edward W. Kiewra, and D.K. SadanaIBM T J Watson Research Center, Yorktown Heights, NY, USA

2008 International Symposium on Compound Semiconductors

ISCS 2008

y p pRust, Germany

*[email protected]

Page 2: InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5 mA/μm1,2 Y (Ang.) • 1 nm EOT gate dielectric Key Challenges • 5 nm channel with back

Outline

• Motivation: III-V MOSFETs• Motivation: III-V MOSFETs

• Approach: Self-aligned source/drain by MBE regrowthMBE regrowth

• FET and Contacts Results

• Conclusion

ISCS 2008

Page 3: InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5 mA/μm1,2 Y (Ang.) • 1 nm EOT gate dielectric Key Challenges • 5 nm channel with back

Why III-V MOSFETs

Silicon MOSFETs:• Scaling limit beyond sub-22 nm Lgg y g

• Non-feasibility of sub-0.5 nm equivalent oxide thickness (EOT)

Alternative III-V channel materialsIII V t i l l * hi h l iti ( )

( )

Id / Wg = qnsveff Id / Qtransit = veff / Lg

III-V materials→ lower m*→ higher velocities (veff)

scmvvmmAsGaIn theff /105.3~ ,041.0 : 7*47.053.0 ⋅=⋅=

ISCS 2008

Page 4: InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5 mA/μm1,2 Y (Ang.) • 1 nm EOT gate dielectric Key Challenges • 5 nm channel with back

22 nm InGaAs MOSFET4

metal gate

gLgatedielectric

source contact drain contact

S/DL

0

2

4

)

InGaAs InAlAs

Al2O3

InP

InP substrate

InAlAs barrierInGaAs channelN+ source N+ drain

4

-2

0

Eneg

y(eV

)

-6

-4

0 50 100 150 200 250Y (Ang )

Predicted drive current: ~5 mA/μm1,2

Y (Ang.)

• 1 nm EOT gate dielectricKey Challenges

• 5 nm channel with back barrier• 15 Ω−μm source resistance

ISCS 2008

1 Rodwell. IPRM 20082 Fischetti. IEDM 2007

• 5×1019 cm-3 source active doping2

Page 5: InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5 mA/μm1,2 Y (Ang.) • 1 nm EOT gate dielectric Key Challenges • 5 nm channel with back

InGaAs MOSFET with Source/Drain regrowth

substrate

barrier

metal gate

InGaAs quantum well

Process scalable to 22 nm

substrate

metal gate

I G A t ll

Source/Drain defined byMBE regrowth

substratebarrier

InGaAs quantum well

sidewall Regrowth InGaAs in situ Mo

b

barrier

sidewallmetal gate

InGaAs quantum wellN+ source N+ drain

Regrowth InGaAs, in situ Mo contact Resistance:0 5 Ω 2 (2 5 Ω )*

sidewallmetal gate

gate dielectric

N+ source N+ drain

source contact drain contact

substrate 0.5 Ω−μm2 (2.5 Ω−μm)*

ISCS 2008

substratebarrier

InGaAs quantum wellN+ source N+ drain

* Wistey, EMC 2008

Page 6: InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5 mA/μm1,2 Y (Ang.) • 1 nm EOT gate dielectric Key Challenges • 5 nm channel with back

Process flow

Gate definition Sidewall, Source/Drain

Ti/Wgate

blanketmetal

side-wall

εr

oxideInGaAs channel

barrier

SI substrate

InP subchannel

εr

wellεr

wellεr

well

(starting material) blanket gatedeposition

etch gate,etch dielectricetch upper channel

sidewall formationS/D regrowthS/D contacts

mesa isolate S/D

ISCS 2008

Page 7: InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5 mA/μm1,2 Y (Ang.) • 1 nm EOT gate dielectric Key Challenges • 5 nm channel with back

Gate Definition: Challenges

εr

εr

εr

wellInP well

iondamage

barrierInP well

• Must scale to 22 nm• Dielectric cap surrounding the gate for source/drain regrowth• Metal & Dielectric etch must stop in 5 nm channel• Dry etch must not damage thin channel

ISCS 2008

Process must leave surfaces ready for S/D regrowth

Page 8: InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5 mA/μm1,2 Y (Ang.) • 1 nm EOT gate dielectric Key Challenges • 5 nm channel with back

Gate Stack: Multiple Layers & Selective Etches

Key: stop etch before reaching dielectric, then gentle low-power etch to stop on dielectric

FIB Cross section

SiO2

FIB Cross-section

Damage free channel

SiO2

Cr etch mask

resist Cl2 / O2etch 15 W

SF6 / Aretch 50 W

Cl2 / O2t h 15 W

CrCr etch stop

W gate metal

etch 15 W

SF6 / Aretch 15 W dielectric

KOH wet etchAl2O3 (εr)

W

barrier

InGaAs wellInP well

SI substrate

2 3

SI substrate

Dry etch scheme

Process scalable to sub 100 nm gate lengths

ISCS 2008

Process scalable to sub-100 nm gate lengths

Page 9: InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5 mA/μm1,2 Y (Ang.) • 1 nm EOT gate dielectric Key Challenges • 5 nm channel with back

Dielectric etch and sidewall formation

εrεrεr

dil KOH

40 nm SiNsidewall

InGaAs wellεr

InP well

εrwell

b iInP well

InGaAs wellεr

InP wellbarrier barrierbarrier

Dielectric etch Sidewall definition InGaAs etch

ISCS 2008

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Surface cleaning before regrowth

• Clean organics by 30 min UV Ozone

E it HCl H O l

HAADF-STEM*

InGaAsregrowth• Ex-situ HCl:H2O clean

• In-situ 30 min H clean

Interface

InGaAs

regrowth

• c(4×2) reconstruction before regrowth 2 nm

• Defect free regrowth

Epi read s rface before regro th Epi-ready surface before regrowth, defect free regrowth on processed wafer

ISCS 2008* Wistey, EMC 2008

Page 11: InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5 mA/μm1,2 Y (Ang.) • 1 nm EOT gate dielectric Key Challenges • 5 nm channel with back

Height selective Etching*

εrεrεrPlanarize

ICP O2 ash SF6/Ar Mo etch

InGaAs wet etch

MoPR

εrεr

well well

InP well InP well

εr

wellInP well

PR PR

barrierInP well

barrierbarrierInGaAs

Dummy gate

εr

εr

εr

εrStrip PRy g

No regrowth

well

barrierInP well

well

barrierInP well

ISCS 2008* Burek, J.Cryst.Growth, submitted for publication

Page 12: InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5 mA/μm1,2 Y (Ang.) • 1 nm EOT gate dielectric Key Challenges • 5 nm channel with back

MOSFET characterstics

80

100

tV0 25iV2tV0V

microns 50 Wmicrons, 10 g ==gL80

100

A)

Lg=10μm, W

g=50μm

Vds

=2V

40

60

80

n C

urre

nt, u

A steps V 0.25in V 2 toV 0Vg =

40

60

80

ain

curr

ent (

μA ds

0

20

40

Dra

in

0

20

0 0 5 1 1 5 2

Dra

Rs ~ 1 MΩ−μm!

00 0.5 1 1.5 2

Vds, Volts

0 0.5 1 1.5 2V

gs(Volts)

Extremely low drive current: 2 A/ m• Extremely low drive current: 2 μA/μm• Extremely high Ron= 10-100 kΩ

• Why is R so high?

ISCS 2008

• Why is Rs so high?

Page 13: InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5 mA/μm1,2 Y (Ang.) • 1 nm EOT gate dielectric Key Challenges • 5 nm channel with back

Aft th

Source Resistance 1: Poly Growth on InP

After regrowth SEM

Rough InGaAs oug Ga sregrowth InGaAs regrowth on unprocessed thin InP*

• Spotty RHEED during regrowth: faceted growth• InP desorbs P during hydrogen clean or regrowth: InP converts to highly-

strained InAs*

• From TLM measurement, Rsh= 310 Ω/, ρc=130 Ω−μm2 and Rs= 300 Ω−μm

ISCS 2008* Wistey (in preparation)

Sheet resistance doesn’t explain 1 MΩ-µm source resistance.

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Source Resistance 2: Gap in Regrowth

1200

W / Cr / SiO2 gate W / Cr / SiO2

SEM

No regrowthN th

SEMInGaAs regrowth

InGaAs regrowth

800

1000

1200L = 10 μm W=10 μm V

g=0.0 V

W

Cr

SiO2N+ regrowthGap~ 200 nm

2 g 2 gateElectron depletion No regrowth

400

600

I d (μA

) εr

InGaAs

barrierInP

W

Electron depletion

0

200

0 2 4 6 8V (V)

• No regrowth within 200 nm of gate because of shadowing by gate

• Gap region is depleted of electrons

Vds

(V)

Gap region is depleted of electrons

• Breakdown at Vg=0V, ~ 8V, consistent with 400 nm gap and InGaAs breakdown field of 20V/μm*

ISCS 2008

μ

High source resistance because of electron depletion in the gap*http://www.ioffe.rssi.ru/SVA/NSM/Semicond/

Page 15: InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5 mA/μm1,2 Y (Ang.) • 1 nm EOT gate dielectric Key Challenges • 5 nm channel with back

Regrowth: Solutions

smooth InGaAs regrowth on thin InGaP* High T migration enhancedEpitaxial (MEE) regrowth*

N Ggate

No Gap

regrowth interface

ISCS 2008

*Wistey, EMC 2008Wistey, ICMBE 2008

Page 16: InGaAs MOSFET with self-aligned Source/Drain by MBE regrowth · Predicted drive current: ~5 mA/μm1,2 Y (Ang.) • 1 nm EOT gate dielectric Key Challenges • 5 nm channel with back

Conclusion

• Scalable III-V MOSFET process with self-aligned source/drain with MBE regrowth

G t d H l l i d 5 h l• Gate proces and H clean leave a epi-ready 5 nm channel

• Low drive current in initial devices because of break in regrowth

• Improved regrowth techniques in next generation of devices

This ork as s pported b Semicond ctor Research Corporation nder the

ISCS 2008

This work was supported by Semiconductor Research Corporation under theNon-classical CMOS Research Program