iC-LNB WITH SPI, SERIAL, AND PARALLEL INTERFACES...iC-LNB 18-BITOPTICALENCODER...

iC-LNB 18-BIT OPTICAL ENCODERWITH SPI, SERIAL, AND PARALLEL INTERFACES

Rev D1, /45

FEATURES

System-on-chip design for excellent reliability Leading/trailing sampling of 10 binary tracks pitched at 400 µm Analog sine/cosine scanning with enlarged photodiodes, signal

conditioning and fast 8-bit vector-tracking interpolation Absolute singleturn resolution up to 18 bits FlexCount® provides programmable resolution for absolute and

incremental data Incremental quadrature outputs with 1 to 65,536 CPR and

programmable index signal LED illumination control using 50 mA high-side current source

(sin2+cos2 or sum control modes) Alarm indication for configuration or illumination error Permanent RAM monitoring by parity bits 3.3 V-compatible SPI and I/O ports for configuration and data Serial position readout in 1 µs cycles at 16 MHz clock frequency Parallel position output resolution up to 16 bits Operation at 4 V to 5.5 V within –40 °C to 110 °C 30-pin optoBGA or 38-pin optoQFN package for SMT Illumination: iC-SN85 BLCC SN1C (850 nm encoder LED) Code discs: LNB1S 42-1024 (1024 PPR, ∅42 mm/18 mm),

LNB4S 26-1024 (1024 PPR, ∅26 mm/9.6 mm)

APPLICATIONS

Programmable incrementalencoders

Optical position sensors Absolute rotary encoders Motor feedback systems Linear scales

PACKAGES

30-pin optoBGA7.6 mm x 7.1 mm x 1.6 mm

38-pin optoQFN7.0 mm x 5.0 mm x 0.9 mm

BLOCK DIAGRAM

DIN

DOUT

CLK

CS

MOSI

MISO

SCK

GND

VDD

INCZ

+3 V ... 5.5 V

NSL

DIR

iC-LNB

sindig

GB

XJD

GA

INCB

INCA

R2R1

+4 V ... 5.5 V

CVDDA

SPI

SER

PAR

P0...15 Power-On

Interpolation6/7/8 bit

CosineSine

P

N

LED Controlsin2+cos2, sum

Calibration

INC

CVDD

LEDiC-SN85Error

D1

GNDA

VDDA

LED

ERR

PSIN

NSIN

PCOS

NCOS

TPC

TNC

TPS

TNS

POK

Copyright © 2013, 2020 iC-Haus http://www.ichaus.com

http://www.ichaus.com


Rev D1, /45

DESCRIPTION

The iC-LNB is an optoelectronic encoder IC for ab-solute linear and angle measuring systems. Whencombined with a linear scale or rotary encoder disc,the iC-LNB provides complete encoder functionality.Photodiodes, amplifiers, comparators, a complete sig-nal conditioning unit, and multiple interfaces for posi-tion data output are monolithically integrated into thedevice.

The iC-LNB reads ten absolute tracks as well as anincremental track from the disc or scale. The incre-mental track provides sine and cosine signals whichcan be calibrated to compensate the offset and scalethe amplitude of the photodiodes. These calibratedsignals are used by the integrated vector-trackinginterpolator to provide up to 8 bits of additional resolu-tion and are also available on dedicated output pins.Combined with the 10 bits of absolute position, theinterpolator provides resolution of up to 18 bits.

An integrated LED current control with a built-indriver allows direct connection of the illumination LED(iC-SN85 or other). The optical power received bythe iC-LNB is kept constant by the current control, re-gardless of temperature and aging effects of the LED.The received power setpoint is programmable and anend-of-life alarm and error pin output indicate whenthe LED current control has exceeded its operatingrange.

The iC-LNB synchronizes the interpolator output andthe absolute data to form a contiguous Gray-codedposition data word. This position or angle data is out-put as incremental ABZ signals, absolute position viaa scalable shift-register, and through the SPI interface.Alternatively, a 16-bit parallel position output is alsoavailable. FlexCount® allows the output position (in-cremental and absolute) resolution to be programmedto any value between 4 and 218 steps (edges) perrevolution.

After startup, the iC-LNB must be configured via theSPI interface. The SPI interface (as well as all theother digital I/O) operates at 3.3 V, allowing direct con-nection to 3.3 V microcontrollers.

General notice on application-specific programmingParameters defined in the datasheet represent supplier’sattentive tests and validations, but - by principle - do not implyany warranty or guarantee as to their accuracy, completeness orcorrectness under all application conditions. In particular, setupconditions, register settings and power-up have to be thoroughlyvalidated by the user within his specific application environmentand requirements (system responsibility).

The chip’s performance in application is impacted by sys-tem conditions like the quality of the optical target, theillumination, temperature and mechanical stress, sensoralignment and initial calibration.


Rev D1, /45

CONTENTS

PACKAGING INFORMATION 4PIN CONFIGURATION

oBGA LNB2C(7.6 mm x 7.1 mm x 1.6 mm) . . . . . . . 4

PIN CONFIGURATIONoQFN38-7x5(7.0 mm x 5.0 mm x 0.9 mm)(in qualification) . . . . . . . . . . . . . . 5

PAD LAYOUT . . . . . . . . . . . . . . . . . 6PACKAGE DIMENSIONS oQFN38-7x5 . . . 7

ABSOLUTE MAXIMUM RATINGS 8

THERMAL DATA 8

ELECTRICAL CHARACTERISTICS 9

OPERATING REQUIREMENTS 15SPI Interface . . . . . . . . . . . . . . . . . . 15Shift Register . . . . . . . . . . . . . . . . . 16

CONFIGURATION PARAMETERS 17

CONFIGURING THE iC-LNB 18Address Range . . . . . . . . . . . . . . . . . 18RAM Monitoring (parity check) . . . . . . . . 18Chip Version . . . . . . . . . . . . . . . . . . 18Reset Values . . . . . . . . . . . . . . . . . . 19Programming Sequence . . . . . . . . . . . . 19

SPI INTERFACE 21General Protocol Description . . . . . . . . . 21Opcodes . . . . . . . . . . . . . . . . . . . . 21Bussing and Chaining Multiple iC-LNBs . . . 25

SIGNAL CONDITIONING 26Gain Range (GR) . . . . . . . . . . . . . . . . 26Sine Gain (GS) and Offsets (OSP and OSN) 26Cosine Gain (GC) and Offsets (OCP and OCN) 27LED Power Control . . . . . . . . . . . . . . . 27

INTERPOLATOR 28Interpolator Resolution . . . . . . . . . . . . . 28Interpolator Hysteresis . . . . . . . . . . . . . 28Interpolator Filter . . . . . . . . . . . . . . . . 28

FLEXCOUNT® 29

Enable/Disable . . . . . . . . . . . . . . . . . 29Incremental FlexCount Output . . . . . . . . 29Absolute FlexCount Output . . . . . . . . . . 29Resolution . . . . . . . . . . . . . . . . . . . 29Position offset . . . . . . . . . . . . . . . . . . 30Absolute Position Numeric Formats . . . . . 30Changing FlexCount Resolution, Offset,

or Direction . . . . . . . . . . . . . . . . 30

OPERATING MODE 32Interface Mode . . . . . . . . . . . . . . . . . 32Parallel Mode . . . . . . . . . . . . . . . . . . 32

INCREMENTAL (ABZ) OUTPUTS 33ABZ Resolution . . . . . . . . . . . . . . . . . 33Direction Reversal . . . . . . . . . . . . . . . 33Incremental Output Inversion . . . . . . . . . 33INCZ Position . . . . . . . . . . . . . . . . . . 33INCZ Width . . . . . . . . . . . . . . . . . . . 34Tristate . . . . . . . . . . . . . . . . . . . . . 34

SHIFT REGISTER OUTPUT 35Output Data Length . . . . . . . . . . . . . . 35Output Data Format . . . . . . . . . . . . . . 35Idle Output . . . . . . . . . . . . . . . . . . . 35Direction Reversal . . . . . . . . . . . . . . . 36Shift Register Disable . . . . . . . . . . . . . 36

GRAY CODE OUTPUTS 36

PARALLEL OUTPUT MODE 37

ADJUSTMENTS 38Tilt Angle . . . . . . . . . . . . . . . . . . . . 38Radial Position . . . . . . . . . . . . . . . . . 38

LED POWER CONTROL 39

ALARM OUTPUT 39

OSCILLATOR 40

TEST FUNCTIONS 41

DESIGN REVIEW: Notes On Chip Functions 42

REVISION HISTORY 43


Rev D1, /45

PACKAGING INFORMATION

PIN CONFIGURATIONoBGA LNB2C(7.6 mm x 7.1 mm x 1.6 mm)

<D-COD

E><A

-COD

E>

<P-COD

E>

1 2 3 4 5 6

B

C

D

E

A

PIN FUNCTIONSNo. Name FunctionA1 SCLK SPI Clock InputA2 VDD + 3 V ... +5.5 V I/O Ports Supply VoltageA3 GND I/O Ports GroundA4 LED LED High-Side Current SourceA5 VDDA + 4 V ... +5.5 V Supply VoltageA6 GNDA GroundB1 CS SPI Chip Select InputB2 MISO SPI Data OutputB3 MOSI SPI Data InputB4 PCOS Analog Voltage Output PCOSB5 NSIN Analog Voltage Output NSINB6 PSIN Analog Voltage Output PSIN

PIN FUNCTIONSNo. Name FunctionC1 DIR Code Inversion Input /

Parallel Output Bit 13C2 TNS Test Input NSIN /

Parallel Output Bit 14C3 TNC Test Input NCOS /

Parallel Output Bit 15C4 TPS Test Input PSIN /

Parallel Output Bit 1C5 TPC Test Input PCOS /

Parallel Output Bit 0C6 NCOS Analog Voltage Output NCOSD1 DOUT Shift Register Data Output /

Parallel Output Bit 10D2 DIN Shift Register Data Input /

Parallel Output Bit 11D3 NSL Shift Register Load Input (active low) /

Parallel Output Bit 12D4 INCB Incremental Output B /

Parallel Output Bit 3D5 INCA Incremental Output A /

Parallel Output Bit 2D6 ERR Error Message Output (active high)E1 GB Gray Code Output B (MSB-1) /

Parallel Output Bit 7E2 GA Gray Code Output A (MSB) /

Parallel Output Bit 8E3 CLK Shift Register Clock Input /

Parallel Output Bit 9E4 XJD Adjustment Signal /

Parallel Output Bit 6E5 POK Power OK Indication/

Parallel Output Bit 5E6 INCZ Incremental Output Z /

Parallel Output Bit 4

IC top marking: <P-CODE> = product code, <A-CODE> = assembly code (subject to changes), <D-CODE> = date code (subject to changes);Grounding unused inputs (10 kΩ to GNDA) is recommended, especially for pins DIR, TPS, TNS, TPC, and TNC.For dimensional specifications, refer to package datasheet iC-LNB oBGA LNB2C, available separately.


Rev D1, /45

PIN CONFIGURATIONoQFN38-7x5 (7.0 mm x 5.0 mm x 0.9 mm)(in qualification)

1234567

8 9 10 11 12 13 14 15 16 17 18 19

20212223242526

272829303132333435363738

<A-CODE>

<P-CODE>

PIN FUNCTIONSNo. Name Function

1 GNDA Ground2-6 n.c. 1 Not Connected

7 GND I/O Ports Ground8 VDD + 3 V ... +5.5 V I/O Ports Supply Voltage9 SCLK SPI Clock Input

10 MOSI SPI Data Input11 MISO SPI Data Output12 CS SPI Chip Select Input13 TNC Test Input NCOS /

Parallel Output Bit 1514 TNS Test Input NSIN /

Parallel Output Bit 1415 DIR Code Inversion Input /

Parallel Output Bit 13

PIN FUNCTIONSNo. Name Function

16 NSL Shift Register Load Input (active low) /Parallel Output Bit 12

17 DIN Shift Register Data Input /Parallel Output Bit 11

18 DOUT Shift Register Data Output /Parallel Output Bit 10

19 CLK Shift Register Clock Input /Parallel Output Bit 9

20 GB Gray Code Output B (MSB-1) /Parallel Output Bit 7

21 GA Gray Code Output A (MSB) /Parallel Output Bit 8

22-24 n.c. 1 Not Connected25 POK Power OK Indication/

Parallel Output Bit 526 XJD Adjustment Signal /

Parallel Output Bit 627 INCZ Incremental Output Z /

Parallel Output Bit 428 INCB Incremental Output B /

Parallel Output Bit 329 INCA Incremental Output A /

Parallel Output Bit 230 ERR Error Message Output (active high)31 TPS Test Input PSIN /

Parallel Output Bit 132 TPC Test Input PCOS /

Parallel Output Bit 033 NCOS Analog Voltage Output NCOS34 PCOS Analog Voltage Output PCOS35 NSIN Analog Voltage Output NSIN36 PSIN Analog Voltage Output PSIN37 LED LED High-Side Current Source38 VDDA + 4 V ... +5.5 V Supply Voltage

BP 2 Backside paddle

IC top marking: <P-CODE> = product code, <A-CODE> = assembly code (subject to changes);Grounding unused inputs (10 kΩ to GNDA) is recommended, especially for pins DIR, TPS, TNS, TPC, and TNC.1 Pin numbers marked n.c. are not connected.2 Connecting the backside paddle is recommended by a single link to GNDA. A current flow across the paddle is not permissible.


Rev D1, /45

PAD LAYOUT

3310

500

300

250

110

80

110

5480

80

200

350

40

200

DA4V DA4N

DA3V DA3N

DA2V DA2N

DA1VP DA1NP

DA1VN DA1NN

DA5V DA5N

DA6V DA6N

DA7V DA7N

DA8V DA8N

DA9V DA9N

DA10V DA10N

DPSIN

DNSINDNCOS DNSIN

DPCOS

1810

PAD FUNCTIONSNo. Name Function

1 GND I/O Ports Ground2 VDD + 3 V ... +5.5 V I/O Ports Supply Voltage3 SCLK SPI Clock Input4 MOSI SPI Data Input5 MISO SPI Data Output6 CS SPI Chip Select Input7 TNC Test Input NCOS /

Parallel Output Bit 158 TNS Test Input NSIN /

Parallel Output Bit 149 DIR Code Inversion Input /

Parallel Output Bit 1310 NSL Shift Register Load Input (active low) /

Parallel Output Bit 1211 DIN Shift Register Data Input /

Parallel Output Bit 1112 DOUT Shift Register Data Output /

Parallel Output Bit 1013 CLK Shift Register Clock Input /

Parallel Output Bit 914 GA Gray Code Output A (MSB) /

Parallel Output Bit 815 GB Gray Code Output B (MSB-1) /

Parallel Output Bit 716 XJD Adjustment Signal /

Parallel Output Bit 617 POK Power OK Indication/

Parallel Output Bit 518 INCZ Incremental Output Z /

Parallel Output Bit 419 INCB Incremental Output B /

Parallel Output Bit 320 INCA Incremental Output A /

Parallel Output Bit 221 ERR Error Message Output (active high)22 TPS Test Input PSIN /

Parallel Output Bit 123 TPC Test Input PCOS /

Parallel Output Bit 024 NCOS Analog Voltage Output NCOS25 PCOS Analog Voltage Output PCOS26 NSIN Analog Voltage Output NSIN27 PSIN Analog Voltage Output PSIN28 LED LED High-Side Current Source29 VDDA + 4 V ... +5.5 V Supply Voltage30 GNDA Ground

Grounding unused inputs (10 kΩ to GNDA) is recommended, especially for pins DIR, TPS, TNS, TPC, and TNC.


Rev D1, /45

PACKAGE DIMENSIONS oQFN38-7x5

7

5.38

5

1.93

G4

TOP

5.65

3.65

0.230.50 0.40

BOTTOM

0.90

±0.10SIDE

0.300.50

5.65

3.65

6.90

4.90

R0.15

0.70

RECOMMENDED PCB-FOOTPRINT

drd_lnb-oqfn38-1_pack_1, 8:1

All dimensions given in mm. Tolerances of form and position according to JEDEC MO-220.Positional tolerance of reticle pattern: ±90μm / ±1° (with respect to center of backside pad).G4: radius of chip center (refer to the relevant encoder disc and code description).Maximum molding excess +20μm / -75μm versus surface of glass/reticle.


Rev D1, /45

ABSOLUTE MAXIMUM RATINGS

These ratings do not imply permissible operating conditions; functional operation is not guaranteed.Exceeding these ratings may damage the device.Item Symbol Parameter Conditions UnitNo. Min. Max.G001 VDDA Voltage at VDDA -0.3 6 VG002 VDD Voltage at VDD -0.3 VDDA+0.3 VG003 V(GND) Voltage at GND -0.3 0.3 VG004 V() Voltage at LED, PCOS, NCOS, PSIN,

NSIN, TPC, TNC, TPS, TNS-0.3 VDDA+0.3 V

G005 V() Voltage at INCA, INCB, INCZ, ERR,DIR, CLK, DOUT, DIN, NSL, CS, MOSI,MISO, SCK, POK, XJD, GA, GB

-0.3 VDD+0.3 V

G006 I(VDDA) Current in VDDA -100 100 mAG007 I(VDD) Current in VDD -50 50 mAG008 I(GND) Current in GND -20 20 mAG009 I(LED) Current in LED -100 20 mAG010 I() Current in INCA, INCB, INCZ, ERR,

DIR, CLK, DOUT, DIN, NSL, CS, MOSI,MISO, SCK, POK, XJD, GA, GB, TPC,TNC, TPS, TNS

-35 35 mA

G011 I() Current in PCOS, NCOS, PSIN, NSIN -35 35 mAG012 Vd() ESD Susceptibility at all pins HBM 100pF discharged through 1.5 kΩ 2 kVG013 Tj Junction Temperature -40 125 °CG014 Ts Chip Storage Temperature -40 125 °C

THERMAL DATA

Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GNDItem Symbol Parameter Conditions UnitNo. Min. Typ. Max.

T01 Ta Operating Ambient Temperature Range packages oBGA LNB2C, oQFN38-7x5 -40 110 °C

T02 Ts Permissible Storage TemperatureRange

packages oBGA LNB2C, oQFN38-7x5 -40 110 °C

T03 Tpk Soldering Peak Temperature package oBGA LSH2C

tpk < 20 s, convection reflow 245 °Ctpk < 20 s, vapor phase soldering 230 °C

TOL (time on label) 8 h;Please refer to customer information file No. 7for details.

T04 Tpk Soldering Peak Temperature package oQFN38-7x5

tpk < 20 s, convection reflow 245 °Ctpk < 20 s, vapor phase soldering 230 °C

MSL 5A (max. floor life 24 h at 30 °C and60% RH);Please refer to customer information file No. 7for details.

All voltages are referenced to ground (GNDA) unless otherwise stated.All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.


Rev D1, /45

ELECTRICAL CHARACTERISTICS

Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.Item Symbol Parameter Conditions UnitNo. Min. Typ. Max.Total Device001 VDDA Permissible Supply Voltage 4 5 5.5 V002 VDD Permissible I/O Supply Voltage VDD≤ VDDA 3 5 5.5 V003 VDDA,

VDDPermissible Supply Voltage Rip-ple

at 150 kHz 10 mV

004 I(VDDA),I(VDD)

Supply Current in VDDA andVDD (sum)

without currents I(LED) and I(ERR), Tj = 27 °C 25 40 mA

005 Vcz()hi Clamp Voltage hi at all Pins I() = 4 mA 11 V006 Vc()hi Clamp Voltage hi at

CLK, DIN, NSL, INCA, INCB,INCZ, ERR, DIR, MISO, DOUT,POK, XJD, GA, GB, TPS, TNS,TPC, TNC

Vc()hi = V() − V(VDD),I() = 4 mA

0.3 1.2 V

007 Vc()hi Clamp Voltage hi atCS, MOSI, SCK

Vc()hi = V() − V(VDD),I() = 4 mA

1.2 2.2 V

008 Vc()lo Clamp Voltage lo at all Pins I() = -4 mA -1.2 -0.3 V009 CVDDA,

CVDDRequired Backup Capacitors atVDDA, VDD

placed near by pin, recommended low ESR 1 µF

Photodiodes101 Se(λ) Spectral Application Range Se(λ) = 0.25 x S(λ)max 400 950 nm102 S(λ)max Spectral Sensitivity λ= 690 nm 0.45 A/W103 S(λ) Spectral Sensitivity λ= 850 nm 0.30 A/W104 Aph() Radiant Sensitive Area DPSIN,

DNSIN, DPCOS, DNCOS0.5 mm x 0.25 mm 0.125 mm2

105 Aph() Radiant Sensitive Area DigitalDA1VP, DA1VN, DA1NP, DA1NN,DA2V ... DA10V, DA2N ... DA10N

0.35 mm x 0.2 mm 0.07 mm2

Photocurrent Amplifier201 Iph() Permissible Photocurrent

Operating Range0 200 nA

202 Z() Equivalent Transimpedance Gain Z() = Vout() / Iph() 1.8 3.0 4.2 MΩ

203 ∆Z()pn Transimpedance Gain Matchingof an Amplifier Pair

P-channel versus corresponding N-channel -0.2 0.2 %

204 fhc() Upper Cut-off Frequency (-3 dB) without LED current control 120 300 500 kHz205 VR() Ratio of Reference Voltage Dig-

ital Tracks (Vcomp) to Sum ofDigital Track 1

VR() = VcompVA1VP + VA1VN + VA1NP + VA1NN 0.25

206 Hys() Hysteresis Digital Tracks 5 15 25 mV207 GR() Coarse Gain Range Analog Track GR = 0x00 0.9 1 1.1

GR = 0x01 1.2 1.33 1.45GR = 0x02 1.45 1.6 1.75GR = 0x03 1.8 2 2.2

208 Vref Reference Voltage of Photocur-rent Amplifiers

0.6 0.8 1 V

209 ∆Vd()sc Analog Track Dark Signal Voltageversus Vref

∆Vd()sc = V() - Vref -20 20 mV

210 ∆Vd()dig Digital Tracks Dark Signal Volt-age versus Vref

∆Vd()dig = V() - Vref -35 35 mV


Rev D1, /45


Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.Item Symbol Parameter Conditions UnitNo. Min. Typ. Max.Signal Conditioning Sin/Cos301 Gmin Adjustable Minimum Gain GS, GC = 0x00 1302 Gmax Adjustable Maximum Gain GS, GC = 0x3F 2303 ∆Gdiff Differential Gain Calibration

Accuracycalibration range 6 bit -0.5 0.5 LSB

304 Omin Offset Calibration Min OSP, OSN, OCP, OCN = 0x00 45 47.5 50 %VDDA305 Omax Offset Calibration Max OSP, OSN, OCP, OCN = 0x7F 50 52.5 55 %VDDA306 ∆Odiff Differential Offset Calibration

Accuracycalibration range 7 bit 0.01 0.04 0.06 %VDDA

Output Voltage PSIN, NSIN, PCOS, NCOS401 Vdc() DC-Voltage at all Outputs Offset adjusted to VDDA/2 47 50 53 %VDDA402 Vpk() Permissible Signal Amplitude DC level = VDDA/2 0.5 0.6 V403 I()mx Permissible Output Current -1 1 mA404 Ri() Output Resistor I() = -1 . . . 1 mA 75 200 Ω

LED Power Control LED, Error Message ERR501 Imx() Permissible LED Current at LED -100 0 mA502 Iop() LED Current Control Range ERRS (internal) = 0, V(LED) > Vs(LED) -50 -1 mA503 Vs() Saturation Voltage at LED Vs() = VDDA - V(LED); I() = -50 mA 1 V504 tr() Rise Time LED Current I(LED): 0 %→90 % 0.8 1.5 ms505 tset() Settling Time of LED Control

Loopamplitude at PSIN, NSIN, PCOS and NCOSfrom 50 % to 100 % of setpoint

300 µs

506 Vs()hi Saturation Voltage hi at ERR Vs()hi = VDD - V(ERR); 400 mVVDD = 3 . . . 4 V, I() = 1.5 mAVDD = 4 . . . 5.5 V, I() = 2.5 mA

507 Isc()hi Short-Circuit Current hi at ERR -100 -1.5 mA508 Vs()lo Saturation Voltage lo at ERR VDD = 3 . . . 4 V, l() = 1.5 mA 400 mV

VDD = 4 . . . 5.5 V, l() = 2.5 mA509 Isc()lo Short-Circuit Current lo at ERR 1.5 100 mA

Interpolator701 AAabs Absolute Angular Position

Accuracyreferenced to Sin/Cos signal period,HYS = 0x00RESIPO = 11 (5 bit interpolation) ± 7.0 DEGRESIPO = 10 (6 bit interpolation) ± 4.2 DEGRESIPO = 01 (7 bit interpolation) ± 2.8 DEGRESIPO = 00 (8 bit interpolation) ± 1.4 DEG

702 AArel Relative Angular Error referenced to output period T, see Figure 1RESIPO = 11 (5 bit interpolation) 1 %RESIPO = 10 (6 bit interpolation) 2 %RESIPO = 01 (7 bit interpolation) 4 %RESIPO = 00 (8 bit interpolation) 8 %

703 AAhys Angular Hysteresis referenced to output period T, see Figure 1 andTable 25, HYS = 0x00RESIPO = 11 (5 bit interpolation) ± 1.4 DEGRESIPO = 10 (6 bit interpolation) ± 1.4 DEGRESIPO = 01 (7 bit interpolation) ± 1.4 DEGRESIPO = 00 (8 bit interpolation) ± 0.7 DEG

704 tw()hi Duty Cycle referenced to output period T, see Figure 1 50 %705 tAB Phase Shift A versus B referenced to output period T, see Figure 1 25 %706 fmax Maximum Permissible Sin/Cos

FrequencyOSZC = 10RESIPO = 11 (5 bit interpolation) 250 kHzRESIPO = 10 (6 bit interpolation) 226 kHzRESIPO = 01 (7 bit interpolation) 113 kHzRESIPO = 00 (8 bit interpolation) 56.5 kHz

707 tpIPO Propagation Delay Interpolator 1/foipo


Rev D1, /45


Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.Item Symbol Parameter Conditions UnitNo. Min. Typ. Max.

708 tstIPO Startup Time Interpolator OSZC = 10, SELABS = 1, no illumination error,until POSOK = 1RESIPO = 11 (5 bit interpolation):

startup at 14500 rpm 5 µsstartup at standstill 2 µs

RESIPO = 10 (6 bit interpolation):startup at 13200 rpm 600 µsstartup at 12000 rpm 30 µsstartup at standstill 4 µs



FlexCount801 AArelFlex Additional Relative Angular Error

of FlexCountreferenced to output period T, see Figure 1all resolutions 0 25 %all binary resolutions 0 %maximum resolution - 4 25 %

for RESIPO = 00 (8 bit interpolation):RESSUB = 0x01387 (resolution 5 000) 0.48 %RESSUB = 0x04E1F (resolution 20 000) 1.92 %RESSUB = 0x09C3F (resolution 40 000) 3.85 %RESSUB = 0x3FFFB (resolution 218 - 4) 25 %

802 tpFlex Propagation Delay FlexCount additional on top of tpIpo() 4/foflex

803 fmax Maximum Permissible Sin/CosFrequency

OSZC = 10RESIPO = 11 (5 bit interpolation) 250 kHzRESIPO = 10 (6 bit interpolation) 226 kHzRESIPO = 01 (7 bit interpolation) 113 kHzRESIPO = 00 (8 bit interpolation) 56.5 kHz

804 tstFlex Startup Time FlexCount OSZC = 10, SELABS = 0, no illumination error,until POSOK = 1, incl. tstIpoRESIPO = 11 (5 bit interpolation):

startup at 14500 rpm 2.5 msstartup at standstill 1.5 ms

RESIPO = 10 (6 bit interpolation):startup at 13200 rpm 35 msstartup at 12000 rpm 15 msstartup at standstill 2.5 ms

RESIPO = 01 (7 bit interpolation):startup at 6600 rpm 70 msstartup at 6000 rpm 30 msstartup at standstill 5 ms

RESIPO = 00 (8 bit interpolation):startup at 3300 rpm 140 msstartup at 3000 rpm 60 msstartup at standstill 10 ms

Incremental Outputs INCA, INCB, INCZ901 Vs()hi Saturation Voltage hi Vs()hi = VDD - V(); 400 mV

VDD = 3 . . . 4 V, I() = 1.5 mAVDD = 4 . . . 5.5 V, I() = 2.5 mA

902 Isc()hi Short-Circuit Current hi -100 -1.5 mA903 Vs()lo Saturation Voltage lo VDD = 3 . . . 4 V, l() = 1.5 mA 400 mV

VDD = 4 . . . 5.5 V, l() = 2.5 mA904 Isc()lo Short-Circuit Current lo 1.5 100 mA905 tr() Rise Time CL = 30 pF, V(): 10% → 90% VDD 50 ns906 tf() Fall Time CL = 30 pF, V(): 90% → 10% VDD 50 ns


Rev D1, /45


Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.Item Symbol Parameter Conditions UnitNo. Min. Typ. Max.SPI Interface SCK, CS, MISO, MOSIA01 Vs()hi Saturation Voltage hi at MISO Vs()hi = VDD - V(); 400 mV

VDD = 3 . . . 4 V, I() = 1.5 mAVDD = 4 . . . 5.5 V, I() = 2.5 mA

A02 Isc()hi Short-Circuit Current hi at MISO -100 -1.5 mAA03 Vs()lo Saturation Voltage lo at MISO VDD = 3 . . . 4 V, l() = 1.5 mA 400 mV

VDD = 4 . . . 5.5 V, l() = 2.5 mAA04 Isc()lo Short-Circuit Current lo at MISO 1.5 100 mAA05 fin() Permissible Clock Frequency at

SCK10 MHz

A06 Vt()hi Threshold Voltage hi at SCK, CS,MOSI

2 V

A07 Vt()lo Threshold Voltage lo at SCK, CS,MOSI

0.8 V

A08 Vt()hys Hysteresis at SCK, CS, MOSI Vt()hys = Vt()hi - Vt()lo 40 100 mVA09 Ipu() Pull-Up Current at SCK, MOSI V() = 0 . . . VDD - 1 V;

VDD = 3 . . . 4 V -65 -25 -5 µAVDD = 4 . . . 5.5 V -120 -60 -10 µA

A10 Vpu() Pull-Up Voltage at SCK, MOSI Vpu() = VDD - V(); 400 mVVDD = 3 . . . 4 V, I() = -3 µAVDD = 4 . . . 5.5 V, I() = -5 µA

A11 Ipd() Pull-Down Current at CS V() = 1 V . . . VDD;VDD = 3 . . . 4 V 5 25 80 µAVDD = 4 . . . 5.5 V 8 60 150 µA

A12 Vpd() Pull-Down Voltage at CS VDD = 3 . . . 4 V, I() = 3 µA 400 mVVDD = 4 . . . 5.5 V, I() = 5 µA

A13 tP2 Propagation Delay: MISO tristateafter Falling Edge CS

CL = 10 pF, see Figure 2 30 50 ns

A14 tP4 Propagation Delay: MISO Stableafter Clock Edge SCK


Shift Register CLK, NSL, DOUT, DINB01 Vs()hi Saturation Voltage hi at DOUT Vs()hi = VDD - V(); 400 mV

VDD = 3 . . . 4 V, I() = 1.5 mAVDD = 4 . . . 5.5 V, I() = 2.5 mA

B02 Isc()hi Short-Circuit Current hi at DOUT -100 -1.5 mAB03 Vs()lo Saturation Voltage lo at DOUT VDD = 3 . . . 4 V, l() = 1.5 mA 400 mV

VDD = 4 . . . 5.5 V, l() = 2.5 mAB04 Isc()lo Short-Circuit Current lo at DOUT 1.5 100 mAB05 fin() Permissible Clock Frequency at

CLK16 MHz

B06 Vt()hi Threshold Voltage hi at CLK,NSL, DIN

2 V

B07 Vt()lo Threshold Voltage lo at CLK,NSL, DIN

0.8 V

B08 Vt()hys Hysteresis at CLK, NSL, DIN Vt()hys = Vt()hi - Vt()lo 40 100 mVB09 Ipu() Pull-Up Current at CLK, NSL V() = 0 . . . VDD - 1 V;

VDD = 3 . . . 4 V -65 -25 -5 µAVDD = 4 . . . 5.5 V -120 -60 -10 µA

B10 Vpu() Pull-Up Voltage at CLK, NSL Vpu() = VDD - V(); 400 mVVDD = 3 . . . 4 V, I() = -3 µAVDD = 4 . . . 5.5 V, I() = -5 µA

B11 Ipd() Pull-Down Current at DIN V() = 1 V . . . VDD;VDD = 3 . . . 4 V 5 25 80 µAVDD = 4 . . . 5.5 V 8 60 150 µA

B12 Vpd() Pull-Down Voltage at DIN VDD = 3 . . . 4 V, I() = 3 µA 400 mVVDD = 4 . . . 5.5 V, I() = 5 µA


Rev D1, /45


Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.Item Symbol Parameter Conditions UnitNo. Min. Typ. Max.

B13 tp3() Propagation Delay: DOUT IdleState after rising Edge NSL


B14 tp4() Propagation Delay: DOUT stableafter Clock Edge CLK


Parallel Outputs Bit 0 . . . 15 (parameter EPG = 0x1)Pins: TNC, TNS, DIR, NSL, DIN, DOUT, CLK, GA, GB, XJD, POK, INCZ, INCB, INCA, TPS, TPCC01 Vs()hi Saturation Voltage hi Vs()hi = VDD - V(); 400 mV

VDD = 3 . . . 4 V, I() = 1.5 mA,VDD = 4 . . . 5.5 V, I() = 2.5 mA

C02 Isc()hi Short-Circuit Current hi -100 -1.5 mAC03 Vs()lo Saturation Voltage lo VDD = 3 . . . 4 V, l() = 1.5 mA, 400 mV

VDD = 4 . . . 5.5 V, l() = 2.5 mAC04 Isc()lo Short-Circuit Current lo 1.5 100 mAC05 tr() Rise Time CL = 30 pF, V(): 10% → 90% VDD 50 nsC06 tf() Fall Time CL = 30 pF, V(): 90% → 10% VDD 50 ns

Power-On-Reset POKD01 Vs()hi Saturation Voltage hi Vs()hi = VDD - V(); 400 mV

VDD = 3 . . . 4 V, I() = 1.5 mA,VDD = 4 . . . 5.5 V, I() = 2.5 mA

D02 Isc()hi Short-Circuit Current hi -100 -1.5 mAD03 Vs()lo Saturation Voltage lo VDD = 3 . . . 4 V, l() = 1.5 mA, 400 mV

VDD = 4 . . . 5.5 V, l() = 2.5 mAD04 Isc()lo Short-Circuit Current lo 1.5 100 mAD05 VDDAon Turn-on Threshold VDDA,

Power-on-releaseincreasing voltage at VDDA; 3.6 3.8 4.0 VPOK: lo → hi

D06 VDDAoff Turn-off Threshold VDDA,Power-down-reset

decreasing voltage at VDDA; 3.3 3.5 3.7 VEPG = 0, POK: hi → lo

D07 VDDAhys Hysteresis VDDAhys = VDDAon - VDDAoff 0.2 0.3 VCode Inversion Input DIRE01 Vt()hi Threshold Voltage hi 2 VE02 Vt()lo Threshold Voltage lo 0.8 VE03 Vt()hys Hysteresis Vt()hys = Vt()hi - Vt()lo 40 100 mVE04 Ipd() Pull-Down Current V() = 1 V . . . VDD;

VDD = 3 . . . 4 V 5 25 80 µAVDD = 4 . . . 5.5 V 8 60 150 µA

E05 Vpd() Pull-Down Voltage VDD = 3 . . . 4 V, I() = 3 µA 400 mVVDD = 4 . . . 5.5 V, I() = 5 µA


Rev D1, /45


Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.Item Symbol Parameter Conditions UnitNo. Min. Typ. Max.OscillatorF01 foipo Oscillator Frequency Interpolator OSZC = 00 13.0 16.5 20.0 MHz

OSZC = 01 13.5 17.5 21.5 MHzOSZC = 10 14.5 19.0 23.0 MHzOSZC = 11 15.0 20.0 24.0 MHz

F02 foflex Oscillator Frequency FlexCount OSZC = 00 14.0 17.0 20.0 MHzOSZC = 01 14.5 18.0 21.5 MHzOSZC = 10 15.5 19.5 23.0 MHzOSZC = 11 16.0 20.5 24.0 MHz

^^êÉä ^^êÉä

q

íïÜá

í^_

Figure 1: Definition of relative angle error


Rev D1, /45

OPERATING REQUIREMENTS: SPI Interface

Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.Item Symbol Parameter Conditions UnitNo. Min. Max.

I001 tC1 Permissible Clock Period see Elec. Char. No.: A05 1/fin()I002 tW1 Wait Time:

between CS hi→ lo and CS lo→hi500 ns

I003 tS1 Setup Time:CS hi before SCK lo→hi

50 ns

I004 tP1 Propagation Delay:MISO stable after CS lo→hi

CL = 10 pF 50 ns

I005 tP2 Propagation Delay:MISO tristate after CS hi→ lo

CL = 10 pF Elec. Char. No.: A13

I006 tH1 Hold Time:CS hi after SCK lo→hi

valid for SPI mode 3 50 ns

I007 tS2 Setup Time:MOSI stable before SCK lo→hi

50 ns

I008 tH2 Hold Time:MOSI stable after SCK lo→hi

50 ns

I009 tP3 Propagation Delay:MISO stable after MOSI change

mode: repeating MOSI on MISO, CL = 10 pF 50 ns

I010 tP4 Propagation Delay:MISO stable after clock edge SCK

mode: sending data MISO, CL = 10 pF Elec. Char. No.: A14

I011 tW2 Wait Time:SCK stable after CS hi→ lo

500 ns

I012 tH3 Hold Time:CS hi after SCK hi→ lo

valid for SPI mode 0 50 ns

I013 tL1 Clock Signal lo Level Duration 50 nsI014 tL2 Clock Signal hi Level Duration 50 ns

SCK

CS

MOSI

MISO

tW1

tS1 tS2 tH2 tC1

tP1 tP2tP3 tP4

MSB in LSB in

MSB in LSB in MSB out LSB out

tH1

tH3 tW2

tL1 tL2

Figure 2: SPI interface timing


Rev D1, /45

OPERATING REQUIREMENTS: Shift Register

Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.Item Symbol Parameter Conditions UnitNo. Min. Max.

I101 tC1 Permissible Clock Period see Elec. Char. No.: B05 1/fin()I102 tW1 Wait Time Load Signal:

NSL low after CLK lo → hi30 ns

I103 tP1 Propagation Delay:DOUT (idle state) after NSL lo→hi

CL = 10 pF Elec. Char. No.: B13

I104 tP2 Propagation Delay:DOUT stable after CLK lo→hi

CL = 10 pF Elec. Char. No.: B14

I105 tS1 Setup Time:DIN stable before CLK lo→hi

30 ns

I106 tH1 Hold Time:DIN stable after CLK lo→hi

30 ns

I107 tW2 Wait Time:NSL high before request of positiondata (CLK hi → lo)

100 ns

I108 tL1 Clock Signal lo Level Duration 30 nsI109 tL2 Clock Signal hi Level Duration 30 ns

CLK

NSL

DOUT

DIN

tW2

tS1 tH1tP2

tC1

tP1

tW1tL1 tL2

Figure 3: Shift register timing


Rev D1, /45

CONFIGURATION PARAMETERS

Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 32EPG: Operating mode

Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . Page 26GR: Gain rangeGS: Sine gainOSP: PSIN offsetOSN: NSIN offsetGC: Cosine gainOCP: PCOS offsetOCN: NCOS offset

LED Power Control . . . . . . . . . . . . . . . . . . . . . . . . Page 39LCMOD: LED power control modeLCTYP: LED power control typeLCSET(5:0): LED power control setpoint

Interpolator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 28RESIPO: Interpolator resolutionHYS: Interpolator hysteresisENIPO: Interpolator enableNENF: Interpolator filter disable

Incremental Output . . . . . . . . . . . . . . . . . . . . . . . . Page 33INC: Incremental output resolutionTRIABZ: Incremental output tristate (hi-z)

FlexCount® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 29NENFLEX: FlexCount enable/disableSELABS: Select maximum or FlexCount resolution

for absolute outputs

RESSUB: FlexCount resolution – 1STOPFLEX: Stop/reset FlexCountPOSOK: FlexCount position validNOUTLO: Set FlexCount outputs lowINVA: Invert INCA outputINVB: Invert INCB outputINVZ: Invert INCZ outputZPOS: INCZ output positionZ90: INCZ output pulse width

Shift Register Output . . . . . . . . . . . . . . . . . . . . . . Page 35

NENSHIFT: Shift register enableNGRAY: Shift register output data formatRNF: Shift register idle outputSRC: Output data lengthDIR: Shift register code inversion

Parallel Output Mode . . . . . . . . . . . . . . . . . . . . . . Page 37EPG: Operating mode

Alarm Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 39ERRS: LED illumination error (internal)ERRP: Parity error (internal)

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 40OSZC: Oscillator adjustment

Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 41TA: Test modesTMUX: Test signal multiplexer


Rev D1, /45

CONFIGURING THE iC-LNB

REGISTER MAP (RAM)Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Signal calibration0x00 P00 NENSHIFT GS(5:0)0x01 P01 LCMOD GC(5:0)0x02 P02 OSP(6:0)0x03 P03 OSN(6:0)0x04 P04 OCP(6:0)0x05 P05 OCN(6:0)

LED Power Control0x06 P06 LCTYP LCSET(5:0)

Output Configuration0x07 P07 NGRAY DIR EPG OSZC(1:0) GR(1:0)0x08 P08 INC(2:0) RNF SRC(2:0)

Test Functions0x09 P09 NENF TA(1:0) TMUX(3:0)

FlexCount0x0A P0A 0 0 0 0 HYS(2:0)0x0B P0B INVA INVB INVZ TRIABZ SELABS NENFLEX 00x0C P0C ZPOS(6:0)0x0D P0D ZPOS(13:7)0x0E P0E RESIPO(1:0) Z90 ZPOS(17:14)0x0F P0F RESSUB(6:0)0x10 P10 RESSUB(13:7)0x11 P11 NOUTLO STOPFLEX ENIPO RESSUB(17:14)

Status (read only)0x12 CHIPVERSION(3:0) 0 ERRP ERRS POSOK

Table 6: Register layout

Address RangeThe addresses available through the SPI interfacerange from 0x00 to 0x12. As only the lower five bitsof the address byte are evaluated, addresses greaterthan 0x1F are mapped back to address range 0x00 –0x12. It is recommended not to use addresses greaterthan 0x12 with the iC-LNB.

RAM Monitoring (parity check)The configuration registers in the internal RAM are con-stantly monitored by a parity check. Bit 7 of each ad-dress is the parity bit (P00 – P11) which must be pro-grammed to give an even number of ones in the byte.An odd number of ones in a byte indicates a parity error(ERRP) which sets the ERRP bit in the status register(0x12 bit 2) and activates the ERR output. See ALARMOUTPUT on page 39 for more information.

Chip Version

Chip Version Addr. 0x12; bit 7:4Value Description0 V1 U22...15 Reserved

Table 7: Chip Version


Rev D1, /45

Reset ValuesAfter power-on, the registers are initialized as follows:

Address ResetValue

Description

0x00-0x01 0xA0 Gain (GS, GC) = 1.408Shift register (NENSHIFT) = enabledLED control behavior (LCMOD) = 0

0x02-0x05 0xC0 Offset (OSP, OSN, OCP, OCN) =0.5004*VDDA

0x06 0x60 LED control mode (LCTYP) = sumcontrol, Set point (LCSET) = 0.23 V

0x07 0x09 Serial output format (NGRAY) = GRAY,Direction (DIR) = CW,EPG = interface mode,Oscillator (OSZC) = 16MHz,Gain range (GR) = 1.33

0x08 0x18 Interpolator factor (INC) = x2,Idle state DOUT (RNF) = ’1’,Shift register (SRC) = 18 bits

0x09-0x0A 0x00 Test functions = 0,Hysteresis Interpolator (HYS) = 1.4°

0x0B 0x8E ABZ outputs (INVA/B/Z) = not inverted,ABZ outputs (TRIABZ) = tri-state, Shiftregister (SELABS) = max. resolution,FlexCount (NENFLEX) = disabled

0x0C-0x10 0x00 FlexCount parameters = 00x11 0xA0 FlexCount:

Outputs (NOUTLO) = low,Reset (STOPFLEX) = stopped,Interpolator (ENIPO) = disabled

Table 8: Register Reset Values (RAM)

Programming SequenceAfter the iC-LNB has powered up (pin POK high), itmust be configured through the SPI interface. A micro-controller with an integrated EEPROM and SPI masteris usually used for this purpose. Depending on the re-quired application functionality, the parameters must bewritten in a specific order (see Figure 4 on page 20).

If the iC-LNB is to be used without FlexCount, only therequired interpolator resolution (RESIPO) and the in-cremental output resolution (INC) need to be set andthe interpolator enabled (ENIPO = 1). Enable the INCA,INCB, and INCZ output drivers by resetting TRIABZ (0).

If the iC-LNB is to be used with FlexCount, the INCA,INCB, and INCZ outputs can be set low (NOUTLO =0 and TRIABZ = 0) or to tristate (TRIABZ = 1) duringconfiguration. After configuring all parameters, enableFlexCount (STOPFLEX = 0). After the current positionhas been found (POSOK = 1), enable the INCA, INCB,and INCZ outputs (NOUTLO = 1 and TRIABZ = 0).

As shown in Figure 4, it is recommended to implementa timeout of 30ms (up to 1000 RPM) when checkingfor POSOK. This avoids a potential infinite loop thatcould happen due to glitches or communication errors.If POSOK is still 0 after some number of timeouts (typi-cally 5), a configuration error can be assumed.


Rev D1, /45

Power On(POK = 1)

enableFlexCount?

NoYes

write address 0x0ERESIPO

write address 0x11ENIPO = 1

write address 0x0BTRIABZ = 0

write addresses 0x0A – 0x100x0B: TRIABZ = 1, SELABS=0

write address 0x11NOUTLO = 1, ENIPO = 1,

RESSUB

read address 0x12POSOK = 1?

No

Yes

write address 0x0BTRIABZ = 0

configurationfinished

INCA, INCB, INCZtristate or low?

write addresses 0x0A – 0x100x0B: TRIABZ = 0, SELABS=0

write address 0x11NOUTLO = 1

read address 0x12POSOK = 1?

tristate

low

write address 0x11NOUTLO = 0, ENIPO = 1,

RESSUB

write addresses 0x00 - 0x09

No

Yes

write address 0x11STOPFLEX = 0


POSOKtimeout

POSOKtimeouttimeout count + 1;

timeout count <= 5

Yes

No

configurationerror


ENIPO = 0

Wait > tstIPO

orWait until POSOK =1

enableSELABS?

No

Yes

write address 0x0BSELABS = 1

Figure 4: Typical Configuration Sequence


Rev D1, /45

SPI INTERFACE

General Protocol DescriptionThe SPI interface in the iC-LNB is implemented as anSPI slave and supports SPI modes 0 and 3, meaningthat the idle state of SCLK can be 0 or 1. Data is alwaysaccepted on the rising edge of SCLK and the MISO pin

is set to tristate if the iC-LNB is not selected by themaster (CS=0). A rising edge on CS initiates an SPItransaction causing the MOSI signal to be fed throughto MISO. Data is sent byte by byte with the MSB (mostsignificant bit) first.

SCLK

MOSI

MISO

CS

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

Figure 5: Typical SPI Transaction (Register Read)

Figure 5 shows a single Register Read transaction be-tween the SPI master and a single iC-LNB (SPI slave).SPI data transactions occur as follows:

1. Master initiates a transaction with a rising edgeon the chip select input (CS).

2. iC-LNB feeds MOSI through to MISO.3. Master sends opcode and address bits on MOSI;

this data is fed through to MISO.4. iC-LNB transmits the data from the specified ad-

dress to the master on MISO.5. Master ends the transaction with a falling edge

on CS.6. iC-LNB switches its MISO output to tristate.

See Bussing and Chaining Multiple iC-LNBs on page25 for more information on multiple-device applications.

OpcodesEach SPI transaction begins with a 1-byte opcode (op-eration code or command) sent by the SPI master.As shown in Table 9, the opcode determines whetherconfiguration (register) or sensor data (position) is ac-cessed.

SPI OpcodesCode Opcode0xB0 Activate0xA6 Position Read0xF5 Position Data (SDAD) Status0x8A Register Read (continuous)0xCF Register Write (continuous)0xAD Register Status

Table 9: SPI Opcodes

These opcodes are explained following.

ActivateThe Activate opcode (0xB0) turns the register and sen-sor data channels in the iC-LNB on and off individually.This command causes the iC-LNB to reset its RA (reg-ister data channel) and PA (Sensor data channel) bits,turning both channels off, and resets the Fail, Valid,Busy, and Dismiss bits in the SPI Status byte (see Ta-ble 15). The RA and PA bits in the data byte followingthe opcode then activate one or both channels for sub-sequent transactions.

With only one iC-LNB slave (one register and one sen-sor data channel), the RA and PA bits are bits 1 and0 respectively in the data byte following the Activatecommand as shown in Figure 6.

SCLK

MOSI

MISO

CS

1 0

RACTIVE / PACTIVE vector

0 0 0 0 RA PAOP

OP

8 cycles

1 0 0 0 0 00 0

Figure 6: RA and PA (one slave)

If RA = 1, the register data channel is activated andcommunication with iC-LNB registers is possible. IfPA = 1, the sensor data channel is activated and po-sition (angle) information can be read. Both channelscan be active at the same time. After power-on (POK =1), the register data channel is enabled (RA = 1) andthe sensor data channel is disabled (PA = 0).

Note that it is not possible for the SPI master to readback the state of the RA or PA bits to determine whichdata channels are active in the iC-LNB. It is only pos-sible for it to turn both channels off and then activateeach or both as required using the Activate command.


Rev D1, /45

If RA = 1, opcodes Register Read, Register Write, andRegister Status operate normally, as explained below.If RA = 0, these commands are not executed and, ifattempted, set the Error bit in the SPI Status byte (Ta-ble 15).

Likewise, if PA = 1, the Position Read opcode operatesnormally, as explained below. If PA = 0, this commandis not executed and, if attempted, sets the Error bit inthe SPI Status byte (Table 15). All of these commands,however, are still passed through to MISO.

Position ReadThe Position Read command (0xA6) is used to read theabsolute position data from the iC-LNB.

SD1

8 cycles

SCLK

MOSI

MISO

CS

OP

OP

SD2 SD3

REQ

Figure 7: Position Read

As shown in Figure 7, the iC-LNB latches its positiondata on the first rising edge of SCLK when CS is high(REQ). The position data shift register then clocks outthe latched position value on subsequent clock cycles(bytes SD1 - SD3). Position data is available in binaryor Gray code.

NGRAY Address 0x07; bit 6Value Data Format0 Gray Code1 Binary

Table 10: SPI Position Output Data Format

The sensor data channel must be activated (PA = 1) forproper operation of this command, otherwise the Errorbit in the SPI Status byte is set. If invalid data is de-tected in the shift register, the Error bit in the SPI Statusbyte (Table 15) is set and SD1 = SD2 = SD3 = 0x00.

The length of the SPI shift register and the number ofposition bits used is determined by parameter SRC, asshown in Table 11.

SRC Address 0x08; bits 2:0Value SPI Shift Reg. Length Number of Bits Used0 24 bits 181 24 bits 172 16 bits 163 16 bits 154 16 bits 145 16 bits 136 16 bits 137 16 bits 12

Table 11: SPI Output Data Length

If SRC≥2, only SD1 and SD2 are used. If SRC < 2,SD1, SD2, and SD3 are used.

SPI position is shifted out MSB first and left-justified. Ifthe SPI output data length is greater than the numberof bits used (SRC =/ 2), the unused LSBs are zero. Forexample, if SRC = 1, the shift register outputs the 17-bitposition value followed by seven zeros. In this case,SD3 bits [6:0] are zero.

Note that SRC is also used to set the length of theposition output shift register (Table 49). However, theposition output shift register is not always the samelength as the SPI shift register. Also, the position out-put shift register outputs right-justified position datawhereas the SPI position data is left-justified.

If FlexCount is selected (SELABS = 0), the number ofvalid position bits is determined by the FlexCount reso-lution, specified by parameter RESSUB. Also, if Flex-Count is enabled and a non-binary resolution is used(RESSUB + 1 is not an integer power of 2), the absoluteposition is a value between two non-zero numbers. SeeFLEXCOUNT® on page 29 for more information on theabsolute position numeric formats.

If FlexCount is not selected (SELABS = 1), the numberof valid position bits is determined by the interpolatorresolution (RESIPO), as shown in Table 12.

RESIPO Address 0x0E; bits 6:5Value Interpolator resolution Valid Position Bits0 8 bit 181 7 bit 172 6 bit 163 5 bit 15

Table 12: Valid Position Bits

Position Data (SDAD) StatusThe status of position data can be checked with theSDAD Status command (0xF5). The command causes:


Rev D1, /45

1. All slaves activated via PACTIVE to switch theirSVALID and SFAIL registers between MOSI andMISO.

2. The next request for sensor data started with thefirst rising edge at SCLK of the next SPI commu-nication is ignored by the slave.

SVSF 0-3

8 cycles

SCLK

MOSI

MISO

CS

OP

OP

SVSF 4-7 ...

Latch

Figure 8: SDAD status

The master can check the validity of the position dataand then read out this data with command SDADtransmission. In iC-LNB, SVALID (SV) is identicalto POSOK and SFAIL (SF) is the logical complement ofPOSOK.

SVALIDValue Description0 Position data invalid (POSOK = 0)1 Position data valid (POSOK = 1)

Table 13: SVALID

SFAILValue Description0 Position data request okay (POSOK = 1)1 Position data request failed (POSOK = 0)

Table 14: SFAIL

If only one slave is connected, the correspondingSVALID (SV0) and SFAIL (SF0) bits are placed at bitpositions 7 and 6 in the SVALID byte.

SCLK

MOSI

MISO

CS

0 0 0 0 0 0 0 0OP

OP 0 0 0 0 0 0SV0 SF0

Latch

SVALID-vector8 cycles

MOSI

MISO

OP

OP

1 Sl

ave

2 Sl

aves 0 0 0 0 0 0 0 0

SV1 SF1 0 0 0 0SV0 SF0

Figure 9: SDAD status (Example with one and twoslaves (daisy chain))

SDAD status

SDAD-transmission

REGISTERstatus/data

errorhandling

(ERROR == 1)?yes

1

2

SF == 1?

nono

yes

yes

SV == 1?

disable followingsensor data request*)

enable sensordata requests*)

*) on the first rising edge at SCLK of the next SPI communication

enable sensordata requests*)

Figure 10: Example sequence of the commandsSDAD Status/SDAD-transmission

Figure 10 shows the interaction of the two commandsSDAD Status and SDAD transmission. The positiondata communication starts with the command SDADStatus (1). The first SDAD Status requests new data.If SFAIL is not set, subsequent SDAD Status com-mands are used to check for the data to be ready totransmit (no new position data requests are issued).

If SFAIL is set, requesting new position data on the firstrising edge of SCLK of the next SPI communication isenabled. If the position data is ready as indicated bySVALID, the SDAD-transmission (2) command canbe executed to read out the position data. Followingthis, the command REGISTER status/data should beexecuted to detect an unsuccessful SPI communica-tion.


Rev D1, /45

Register ReadThe Register Read command (0x8A) reads data froma contiguous block of one or more RAM addressesstarting at a specified address.

ADR

8 cycles

SCLK

MOSI

MISO

CS

OP

OP DATA1 ...DATA2ADR

Figure 11: Register Read

The master transmits the read register opcode (0x8A)followed by the starting address of the block of ad-dresses to read (ADR) on MOSI. The iC-LNB immedi-ately outputs the opcode and address on MISO followedby the data from the register at address ADR (DATA1).As long as CS stays active (high), data from the thenext register (address ADR + 1) is then output (DATA2).Data from subsequent registers continues to be outputas long as CS remains high.

The register data channel must be activated (RA = 1)for proper operation of this command, otherwise theError bit in the SPI Status byte is set. If an error occursduring a register read (invalid address, invalid data,etc.), the Fail bit in the SPI Status byte is set, the ad-dress counter is no longer incremented, and the datareturned is invalid. See Table 15 on page 24 for moreinformation.

Register WriteThe Register Write command (0xCF) writes data to acontiguous block of one or more RAM addresses start-ing at a specified address.

ADR

8 cycles

SCLK

MOSI

MISO

CS

OP

OP

DATA1 DATA2 ...

ADR DATA1 DATA2 ...

Figure 12: Write to REGISTER (cont.)

The master transmits the write register opcode (0xCF)followed by the starting address of the block of ad-dresses to write (ADR), followed by the data to write tothe register at address ADR (DATA1), the data to writeto the address at ADR + 1 (DATA2), etc. on MOSI. TheiC-LNB immediately outputs the MOSI bits on MISO.

Data continues to be written to subsequent registers aslong as CS stays active (high).

The register data channel must be activated (RA = 1) forproper operation of this command, otherwise the Errorbit in the SPI Status byte is set. If an error occurs duringa register write (invalid address, invalid data, etc.), theFail bit in the SPI Status byte is set, the address counteris no longer incremented, and the data is not written.See Table 15 on page 24 for more information.

Register StatusThe Register Status command (0xAD) returns the SPIStatus byte which indicates the status of the last registertransaction or data transmission.

STATUS

8 cycles

SCLK

MOSI

MISO

CS

OP

OP

DATA

Figure 13: Register Status

As shown in Figure 13, the SPI Status byte is re-turned immediately following the Register Status op-code (STATUS) and is followed by an undefined databyte (DATA).

Table 15 shows the SPI Status byte bits.

STATUSBit Name Description7 Error Invalid opcode6:4 – Reserved3 Dismiss Illegal Address2 Fail Data request failed1 Busy Slave busy0 Valid Position data valid

Table 15: SPI Status Byte

Status bits are updated with every register access, ex-cept Error, which indicates the status of the last com-mand (opcode).


Rev D1, /45

Bussing and Chaining Multiple iC-LNBsMultiple iC-LNBs can be bussed or chained to a singleSPI master. Figure 14 shows two iC-LNBs in a bussedconfiguration.

iC-LNB

(0)MOSI

iC-LNB

(1)MISO

MISO

SCK

CS1

MISO

MOSI

MOSI

CS

SCK

CS

SCKSPI

Master

CS0

Figure 14: Bussing Multiple iC-LNBs

In this configuration, the SPI master communicates witheach iC-LNB individually by activating the appropriatechip select (CS) output.

Figure 15 shows two iC-LNBs in a chained configura-tion.

iC-LNB

(1)MOSI

iC-LNB

(0)MISO

MISOSCKCS

MISOMOSI MOSI

CS

SCK

CS

SCKSPI

Master

Figure 15: Chaining Multiple iC-LNBs

In this configuration, the MISO output of each iC-LNBis chained to the MOSI input of the next device in thechain. The SPI master must activate the desired chan-nel(s) in a specific slave device to communicate with it.

The required RA and PA bits for each slave are packedinto the bytes following the Activate opcode, as shownin Figure 16.

RAPA 0-3

8 cycles

SCLK

MOSI

MISO

CS

OP

OP RAPA 4-7 ...

Figure 16: Activate Command For Multiple Slaves

For example, Figure 17 shows MOSI and MISO for anActivate command for one and two chained slaves.

0

SCLK

MOSI

MISO

CS

1 0

RACTIVE/PACTIVE-vector

0 0 0 0 RA0 PA0OP

OP

8 cycles

1 0 0 0 0 00 0

MOSI

MISO

1 0 0 0 RA0 PA0 RA1 PA1OP

OP 10 0 0 00 0

1 Sl

ave

2 Sl

aves

Figure 17: Activate Command For Two Slaves

Each slave outputs two zeros on MISO followed by thesix most significant bits of MOSI and reads its RA andPA bits from bits 1 and 0 respectively of the RA/PAvector on MOSI. In this way, the RA/PA bits for the nextslave in the chain are moved into bits 1 and 0 for thenext slave.

The SPI master can determine the number of data chan-nels in the chain by sending a 1 as bit 7 after the opcodein the Activate command. It then counts the number ofzeros it receives on MISO before receiving the 1 back.The number of zeroes preceding the returned 1 is thenumber of data channels in the chain.


Rev D1, /45

SIGNAL CONDITIONING

The iC-LNB provides seven parameters for condition-ing and calibrating the signals from the sine and cosinephotodiodes. These allow the elimination of offsets andthe calibration and equalization of gain between the twochannels. The sin/cos signal path and the adjustmentparameters are shown in Figure 18.

-+

-+

+-

+-

+-

+-

-+

+-

+-

+-+

-

+-

-+

+-

+-

+-

DNCOS

DPCOSGC

OCN

GC

OSP

GS

GS

GR

OCP

GR

GR

GC

OSN

GS

GS

GR

GC

DPSIN

DNSIN

VREFNC

VREFPC

VREFPS

VREFNS

3Meg

3Meg

3Meg

3Meg

PCOS

VDDA

NCOS

VDDA

VDDA

VDDA

VNCO

VPCO

3Meg

3Meg

3Meg

3Meg

VNSI

VPSI NSIN

PSIN

OCN

OCP

OSN

OSP

Vref

Vref

Vref

Vref

Vref

Vref

Vref

Vref

+

++

++

+

+

+

+

+

+

+

+

+

+

+

GC

GC

GC

GC

GS

GS

GS

GR

GS

GR

GR

GR

-

-

-

-

-

-

-

-

-

-

-

-

-

-

--NCOS

Vref

-

+

VREFPC

-+

-

VPCO

PSIN

NSIN

+

+

VREFNC

+

+

VPSI

VREFPS

VDDA

PCOS

-

-

Vref

+

-

+

+

VDDA

Vref

Vref

-

+

Vref

+

VDDA

+ VDDA

VREFNS

-

-

-

Vref

-

+

+

-+

-

-

VNSI

-

+

Vref

Vref

VNCO

-

Figure 18: Sin/Cos Signal Path

Test modes (see TEST FUNCTIONS on page 41) allowobserving many of the internal signals of the sin/cos sig-nal path on the NSIN, PSIN, NCOS, and PCOS outputsto assist in calibration.

Gain Range (GR)The gain range for the analog sin/cos signal path is setusing parameter GR (0x07 bits 1:0).

GR Address 0x07; bits 1:0Value Gain Factor0 1.01 1.332 1.63 2.0

Table 16: Gain Range for Sin/Cos Signal Path

A gain range of 1.33 (GR = 1) is recommended for mostapplications.

Sine Gain (GS) and Offsets (OSP and OSN)To calibrate the sine channel gain and offsets, the LEDpower control must be set to sum control (LCTYP = 1).In addition, the internal sine channel calibration sig-nals must be made available on the analog out-puts as shown in Figure 19 by setting TA = 0x1 andTMUX = 0x0D.

PSIN

NSIN

PCOS

NCOS

GNDA

VPx

VNx

VNxVPxTA = 0x1

TMUX = 0x0D or

TMUX = 0x0E

(x = S, C)

Figure 19: Gain and Offset Calibration

To start, set the sine and cosine amplitude (GS and GC)and offset parameters (OSP, OSN, OCP, and OSN) totheir nominal values of 0xA0 and 0xC0 respectively(see Table 8). Adjust the optical power of the LED usingparameter LCSET (0x06 bits 5:0) to set the sine chan-nel amplitudes (VPS and VNS) as close to 500 mV aspossible. Trim the sine channel amplitudes to 500 mVusing parameter GS (0x00 bits 5:0).

GS Address 0x00; bits 5:0Value Gain0x00 1.00x01 1.01... 1+GS·0.0053

1−GS·0.00530x3F 2.0

Table 17: Sine Channel Gain

Next, calibrate the offset of VPS and VNS such thatthe zero level (average) of VPS is equal to VNS, usingparameters OSP (0x02 bits 6:0) and OSN (0x03 bits6:0), respectively. When properly adjusted, the differ-ence between the average DC voltage of VPS and VNSshould be zero.


Rev D1, /45

OSP Address 0x02; bits 6:0Value Offset Value0x00 0.475 · VDDA0x01 0.4754 · VDDA... (0.475 + OSP·0.05

127 ) · VDDA0x7F 0.525 · VDDA

Table 18: Positive Sine (PSIN) Offset

OSN Address 0x03; bits 6:0Value Offset Value0x00 0.475 · VDDA0x01 0.4754 · VDDA... (0.475 + OSP·0.05

127 ) · VDDA0x7F 0.525 · VDDA

Table 19: Negative Sine (NSIN) Offset

Cosine Gain (GC) and Offsets (OCP and OCN)Calibration of the cosine channel gain and offsets is thesame as for the sine channel, except that parameterTMUX must be set to 0x0E instead of 0x0D. This makesthe internal cosine channel calibration signals availableon the analog outputs as shown in Figure 19.

First, trim the cosine channel amplitudes (VPC andVNC) to 500 mV using parameter GC (0x01 bits 5:0).

GC Address 0x01; bits 5:0Value Gain0x00 1.00x01 1.01... 1+GC·0.0053

1−GC·0.00530x3F 2.0

Table 20: Cosine Channel Gain

Next, calibrate the offset of VPC and VNC such thatthe zero level (average) of VPC is equal to VNC using

parameters OCP (0x04 bits 6:0) and/or OCN (0x05 bits6:0), respectively. When properly adjusted, the differ-ence between the average DC voltage of VPC and VNCshould be zero.

OCP Address 0x04; bits 6:0Value Offset Value0x00 0.475 · VDDA0x01 0.4754 · VDDA... (0.475 + OSP·0.05

127 ) · VDDA0x7F 0.525 · VDDA

Table 21: Positive Cosine (PCOS) Offset

OCN Address 0x05; bits 6:0Value Offset Value0x00 0.475 · VDDA0x01 0.4754 · VDDA... (0.475 + OSP·0.05

127 ) · VDDA0x7F 0.525 · VDDA

Table 22: Negative Cosine (NCOS) Offset

After all seven parameters (three gain and four offset)have been calibrated, return the iC-LNB to normal op-eration by turning off test mode (TA = 0x0).

LED Power ControlAfter calibration, it is recommended to enable the

square control function of the LED power control bysetting LCTYP = 0. This keeps the optical power re-ceived by the sine/cosine sensors constant regardlessof changes in temperature and LED aging effects. Af-ter changing to square control, disable the deadbandcontrol by setting LCMOD = 0 and then use parameterLCSET (0x06 bits 5:0) to adjust the sine/cosine ampli-tudes to 500mV. After adjustment, it is recommendedto enable the deadband control by setting LCMOD = 1.See LED POWER CONTROL on page 39 for moreinformation.


Rev D1, /45

INTERPOLATOR

Interpolator ResolutionThe resolution of the internal interpolator determinesthe resolution of the iC-LNB; it is set using parameterRESIPO (0x0E bits 6:5). The interpolator resolutionalso determines the maximum speed (sin/cos input fre-quency) as shown in Table 23.

RESIPO Address 0x0E; bits 6:5Value Interpolator

ResolutioniC-LNBResolution

Max. Speed

00 8 bit 18 bit 3300 rpm01 7 bit 17 bit 6600 rpm10 6 bit 16 bit 13200 rpm11 5 bit 15 bit 14500 rpm

Table 23: Interpolator Resolution

The maximum speeds shown in Table 23 are for anominal interpolator oscillator frequency of 19.0 MHz(OSCZ = 10).

The interpolator must be enabled (ENIPO = 1) for nor-mal operation of the iC-LNB, but must be disabled(ENIPO = 0) when setting or changing its resolution.After setting ENIPO = 1, the interpolator needs thestartup time tstIPO to reach the current position. Thestartup time depends on the interpolator resolution andthe speed at enabling, see spec. item 708.

ENIPO Address 0x11; bit 4Value Description0 Interpolator Disabled1 Interpolator Enabled

Table 24: Interpolator Enable

When disabled, the interpolator output is zero.

Interpolator HysteresisThe hysteresis window of the interpolator is set usingparameter HYS.

HYS Address 0x0A; bits 2:0Value Hysteresis with RESIPO =

00 (8 bit) 01 (7 bit) 10 (6 bit) 11 (5 bit)0x00 +/- 0.7° +/- 1.4° +/- 1.4° +/- 1.4°0x01 +/- 2.1° +/- 1.4° +/- 1.4° +/- 1.4°0x02 +/- 3.5° +/- 2.8° +/- 1.4° +/- 1.4°0x03 +/- 4.9° +/- 4.1° +/- 2.8° +/- 1.4°0x04 +/- 6.3° +/- 5.6° +/- 4.1° +/- 1.4°0x05 +/- 7.7° +/- 7.0° +/- 5.6° +/- 2.8°0x06 +/- 9.1° +/- 8.4° +/- 7.0° +/- 4.1°0x07 +/- 10.5° +/- 9.8° +/- 8.4° +/- 5.6°Note The recommended values are printed in black

Table 25: Hysteresis Depending On Interpolator Reso-lution

Interpolator FilterA low-pass filter is available to reduce noise on theinterpolator inputs. This filter is enabled by parameterNENF.

NENF Address 0x07; bit 6Value Description0 Filter Enabled (recommended)1 Filter Disabled

Table 26: Interpolator Filter

It is recommended to always use the input filter; it hasbeen designed so that it can be used across the entirespeed range.


Rev D1, /45

FLEXCOUNT®

FlexCount® allows the resolution of the incremental,serial, and parallel outputs, as well as the SPI positionto be programmed to any value less than the maximumresolution. FlexCount operates in real time and doesnot introduce any significant latency into the signal path.

Enable/DisableFlexCount is enabled or disabled using parameterNENFLEX.

NENFLEX Address 0x0B; bit 1Value Description0 FlexCount Enabled1 FlexCount Disabled

Table 27: FlexCount Disable

Incremental FlexCount OutputTo use FlexCount for the incremental (ABZ) outputs,parameter INC must be set to INC = 0x07. See IN-CREMENTAL (ABZ) OUTPUTS on page 33 for moreinformation.

Absolute FlexCount OutputFlexCount can also be used for the absolute serial (shiftregister), parallel, and SPI outputs of the iC-LNB as de-termined by parameter SELABS.

SELABS Address 0x0B; bit 2Value Absolute Output Resolution0 FlexCount Resolution1 Maximum Resolution

Table 28: Absolute Output Resolution

FlexCount provides Gray code absolute outputs for allresolutions, however the position data output also al-lows binary absolute output.

If FlexCount is not used for the absolute outputs(SELABS = 1), the resolution of the absolute outputs isthe maximum iC-LNB resolution, as determined by theselected interpolator resolution (RESIPO), as shown inTable 29.

Note that with SELABS = 1 the status POSOK is set to 1if the interpolator position is valid and with SELABS = 0the status POSOK is set to 1 if the FlexCount positionis valid.

RESIPO Address 0x0E; bits 6:5Value Maximum Resolution (Counts per Revolution)3 15 bits (32 768)2 16 bits (65 536)1 17 bits (131 072)0 18 bits (262 144)

Table 29: Maximum Absolute Output Resolution

ResolutionParameter RESSUB determines the FlexCount reso-lution in incremental edges (ABZ outputs) or absolutecounts (serial, parallel, and SPI outputs) per revolution.

RESSUB Addresses 0x0F, 0x10, and 0x11 bits 3:0Value Resolution (edges or counts per revolution)0x3 40x7 8... ...0x07FFF 32 7680x08003 32 772... ... (only with 6, 7 or 8 bit interpolation)0x0FFFF 65 5360x10003 65 540... ... (only with 7 or 8 bit interpolation)0x1FFFF 131 0720x20003 131 076... ... (only with 8 bit interpolation)0x3FFFF 262 144

Table 30: FlexCount Resolution

As shown in Table 30, RESSUB is equal to the desiredresolution minus 1. For example, if an output resolutionof 10 000 edges per revolution for the ABZ outputs isdesired, set RESSUB = 0x0270F (10 000 – 1 = 9999 =0x0270F).

FlexCount resolution must be evenly divisible by four.In addition, maximum FlexCount resolution is limited bythe selected interpolator resolution (RESIPO) as shownin Table 31.

RESIPO Address 0x0E; bits 6:5Value Maximum RESSUB Value3 0x07FFF2 0x0FFFF1 0x1FFFF0 0x3FFFF

Table 31: Maximum FlexCount Resolution


Rev D1, /45

RESSUB is an 18-bit value spread across three reg-isters in the iC-LNB register map, as shown in Table32.

RESSUB RegistersBits Address17:14 0x11 bits 3:013:7 0x10 bits 6:06:0 0x0F bits 6:0

Table 32: RESSUB Addresses

Position offsetiC-LNB’s FlexCount allows a programmable positionoffset to be specified. This offset can be set as a bi-nary value of the maximum internal resolution (whichis dependent on interpolator resolution RESIPO) usingparameter ZPOS (not in the selected FlexCount reso-lution). All values from 0 to 262,143 can be selectedwhen using 8 bit interpolator resolution; with 7 bit reso-lution, the LSB must be 0; with 6 bit resolution, the lasttwo LSBs must be 0, and with 5 bit resolution, the lastthree LSBs must be 0.

ZPOS Addresses 0x0C, 0x0D, 0x0E bits 3:0Value Position offset (binary)0x00000 0 (any interpolation)0x00001 1 (only with 8 bit interpolation)0x00002 2 (only with 7 or 8 bit interpolation)0x00003 3 (only with 8 bit interpolation)0x00004 4 (only with 6, 7 or 8 bit interpolation)... ...0x00008 8 (any interpolation)... ...0x3FFFF 262 143 (only with 8 bit interpolation)

Table 33: FlexCount Position Offset

Absolute Position Numeric FormatsWith binary FlexCount resolutions (those whereRESSUB + 1 is an integer power of two), the Gray codeabsolute position is a number between 0 and RESSUB.Contiguous Gray code values differ by only one bit.Gray code 0 is coincident with the zero position of theencoder disc (falling edge of GA with DIR = 0).

With non-binary resolutions (those where RESSUB + 1is not an integer power of 2), however, the full n-bitGray code cannot be used. In these cases, to preservethe Gray code characteristic of a one bit change be-tween contiguous values, only RESSUB+1 number ofbits from the center of the full n-bit Gray code are used.This means that the Gray code absolute position is avalue between two non-zero numbers.

For example, with a binary FlexCount resolution of 128(RESSUB = 0x0007F), the Gray code absolute positionis a value between 0 (0g0000) and 127 (0g0100’0000)inclusive. However, for the non-binary resolution of100 (RESSUB = 0x00063), the Gray code absolute po-sition is a value between 14 (0g0000’1001) and 113(0g0100’1001) inclusive.

The lowest Gray code value (14 in this case) is calledthe excess and is the value by which the Gray codevalue exceeds the actual absolute position. To deter-mine the true absolute position (a value between 0 and99 for a FlexCount resolution of 100 as in the exam-ple above), the excess must be subtracted from eachconverted Gray code value.

For example, if the absolute position returnedby the iC-LNB is 0g0010’0111, the true abso-lute position is calculated as 58 – 14 = 44 because0g0010’0111 = 0b0011’1010 = 0x3A = 58).

With non-binary resolutions, the excess is calculated as

Excess =2N − (RESSUB + 1)

2

In the above equation, N is the number of bits neces-sary to represent RESSUB. For example, with a Flex-Count resolution of 100, N = 7 since 7 bits are requiredto represent 0x63. For any FlexCount resolution, N iscalculated as

N = INT(log2(RESSUB) + 1)

With non-binary FlexCount resolutions, a Gray codevalue equal to the excess is coincident with the zeroposition of the encoder disc (falling edge of GA withDIR = 0).

Changing FlexCount Resolution, Offset,or DirectionFlexCount must be stopped before the resolution(RESSUB), offset (ZPOS), or direction of rotation arechanged (pin DIR or parameter DIR). This is done usingparameter STOPFLEX, which stops FlexCount.

STOPFLEX Address 0x11; bit 5Value Description0 FlexCount active (normal operation)1 FlexCount Stopped

Table 34: FlexCount Reset


Rev D1, /45

After changing the FlexCount resolution, offset,or direction, activate FlexCount again by settingSTOPFLEX = 0. This resets and re-enables FlexCount,causing the incremental (ABZ) and absolute (if SE-LABS = 0) outputs to count to the current absolute po-sition. During this period, the outputs are not validand POSOK = 0. POSOK is set to 1 when the positionoutputs are again valid.

POSOK Address 0x12; bit 0Value Description0 Position Invalid1 Position Valid

Table 35: Position Valid

As shown in Figure 4, it is recommended to implementa timeout when checking for POSOK. This timeout mustbe larger than the startup time tstFlex (see spec. item804) of the FlexCount. This avoids a potential infiniteloop that could happen due to glitches or communi-

cation errors. If POSOK is still 0 after some numberof timeouts (typically 5), a configuration error can beassumed.

Additionally, the incremental (ABZ) outputs can be setlow (NOUTLO = 0 and TRIABZ = 0) or the incrementaloutputs can be set to tristate (TRIABZ = 1) to avoid in-valid outputs when changing the FlexCount resolution,offset or direction. After the outputs are at the currentabsolute position (POSOK = 1), enable the FlexCountoutputs (NOUTLO = 1 and TRIABZ = 0).

NOUTLO Address 0x11; bit 6Value FlexCount Outputs0 Low1 Normal Operation

Table 36: FlexCount Outputs

See INCREMENTAL OUTPUTS on page 33 for moreinformation on TRIABZ.


Rev D1, /45

OPERATING MODE

The iC-LNB has two operating modes which are se-lected using configuration bit EPG.

EPG Address 0x07, bit 4Value Description0 Interface Mode1 Parallel Mode

Table 37: Operating Mode

Interface ModeIn interface mode, the shift register is used for abso-lute position output and the quadrature outputs (INCAand INCB) are used for incremental position output. IfFlexCount is enabled (NENFLEX = 0), the incrementalresolution is programmable and an index signal (INCZ)is also available. Also with FlexCount active, the ab-solute resolution can be the same as the incrementalresolution or the maximum as determined by RESSUB.See FLEXCOUNT® on page 29 for more information.

Regardless of the FlexCount resolution, two Gray codeoutputs GA and GB are available. These represent theMSB and MSB – 1 (respectively) of the iC-LNB absolute

position and are provided for use by an external turns(revolution) counter. See GRAY CODE OUTPUTS onpage 36 for more information.

Also in interface mode, an output (XJD) is provided toaid in minimizing the mechanical tilt angle of the iC-LNBrelative to the code disc. See ADJUSTMENT on page38 for more information.

A power-on output at pin POK indicates whether or notthe iC-LNB is ready.

Parallel ModeIn parallel mode, the absolute position output is a 16-bitparallel data word in Gray code. In this mode, all I/Opins are configured as outputs and the shift register out-put, incremental outputs, Gray code outputs, XJD, andPOK outputs cannot be used. See PARALLEL MODEon page 37 for more information.

The SPI interface can also be used for position datareadout and is available in both operating modes. Table38 shows the pin functions for each operating mode.Pins not shown in Table 38 are not affected by thechoice of operating mode.

Pad Interface Mode Parallel ModeTNC Test Input NCOS Parallel Output Bit 15TNS Test Input NSIN Parallel Output Bit 14DIR Code Inversion Input Parallel Output Bit 13NSL Shift Register Load Input Parallel Output Bit 12DIN Shift Register Data Input Parallel Output Bit 11DOUT Shift Register Data Output Parallel Output Bit 10CLK Shift Register Clock Input Parallel Output Bit 9GA Gray-code Output A (MSB) Parallel Output Bit 8GB Gray-code Output B (MSB-1) Parallel Output Bit 7XJD Adjustment Signal Parallel Output Bit 6POK Power OK Indication Parallel Output Bit 5INCZ Incremental Output Z Parallel Output Bit 4INCB Incremental Output B Parallel Output Bit 3INCA Incremental Output A Parallel Output Bit 2TPS Test Input PSIN Parallel Output Bit 1TPC Test Input PCOS Parallel Output Bit 0

Table 38: Pin Functions According to Operating Mode


Rev D1, /45

INCREMENTAL (ABZ) OUTPUTS

ABZ ResolutionIn interface mode (EPG = 0), the incremental outputsINCA and INCB can be set to use various interpolationfactors or the FlexCount resolution. Selection is madeusing parameter INC.

INC Address 0x08; bits 6:4Value Resolution0x00 Interpolation Factor X10x01 Interpolation Factor X20x02 Interpolation Factor X40x03 Interpolation Factor X80x04 Interpolation Factor X160x05 iC-Haus digital test0x06 iC-Haus test0x07 FlexCount Resolution

Table 39: Incremental Output Resolution

If INC = 0x00 – 0x04, the resolution of the ABZ outputsis the selected interpolation factor times the resolutionof the incremental track on the code disc. INC = 0x05and 0x06 are used for special test modes as explainedin TEST FUNCTIONS on page 41. If INC = 0x07, theABZ resolution is the selected FlexCount resolution.See FLEXCOUNT® on page 29 for more information.

Note that a valid Z pulse on output INCZ is only avail-able when FlexCount resolution is used (INC = 0x07).

Direction ReversalIf FlexCount is enabled (NENFLEX = 0 and SE-LABS = 0), the rotation direction of the incremental out-puts can be reversed using parameter DIR or the DIRinput.

DIR Address 0x07; bit 5Value Description0 CW (Normal Rotation)1 CCW (Reversed Rotation)

Table 40: Direction Reversal

The DIR input and the DIR bit are XOR (exclusive OR)gated. This means that no direction reversal occurs ifthe DIR input is high and parameter DIR = 1.

FlexCount must be reset after changing the directionof rotation. See FLEXCOUNT® on page 29 for moreinformation.

Incremental Output InversionIf FlexCount is used (INC = 0x07), the incremental (ABZ)outputs can be inverted as required using register bitsINVA, INVB, and INVZ. If FlexCount is not used (INC =/0x07), these bits have no effect.

INVA Address 0x0B; bit 6Value Incremental Output INCA0 Normal1 Inverted

Table 41: INCA Output Inversion

INVB Address 0x0B, bit 5Value Incremental Output INCB0 Normal1 Inverted

Table 42: INCB Output Inversion

INVZ Address 0x0B; bit 4Value Incremental Output INCZ0 Normal1 Inverted

Table 43: INCZ Output Inversion

Note that inverting INCA or INCB reverses the countingdirection of the AB outputs. Inverting both INCA andINCB does not affect the AB counting direction.

INCZ PositionIf FlexCount resolution is used (INC = 0x07), the posi-tion of the INCZ output (relative to zero absolute posi-tion) is programmable. The Z position is determined byparameter ZPOS, as shown in Table 44.

ZPOS Addresses 0x0C, 0x0D, 0x0E bits 3:0Value Z Position (Edges Relative to Absolute Zero)0x00000 0 (any interpolation)0x00001 1 (only with 8 bit interpolation)0x00002 2 (only with 7 or 8 bit interpolation)0x00003 3 (only with 8 bit interpolation)0x00004 4 (only with 6,7 or 8 bit interpolation)... ...0x00008 8 (any interpolation)... ...0x3FFFF 262 143 (only with 8 bit interpolation)

Table 44: INCZ Position


Rev D1, /45

If ZPOS = 0x0000, the zero position is coincident withthe falling edge of GA (iC-LNB MSB) as shown in Figure20).

INCZ

GA (MSB)

INCA

INCB

ZPOS = 0x0

Figure 20: Zero position for ZPOS = 0x0

Acceptable ZPOS values are also affected by the inter-polator resolution RESIPO, as shown in Table 45.

RESIPO Address 0x0E; bits 6:5Value ZPOS Value3 Evenly divisible by 82 Evenly divisible by 41 Evenly divisible by 20 any value

Table 45: Allowed ZPOS Value

ZPOS is an 18-bit value spread across three registersin the iC-LNB register map, as shown in Table 46.

ZPOS RegistersBits Address17:14 0x0E bits 3:013:7 0x0D bits 6:06:0 0x0C bits 6:0

Table 46: ZPOS Addresses

INCZ WidthIf FlexCount resolution is used (INC = 0x07), the widthof the INCZ output is also programmable. The Z widthis determined by parameter Z90, as shown in Table 47.

Z90 Address 0x0E; bit 4Value Index Width (AB Cycle) Coincident With0 180 A high1 90 A and B high

Table 47: Z Pulse Width

The INCZ output coincidence shown in Table 47 is trueif ZPOS = 0x00000 and INVA = INVB = INVZ = 0. OtherZPOS values cause the INCZ output to be coincidentwith other AB states. Depending on the value of ZPOS,it may be necessary to invert INCA, INCB, or both toachieve the desired coincidence.

TristateThe incremental outputs INCA, INCB, and INCZ can beput into a high-impedance state (tristate) using registerbit TRIABZ.

TRIABZ Address 0x0B; bit 3Value INCA, INCB, INCZ0 Normal Operation1 Tristate

Table 48: Incremental Outputs Tristate

This can be used to eliminate invalid transitions on theABZ outputs when changing the FlexCount resolutionor direction. After power-on TRIABZ = 1.


Rev D1, /45

SHIFT REGISTER OUTPUT

In interface mode (EPG = 0), a shift register is used forabsolute position output.

As shown in Figure 21, the current absolute positionis latched into the shift register on the first falling edgeon the shift register clock input (CLK) while the shift

register load input (NSL) is high. Following this, theabsolute position is clocked out on the shift registeroutput (DOUT) on each rising edge of CLK, regardlessof the level of NSL. Position is output in Gray code orbinary, depending on parameter NGRAY, MSB first.

CLK

NSL

DOUT MSB MSB-1 LSB DIN

CLK

NSL

DOUT MSB MSB-1 LSB DIN

RN

F =

0R

NF

= 1 Latch

Latch

Figure 21: Shift register output

External data can be read into the iC-LNB through theshift register input (DIN). This data is clocked out fol-lowing the position data, as shown in Figure 21.

The shift register output (DOUT) returns to its idle state(as specified by parameter RNF) on the rising edge ofNSL. This means that the falling edge of NSL can occurany time during position transmission and is not critical.

Output Data LengthThe length of the shift register and the number of po-sition bits used are selected using parameter SRC, asshown in Table 49.

SRC Address 0x08; bits 2:0Value Shift Register Length Number of Bits Used0 18 bits 181 17 bits 172 16 bits 163 16 bits 154 16 bits 145 16 bits 136 14 bits 137 14 bits 12

Table 49: Shift Register Output Data Length

Position is always shifted out MSB first and left-justified.If the output data length is greater than the number ofbits used (SRC ≥ 3), the unused LSBs are zero. For

example, if SRC = 4, the shift register outputs the 14-bitposition value followed by two zeros.

Output Data FormatParameter NGRAY is used to select whether the shiftregister absolute position output is in Gray code or bi-nary as shown in Table 50.

NGRAY Address 0x07; bit 6Value Data Format0 Gray Code1 Binary

Table 50: Shift Register Output Data Format

If FlexCount is enabled (NENFLEX = 0 and SE-LABS = 0) and a non-binary resolution is used(RESSUB + 1 is not an integer power of 2), the absoluteposition is a value between two non-zero numbers re-gardless of the setting of NGRAY. See FLEXCOUNT®

on page 29 for more information on the absolute posi-tion numeric formats.

Idle OutputParameter RNF is used to select the idle output of theshift register output (DOUT) as shown in Table 51.


Rev D1, /45

RNF Address 0x08; bit 3Value Shift Register Output (DOUT)0 Absolute Position MSB1 High

Table 51: Shift Register Idle Output

If the position data is invalid (POSOK = 0), the outputDOUT is set to low in idle state.

Direction ReversalIf FlexCount is enabled (NENFLEX = 0 and SE-LABS = 0), the absolute position direction can be re-versed using parameter DIR or the DIR input. Bothof these accomplish direction reversal by inverting theMSB of the Gray code absolute position.



The DIR input and the DIR bit are XOR (exclusive OR)gated. This means that no direction reversal occursif the DIR input is high and parameter DIR = 1. Direc-tion reversal also works when binary output is selected(NGRAY = 1) as the conversion from Gray code to bi-nary occurs after the MSB inversion.

FlexCount must be reset after changing the directionof rotation. See FLEXCOUNT® on page 29 for moreinformation.

Shift Register DisableThe output shift register can be disabled using NEN-SHIFT.

NEN-SHIFT

Address 0x00; bit 6

Value Description0 Output shift register enabled1 Output shift register disabled

Table 53: Shift Register Disable

GRAY CODE OUTPUTS

In interface mode (EPG = 0), outputs GA and GB pro-vide two 90° shifted digital signals with 1 PPR eachas shown in Figure 22. These signals can be used byan external revolution counter to implement multiturncapability.

GA (MSB)

0°

GB (MSB-1)

270°90° 180° 360°

One revolution

V10 (DA10V)

N10 (DA10N)

V9 (DA9V)

N9 (DA9N)

Figure 22: Outputs GA and GB

GA and GB are independent of the FlexCount resolu-tion (RESSUB) or the zero position (ZPOS), and alwaysoccur at the positions shown in Figure 22 relative to thecode disc.

The DIR input or parameter DIR (0x07 bit 5) can beused to invert the GA signal to reverse the rotationdirection of the GA and GB outputs.




If FlexCount is enabled (NENFLEX = 0 and SE-LABS = 0), it must be reset after changing the directionof rotation. See FLEXCOUNT® on page 29 for moreinformation.


Rev D1, /45

PARALLEL OUTPUT MODE

Parallel output mode is provided as an alternative to theserial shift register output, incremental outputs, and theGray code outputs. Parallel output mode is selected bysetting EPG = 1.

EPG Address 0x07, bit 4Value Description0 Interface Mode1 Parallel Output Mode

Table 55: Operating Mode

In parallel output mode, the absolute position output is a16-bit parallel data word in Gray code. In this mode, allI/O pins are configured as outputs and the shift registeroutput, incremental outputs, Gray code outputs, XJD,and POK outputs cannot be used.

The 16-bit parallel output can be the 10 bits from thedigital tracks and 6 bits from the interpolator or the top16 FlexCount bits depending on parameter SELABS.See FLEXCOUNT® on page 29 for more informationon parameter SELABS and configuring FlexCount.

If FlexCount is enabled (NENFLEX = 0 and SE-LABS = 0) and a non-binary resolution is used(RESSUB + 1 is not an integer power of 2), the absoluteposition is a value between two non-zero numbers. See

FLEXCOUNT® on page 29 for more information on theabsolute position numeric formats.

It is recommended to set the interpolator resolution to 6bits (RESIPO = 0x2) when using parallel output mode toallow the maximum input frequency, unless additionalresolution is required by the SPI interface. See INTER-POLATOR on page 28 for more information on RESIPOand input frequency.

The DIR input or parameter DIR (0x07 bit 5) can beused to invert the MSB to reverse the rotation directionof the parallel output.




If FlexCount is enabled (NENFLEX = 0 and SE-LABS = 0), it must be reset after changing the directionof rotation. See FLEXCOUNT® on page 29 for moreinformation.


Rev D1, /45

ADJUSTMENTS

Tilt AngleIn interface mode (EPG = 0), a special output (XJD) isavailable to aid in adjusting the iC-LNB to minimize itstilt angle relative to the code disc for maximum accu-racy.

XJD is the XORed signal from tracks DA4V and DA10V(the differential signal of the leading track 4 and track10 diodes). As shown in Figure 23, adjust the tilt angleof the iC-LNB relative to the code disc to minimize thespike width, t, at 0° and 180°, as indicated by the edgesof the GA output.

GA (MSB)

XJD

0° 180°

t

T/2

t

Figure 23: Using XJD to Minimize Tilt Angle

The maximum tilt angle that can be tolerated by thesystem is determined by the the diameter of the codedisc and the chosen interpolator hysteresis (HYS), asshown in Table 57.

HYS(2:0) LNB1S LNB4S0x00 1.8° 1.0°0x01 1.75° 1.0°0x02 1.7° 0.95°0x03 1.7° 0.95°0x04 1.65° 0.95°... ... ...0x07 1.6° 0.9°

Table 57: Maximum Tilt Angle (relative to chip center)

The scan ratio for the adjustment signal at XJD can bederived from the maximum tilt angle. For example, withthe LNB1S 42-1024 at a tilt angle of 1.8°, photodiodeDA4V is approximately 74 µm from its ideal position.With an average radius of 19.89 mm for track DA4, thisresults in an edge shift of 0.06%. The edge shift forphotodiode DA10V is approximately the same size, butin the opposite direction. Therefore, the scan ratio ist/T = 0.12% for the maximum tilt angle of 1.8°. Minimiz-ing this value minimizes the tilt angle and maximizessystem accuracy.

The actual spike width, t, depends on the rotation speedof the code disc. Under optimum conditions, the maxi-mum spike Width is

t [µs] =36 000

Speed [RPM]

The min. spike width is 0 µs and can be regarded as anideal value, but is difficult to achieve in practice. Dueto imperfect light levels, code disc tolerances, etc. ad-justment to a spike width between 0 µs and half of thismaximum value is recommended. Ideally, both spikesshould be the same width. For example, at 300 RPM,the spike width, t, should be less than 60 µs ( 36000

300 ·0.5).

Radial PositionThe radial position of the iC-LNB relative to the codedisc must be adjusted to center the tracks of the disc onthe photodiodes of the iC-LNB. The error from ideal ra-dial position must be less than 100 µm to avoid crosstalkbetween the absolute tracks, which can cause absoluteposition errors.

Radial position error also causes a phase error betweenthe sine and cosine signals from the incremental track.This phase error can be measured and used to adjustthe radial position of the iC-LNB relative to the codedisc.

The phase error for a radial position error of 100 µm isshown in Table 58.

Code Disc Phase ErrorLNB1S 42-1024 0.65°LNB4S 26-1024 1.6°

Table 58: Phase Error with 100 µm Radial PositionError

Adjust the radial position of the iC-LNB relative to thecode disc to minimize the phase error between the sineand cosine signals.


Rev D1, /45

LED POWER CONTROL

The optical power received by the sine/cosine sensorsis kept constant by the integrated LED power control,regardless of changes in temperature and LED agingeffects. The control mode is determined by parameterLCTYP, the options being sum control or square control.It is recommended to use square control during normaloperation and sum control only for calibration.

LCTYP Address 0x06; bit 6Value Control Type0 Square Control (sin2+cos2)1 Sum Control (DC sum)

Table 59: LED Power Control Type

The control setpoint is determined by parameterLCSET.

LCSET Address 0x06; bits 5:0Value Square Control

LCTYP = 0Sum ControlLCTYP = 1

0x00 0.240 Vp 0.140 V0x01 0.243 Vp 0.142 V... 0.24 Vp

1−LCSET·0.01250.14 V

1−LCSET·0.01250x3F 1.1 Vp 0.640 V

Table 60: LED Power Control Setpoint

LCMOD determines whether or not deadband is usedin the LED power control loop.

LCMOD Address 0x01; bit 6Value Control Mode (LCTYP = 0 or 1)0 Continuous Control1 Deadband Control (approximately ± 5% of setpoint)

Table 61: LED Power Control Mode

In operation, if LCMOD = 0, the LED power control de-creases the LED power whenever the LED voltage ex-ceeds the setpoint (LCSET) and increases it wheneverthe LED voltage is less than the setpoint. If LCMOD = 1,the LED power is only changed when the LED voltagedeviates from the setpoint by more than ≈ ± 5%.

The iC-LNB monitors the operation of the LED powercontrol. If LED current exceeds the control range,ERRS in the status register (0x12 bit 1) is set to 1and the ERR output is activated. See ALARM OUTPUTon page 39 for more information.

ALARM OUTPUT

The iC-LNB has an alarm or error output (ERR) toindicate errors. Under normal operation, ERR is lowindicating that no errors are present.

ERR is driven high when the LED power control rangeis exceeded (ERRS = 1) or a parity error is detected inthe RAM (ERRP = 1). ERRS and ERRP can also beread from the SPI status register, address 0x12 bits 1and 2, respectively.

ERR

GND

VDD

³1ERRS

ERRP

ERROR MESSAGE

Figure 24: Alarm Output


Rev D1, /45

OSCILLATOR

The iC-LNB has two internal oscillators, one each forthe interpolator and FlexCount. The frequency of theseoscillators can be trimmed using parameter OSZC.

The oscillator frequency also affects the maximumspeed (sin/cos input frequency). See INTERPOLATORon page 28 and spec. item 706 for more information.

OSZC Address 0x07; bits 3:2Value Typical Interpolator

Oscillator FrequencyTypical FlexCountOscillator Frequency

0 16.5 MHz 17.0 MHz1 17.5 MHz 18.0 MHz2 19.0 MHz 19.5 MHz3 20.0 MHz 20.5 MHz

Table 62: Oscillator Adjustment

It is recommended to use OSZC = 2, the startup value,unless application conditions require otherwise.


Rev D1, /45

TEST FUNCTIONS

Test functions are provided in the iC-LNB to allow ob-servation of internal analog signals for calibration andadjustment. These internal signals replace the analogsine and cosine outputs when TA = 1.

TA Address 0x09; bits 5:4Value Output at PSIN, NSIN, PCOS, NCOS0 Normal operation1 Test Mode2 iC-Haus Test3 iC-Haus Test

Table 63: Test Modes

In test mode (TA = 1), parameter TMUX determineswhich four internal signals are available on the analogsine and cosine outputs, as shown in Table 64.

TMUX Address 0x09; bits 3:0Value Pin PSIN Pin NSIN Pin PCOS Pin NCOS0x00 VPSI VNSI VPCI VNCI0x01 AVP1 Vref AVN1 Vcomp0x02 ANP1 Vref ANN1 Vcomp0x03 AN2 Vref AV2 Vcomp0x04 AN3 Vref AV3 Vcomp0x05 AN4 Vref AV4 Vcomp0x06 AN5 Vref AV5 Vcomp0x07 AN6 Vref AV6 Vcomp0x08 AN7 Vref AV7 Vcomp0x09 AN8 Vref AV8 Vcomp0x0A AN9 Vref AV9 Vcomp0x0B AN10 Vref AV10 Vcomp0x0C VREFPS VREFNS VREFPC VREFNC0x0D PSIN NSIN PCOS SVDC0x0E PCOS NCOS PSIN CVDC0x0F,NENF = 1

IPQT IPO VREFO BIASPO

0x0F,NENF = 0

PSF NSF PCF NCF

Table 64: Test Signal Multiplexer for Analog Signals

See SIGNAL CONDITIONING on page 26 for informa-tion on using the test signals for device calibration.

A digital test mode is provided to allow observation ofinternal digital signals for test and diagnosis. Theseinternal signals replace the incremental outputs whenINC = 0x05, as shown in Table 65.

TMUX Address 0x09; bits 3:0Code Pin INCA Pin INCB Pin INCZ0x00 NENOS NLOCK fipo/40x01 V1 N1 I70x02 V1 N1 I70x03 V2 N2 I70x04 V3 N3 I70x05 V4 N4 I70x06 V5 N5 I70x07 V6 N6 I70x08 V7 N7 I70x09 V8 N8 I70x0A V9 N9 I70x0B V10 N10 I70x0C I6 I5 I70x0D I4 I3 I70x0E IPO_A IPO_B IPO_Z0x0F I2 I1 I7

Table 65: Test Signal Multiplexer for Digital Signals


Rev D1, /45

DESIGN REVIEW: Notes On Chip Functions

iC-LNB VNo. Function, Parameter/Code Description and Application Notes

Refer to datasheet iC-LNB release B2, 2016.

Table 66: Notes on chip functions regarding iC-LNB chip release V

iC-LNB U2No. Function, Parameter/Code Description and Application Notes

None at time of release.

Table 67: Notes on chip functions regarding iC-LNB chip release U2


Rev D1, /45

REVISION HISTORY

Rel. Rel. Date* Chapter Modification PageA1 13-06-21 Initial Release

Rel. Rel. Date* Chapter Modification PageB1 15-02-02 Electrical Characteristics Item 102: changed name in "Max. Spectral Sensitivity"

Added new item 103: spectral sensitivity of 850nmItem 703: angular hysteresis correctedItem F01, F02: corrected typ. and add. min/max valid for iC-LNB V

9, 10

OPERATING REQUIREMENTS:SPI Interface

Updated Figure 2 SPI interface timing: definition of tcsItem I002: changed SCK hi→ lo to SCK lo→hi

14

SPI Interface Notice box on MISO regarding idle state of pin MISODescription revised: Position data output format is always Gray code

21, 22

Design Review Added chip revision iC-LNB VChip revision X and X1 removed

35

Programming iC-LNB Figure 4 enhanced with information regarding defensive programming 19

Rel. Rel. Date* Chapter Modification PageB2 2016-06-17 ELECTRICAL

CHARACTERISTICSItem 707 added: propagation delay interpolator 10

FLEXCOUNT® Improved description and notes of table 30 29DESIGN REVIEW: Notes On ChipFunctions

Removed notes of pre-series revision W1Added note on chip revision V

42

Rel. Rel. Date* Chapter Modification PageC1 2018-03-27 all Complete rework for chip revision iC-LNB U2

(For chip revision iC-LNB V please refer to datasheet release B2, 2016)all

Rel. Rel. Date* Chapter Modification PageD1 2020-10-08 DESCRIPTION Note added 2

PACKAGING INFORMATION Added information of IC top marking for LNB2C package 4ABSOLUTE MAXIMUM RATINGS Items G005, G010 changed 8ELECTRICALCHARACTERISTICS

Items 702, 703, 706, 707, 802, 803, A13, A14, B13, B14 changedItems 708, 804 added

10 ff.

OPERATING REQUIREMENTS Symbol names changed 15 f.CONFIGURATION PARAMETERS Parameter SRC changed 17CONFIGURING THE iC-LNB Figure 4 changed 20SPI INTERFACE Figure 17 changed 25SIGNAL CONDITIONING Information on square control adjustment added 27INTERPOLATOR Table 23 and Table 25 changed

Startup time added28

FLEXCOUNT® Note on POSOK addedPOSOK timeout changed

29 ff.

SHIFT REGISTER OUTPUT Note on idle output added 36ADJUSTMENTS Note on ideal spike width added 38OSCILLATOR Table 62 values corrected 40TEST FUNCTIONS Table 64 changed: VTH→ Vref, VREF → Vcomp 41

* Release Date format: YYYY-MM-DD


Rev D1, /45

iC-Haus expressly reserves the right to change its products, specifications and related supplements (together the Documents). A Datasheet Update Notification(DUN) gives details as to any amendments and additions made to the relevant Documents on our internet website www.ichaus.com/DUN and is automaticallygenerated and shall be sent to registered users by email.Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source.

The data and predicted functionality is intended solely for the purpose of product description and shall represent the usual quality and behaviour of the product.In case the Documents contain obvious mistakes e.g. in writing or calculation, iC-Haus reserves the right to correct the Documents and no liability arises insofarthat the Documents were from a third party view obviously not reliable. There shall be no claims based on defects as to quality and behaviour in cases ofinsignificant deviations from the Documents or in case of only minor impairment of usability.No representations or warranties, either expressed or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder withrespect to information/specification resp. Documents or the products to which information refers and no guarantee with respect to compliance to the intendeduse is given. In particular, this also applies to the stated possible applications or areas of applications of the product.

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Software and its documentation is provided by iC-Haus GmbH or contributors "AS IS" and is subject to the ZVEI General Conditions for the Supply of Productsand Services with iC-Haus amendments and the ZVEI Software clause with iC-Haus amendments (www.ichaus.com/EULA).

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Rev D1, /45

ORDERING INFORMATION

Type Package Options Order Designation

iC-LNB 30-pin optoBGA standard reticle LNB1R iC-LNB oBGA LNB2C-1Rstandard reticle LNB4R iC-LNB oBGA LNB2C-4Rcustomer specific reticle iC-LNB oBGA LNB2C-xR

38-pin optoQFN standard reticle LNB1R iC-LNB oQFN38-7x5-1Rstandard reticle LNB4R iC-LNB oQFN38-7x5-4Rcustomer specific reticle iC-LNB oQFN38-7x5-xR

StandardCode Discs Sin/Cos 1024 PPR,

10 bit digitalOD/ID ∅42/18 mm, glass

LNB1S 42-1024

Sin/Cos 1024 PPR,10 bit digitalOD/ID ∅26/9.6 mm, glass

LNB4S 26-1024

Please send your purchase orders to our order handling team:

Fax: +49 (0) 61 35 - 92 92 - 692E-Mail: [email protected]

For technical support, information about prices and terms of delivery please contact:

iC-Haus GmbH Tel.: +49 (0) 61 35 - 92 92 - 0Am Kuemmerling 18 Fax: +49 (0) 61 35 - 92 92 - 192D-55294 Bodenheim Web: http://www.ichaus.comGERMANY E-Mail: [email protected]

Appointed local distributors: http://www.ichaus.com/sales_partners

mailto:[email protected]

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iC-LNB WITH SPI, SERIAL, AND PARALLEL INTERFACES...iC-LNB 18-BITOPTICALENCODER...

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