Going Deeper with Embedded FPGA Platform for Convolutional ... · Going Deeper with Embedded FPGA...

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Going Deeper with Embedded FPGA Platform for Convolutional Neural Network Jiantao Qiu 1 , Jie Wang 1 , Song Yao 1 , Kaiyuan Guo 1 , Boxun Li 1 , Erjin Zhou 1 , Jincheng Yu 1 , Tianqi Tang 1 , Ningyi Xu 2 , Sen Song 3 , Yu Wang 1 , Huazhong Yang 1 1 Departmentt of Electronic Engineering, Tsinghua University 2 Hardware Computing Group, Microsoft Research Asia 3 School of Medicine, Tsinghua University Group URL: http://nicsefc.ee.tsinghua.edu.cn {songyao, yu-wang}@mail.tsinghua.edu.cn 2016/2/22 1

Transcript of Going Deeper with Embedded FPGA Platform for Convolutional ... · Going Deeper with Embedded FPGA...

Page 1: Going Deeper with Embedded FPGA Platform for Convolutional ... · Going Deeper with Embedded FPGA Platform for Convolutional Neural Network JiantaoQiu1, JieWang1, Song Yao1, KaiyuanGuo1,

Going�Deeper�with�Embedded�FPGA�Platform�

for�Convolutional�Neural�NetworkJiantao Qiu1, Jie Wang1, Song Yao1, Kaiyuan Guo1, Boxun Li1,

Erjin Zhou1, Jincheng Yu1, Tianqi Tang1, Ningyi Xu2, Sen Song3, Yu Wang1, Huazhong Yang1

1Departmentt of Electronic Engineering, Tsinghua University2Hardware Computing Group, Microsoft Research Asia

3School of Medicine, Tsinghua UniversityGroup URL: http://nicsefc.ee.tsinghua.edu.cn{songyao, yu-wang}@mail.tsinghua.edu.cn

2016/2/221

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Contents

• Deep Learning and Convolutional Neural Network• Motivation• Related Work• Our Work: Angel-Eye

– Overall Flow– V1: Architecture and Implementation Details– V1: Performance Comparison– V2: Brief introduction

• Open Question: Computation Granularity

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Deep Learning

• Deep Learning: The new tide in artificial intelligence• Inspired by neuroscience• A collection of simple trainable mathematical units, which collaborate to

compute a complicated function.• Deep Neural Network (DNN)/Recurrent Neural Network (RNN)/Long-

Short Term Memory (LSTM)/Convolutional Neural Network (CNN)

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Convolutional Neural Network (CNN)

• CNN: State-of-the-art in visual recognition applications

CONV + Non Linear + Pooling CONV + Non Linear + Pooling FC + Non Linear

FC + Non Linear

Probability in class 1 Probability in class 2

Probability in class N

Input Image Feature Maps

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Year Team Top-5 Accuracy

2010 NEC 71.8%

2011 XRCE 74.2%

2012 SuperVision 84.7%

2013 Clarifai 88.3%

2014 GoogLeNet 93.3%

2015 MSRA 96.4%

Top-5 accuracy of image classification in Image-Net Large-Scale Visual Recognition Challenge (ILSVRC)

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Contents

• Deep Learning and Convolutional Neural Network• Motivation• Related Work• Our Work: Angel-Eye

– Overall Flow– V1: Architecture and Implementation Details– V1: Performance Comparison– V2: Brief introduction

• Open Question: Computation Granularity

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CNN: Mainstream in Computer Vision

• CNN: State-of-the-art in visual recognition applications

Tracking [UIUC2015]Vehicle and Lane Detection[Stanford2015]

Pedestrian Detection [NUS2015]

Object detection Posture estimation Face recognition

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CNN: High Complexity

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• Conv Layers: bounded by computations

0.21

 

0.34

 

0.17

  3.87

 

3.87

 

0.90

 

0.83

 

1.85

  5.55

 

5.55

 

0.30

 

0.30

 

5.55

  9.25

  12.95 

0.45

 

0.45

 

5.55

  9.25

  12.95 

0.30

 

0.30

 

1.85

 

2.31

 

3.70

 

0.08

 

0.10

 

0.21

 

0.21

 

0.21

 

0.03

 

0.03

 

0.03

 

0.03

 

0.03

 

0.01

 

0.01

 

0.01

 

0.01

 

0.01

 

CaffeNet ZF VGG11 VGG16 VGG19

CONV1 CONV2 CONV3 CONV4CONV5 FC6 FC7 FC8

0.14

0.06

0.01

0.15

0.15

1.23

2.46

0.29

0.88

0.88

3.54

3.54

3.54

5.90

8.26

2.65

5.31

14.1

6

23.5

9

33.0

3

1.77

3.54

18.8

7

28.3

1

37.7

5 150.

99

209.

72 411.

04

411.

04

411.

04

67.1

1

67.1

1

67.1

1

67.1

1

67.1

1

16.3

8

16.3

8

16.3

8

16.3

8

16.3

8

CaffeNet ZF VGG11 VGG16 VGG19

CONV1 CONV2 CONV3 CONV4CONV5 FC6 FC7 FC8

• FC Layers: bounded by memory accessDistribution of computations (GOPs)

Distribution of storage demands (GOPs)

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Motivation

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Why customized hardware?• High complexity versus Limited energy• CPU and GPU are not efficient enoughHow to accelerate CNN with FPGA?

• High Complexity under Limited Resource• CNN Model Compression• Highly efficient computing units• Using convolver for FC layers

• High Complexity under Limited Bandwidth• CNN model compression• Shorter representations• Reducing memory access

CNN acceleration is more than hardwareComplete compilation tool is expected

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Contents

• Deep Learning and Convolutional Neural Network• Motivation• Related Work• Our Work: Angel-Eye

– Overall Flow– V1: Architecture and Implementation Details– V1: Performance Comparison– V2: Brief introduction

• Open Question: Computation Granularity

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Related Work

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• (MSR) K. Ovtcharov et al. Accelerating deep convolutional neural networks using specialized hardware. Microsoft Research Whitepaper, 2, 2015

• (MSR Slides) K. Ovtcharov et al. Toward Accelerating Deep Learning at Scalue Using Specialized Hardware in the Datacennter, Hotchips 2015.

• (Baidu Slides)• (NYU) C. Farabet et al. An FPGA-

based Stream Processor for Embedded Real-Time Vision with Convolutional Networks, ECVW 2009.

• (NYU) C. Farabet et al. CNP: An FPGA-based Processor for Convolutional Networks, FPL 2009.

• (NEC) M. Sankaradas et al., A massively parallel coprocessor for convolutional neural networks. ASAP 2009.

• (NEC) S. Cadambi et al., A programmable parallel accelerator for learning and classification. PACT 2010.

• (NEC) S. Chakradhar et al., A dynamically configurable coprocessor for convolutional neural networks. In ACM SIGARCH Computer Architecture News 2010.

• (NYU/Yale) Farabet et al. Large-Scale FPGA-based Convolutional Networks, 2011.

• (NYU/Yale) Farabet et al. NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision, ECVW 2011.

• (NYU/Yale) Farabet et al. Hardware Accelerated Convolutional Neural Network for Synthetic Vision Systems.

• (Purdue/NYU) P. Pham, NeuFlow:Dataflow Vision Processing System-on-a-chip, MWSCAS 2012.

• (Eindhoven University of Technology) M. Peemen et al. Memory-centric accelerator design for convolutional neural networks. ICCD 2013.

• (Purdue) V. Gokhale et al. A 240 G-ops/s Mobile Coprocessor for Deep Neural Networks, CVPRW 2014.

• (CAS) T. Chen et al. DianNao: A small-footprint high-throughput accelerator for ubiquitous machine learning, ASPLOS 2014

• (CAS) Y. Chen et al. DaDianNao: A Machine-Learning Supercomputer, MICRO 2014

• (CAS) Y. Chen et al. PuDianNao: A Machine Learning Accelerator, ASPLOS 2015

• (CAS) Z. Du et al. Shidiannao: Shifting vision processing closer to the sensor, ISCA 2015

• (PKU) C. Zhang et al., Optimizing fpga-based accelerator design for deep convo-lutional neural networks. FPGA 2015.

• (MIT) Y. Chen et al. Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. ISSCC 2016.

• (KAIST) J. Sim et al. A 1.42tops/w deep convolutional neural network recognition processor for intelligent ioe systems. ISSCC 2016.

• (Stanford) S. Han et al. EIE: Efficient Inference Engine on Compressed Deep Neural Network, arxiv

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Related Work

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• Memory System Optimization– DianNao Series

*1 Diannao: A small-footprint high-throughput accelerator for ubiquitous machine learning, Chen, Z. Du, N. Sun, J. Wang, C. Wu, Y. Chen, and O. Temam. ASPLOS ’14 *2 DaDianNao: A Machine-Learning Supercomputer, Y. Chen, T. Luo, S. Liu, S. Zhang, L. He, J. Wang, L. Li, T. Chen, Z. Xu, N. Sun, O. Temam, MICRO ’14*3 PuDianNao: A Machine Learning Accelerator, Y. Chen, T. Luo, S. Liu, S. Zhang, L. He, Jia Wang, L. Li, T. Chen, Z. Xu, N. Sun, O. Temam, ASPLOS ‘15*4 Shidiannao: Shifting vision processing closer to the sensor, Z. Du, R. Fasthuber, T. Chen, P. Ienne, L. Li, T. Luo, X. Feng, Y. Chen, and O. Temam, ISCA ’15

DianNao ‘14 DaDianNao ‘14

PuDianNao ‘15

Functionality

An ML accelerator which accommodates seven representative ML techniques (CNN/DNN included).

Multi-chip CNN/DNN Accelerator

Single-chip CNN/DNN Accelerator

ScaleShiDianNao ‘15Single-chip CNN

Accelerator for Visual Recognition Algorithms

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Related Work

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• Memory System Optimization– DianNao Series

Problem: Using on-chip memory to store parameters in each layer of the CNN model, hard to be used for state-of-the-art large CNN models

Strategy 1: Tiling and Data ReuseCut down memory trafficStrategy 2: Storage BufferDedicated buffer for data reuseStrategy 3: On-Chip MemoryUsing on-chip memory to store all parameters

How to solve the memory problem?

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Related Work

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• Computing Engine Optimization

• [MIT ISSCC2016] Y. Chen et al. Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. ISSCC 2016.

• [KAIST ISSCC2016] J. Sim et al. A 1.42tops/w deep convolutional neural network recognition processor for intelligent ioe systems. ISSCC 2016.

Small PE: Eyeriss [MIT ISSCC2016] Complex PE: [KAIST ISSCC2016]

All existing work considers partial of the entire flow, and thus are hard to fully utilize hardware and achieve optimal

energy efficiency

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Contents

• Deep Learning and Convolutional Neural Network• Motivation• Related Work• Our Work: Angel-Eye

– Overall Flow– V1: Architecture and Implementation Details– V1: Performance Comparison– V2: Brief introduction

• Open Question: Computation Granularity

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Overall Flow

• Overall Flow of Angel-Eye

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CNN Model

CompressedFloating-Point Model

CompressedFixed-Point Model

Instructions

Neural NetworkAccelerator

On Embedded FPGA

Modelcompression

Data/weightquantization

Compilation

Run

“Goal: accelerate fast algorithms.”

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Model Compression

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• Model Compression– Reducing complexity while maintaining comparable accuracy

Original Shallow Thin Decomposition Pruning • Singular Value Decomposition (SVD)

• No demand for specific computation unit• Moderate compression• Computation model

• Storage complexity

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Data Quantization

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• Data Quantization– Uses shorter fixed-point numbers

1 2 48

16

32

0

10

20

30

40

32bit 16bit 8bit 4bit 2bit 1bit

1338

38798 35 8 0

756

225 60 21 5 00

1000

2000

32bit 16bit 8bit 4bit 2bit 1bit

LUT FF

Resources needed by a multiplier

• Dynamic-Precision Data Quantization

Interger part Fractional part

Dynamic for different layer

Bandwidth utilization

• Proposed Flow

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• Dynamic-Precision Data Quantization Results (Simulation results)

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Data Quantization

Network CaffeNet VGG16-SVDData Bits Single-float 16 8 Single-float 16 8

Weight Bits Single-float 16 8 Single-float 16 8 or 4

Data Precision N/A Dynamic Dynamic N/A Dynamic Dynamic

Weight Precision N/A Dynamic Dynamic N/A Dynamic Dynamic

Top-1 Accuracy 53.9% 53.9% 53.0% 68.0% 64.6% 64.1%

Top-5 Accuracy 77.7% 77.1% 76.6% 88.0% 86.7% 86.3%

Network VGG16Data Bits Single-float 16 16 8 8 8 8

Weight Bits Single-float 16 8 8 8 8 8 or 4

Data Precision N/A 2-2 2-2 Impossible 2-5/2-1 Dynamic Dynamic

Weight Precision N/A 2-15 2-7 Impossible 2-7 Dynamic Dynamic

Top-1 Accuracy 68.1% 68.0% 53.0% Impossible 28.2% 66.6% 67.0%

Top-5 Accuracy 88.0% 87.9% 76.6% Impossible 49.7% 87.4% 87.6%

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Instruction Set

• Coarse‐grained Instructions

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Index PoolBypass

NLBypass

ZeroSwitch

Result Shift

Bias Shift

WriteEn

PEEn

PhaseType

Pic Num

TileSize

LayerType

1 X X X X X No 2 First 2 Tr Conv

2 Yes Yes Bias X BS No 2 Calculate 2 Tr Conv

3 No No Zero X X PE 2 Calculate 2 Tr Conv

4 X X X RS X DDR 2 Last 2 Tr Conv

• Hardware handles fine-grained operations• Inst 1: commands Input Buffer to load all the needed data• Inst 2: starts calculating the four tiled blocks in the output layer• Inst 3: Write En is set as “PE” to command Output Buffer send

the intermediate results back to the Pes• Inst 4: Write EN is set as “DDR” to command the Output Buffer

write results back to the external memory (last layer)

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Architecture and Implementation Details

• Overall Architecture

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CPU ExternalMemory

Proc

essi

ng S

yste

m

DMA

Data & Inst. Bus

Input Buffer

PE

Computing Complex

Output Buffer

PE PE

FIFO

Con

trol

ler

Prog

ram

mab

le L

ogic

Config.

Bus

• Processing System• Flexibility• CPU + DDR• Scheduling operations• Prepare data and instructions• Realize Softmax function

• Programmable Logic• Hardware acceleration• Computing Complex + On-chip

Buffers + Controller + DMA• Few Complex PEs

• Achieve three-level parallelism• Inter-output: multiple PEs• Intra-output• Operator-level

• 16-bit dynamic-precision data quantization

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Architecture and Implementation Details

• Processing Engine Architecture

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C

ConvolverComplex

+

+

+

+

+ NL PoolC

C

Output Buffer

InputBuffer

Data

Bias

Weights

Intermediate Data

Controller

PE

AdderTree

Bias Shift

Datashift

……

• Achieve intra-output parallelism by placing multiple Convolvers• Convolver: optimized for 3x3 convolution operation• Adder Tree: sum up results of one convolution operation• NL: supports non-linear function (ReLU)• Pool: supports max-pooling• Bias Shift & Data Shift: support dynamic-precision fixed-point numbers

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Architecture and Implementation Details

• Line-buffer design– Optimized for 3x3 Convolver– Supports operator-level parallelism

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⋯⋯ ⋯⋯

⋯⋯ ⋯⋯

⋯⋯

MUX

MUX

Data buffer

Weight buffer

MultipliersAdder Tree

X+

9 Data Inputs

9 Weight Inputs

n Delays

Delays

+

++

⋯ +⋯

X XX X XX X X

InputData

InputWeight

OutputData

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Architecture and Implementation Details

• Tiling and Data Reuse Strategy

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• Using Convolver for FC layers

• FC layers are bandwidth-bounded

• Convolvers are enough tocompute FC layers

• Save resource to accelerateConv layers

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Performance Comparison

• Performance and Energy Efficiency Comparison

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Chakaradhar2010

Gokhale2014

Zhang2015 Ours

Platform Virtex 5 SX240t

ZynqXC7Z045 Virtex7 VX485t Zynq XC7Z045

Clock (MHz) 120 150 100 150Bandwidth (GB/s) - 4.2 12.8 4.2

Quantization 48-bit fixed 16-bit fixed 32-bit float 16-bit fixedProblem Complexity

(GOP) 0.52 0.552 1.33 30.76

Performance(GOP/s) 16 23.18 61.62 136.97 (Overall)187.89 (Conv)

Power (W) 14 8 18.61 9.63Power Efficiency

(GOP/J) 1.14 2.90 3.31 14.22 (Overall)19.50 (Conv)

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Angel-Eye V2

• Similar overall architecture• Fully parameterized design

• Supports different data quantization settings• Supports different PE and Convolver number

• Supports different Conv kernel size• User-friendly compiler• Fine-grained instructions

• Increase the flexibility of compiler• More optimization in compiler back-end

Platform Performance Power PriceAngel-Eye V2 on

Xilinx 7020 30GOP/S ~2W ~40 dollar

Nvidia Tegra K1 60-90GOP/S ~10-15W 199 dollar

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Angel-Eye V2: Face Det + Alig

• Overall Flow

Face Alignment

InputInput FaceDetection

FaceDetection

FaceAlignment

FaceAlignment

Haar-like featureon ARM

9-layer CNNin FPGARGB image

16Conv3x3 -> 16Conv3x3 -> 32Conv3x3 -> 32Conv3x3 -> 48Conv3x3 ->64Conv3x3 -> 64Conv3x3 -> 80Conv3x3 -> 128Conv3x3 -> FC10

• 8-bit dynamic-precision quantization without fine-tuningFixed-point

Network 27.3794 32.0091 66.1796 27.1025 45.1339 33.6290 67.4658 62.2705

Original Network 26.0281 31.5535 65.0193 25.9672 43.4501 33.8175 66.2999 61.1216

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Contents

• Deep Learning and Convolutional Neural Network• Motivation• Related Work• Our Work: Angel-Eye

– Overall Flow– V1: Architecture and Implementation Details– V1: Performance Comparison– V2: Brief introduction

• Open Question: Computation Granularity

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Open question: Computation Granularity

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• Computer Engine Architecture Comparison– [KAIST ISSCC2016] and ours

Few complex compute elements

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Open question: Computation Granularity

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• Computer Engine Architecture Comparison

Few complex PEs VS. Many simple PEs

[MIT ISSCC2016]

[KAIST ISSCC2016]

[Ours]

Guess: Neural networks are highly predictable and serial. Few complex PEs can better utilize these characters.

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Conclusion

• Deep Learning: Mainstream in AI• Motivation• Related Work• Our Work: Angel-Eye

– Overall Flow– V1: Architecture and Implementation Details– V1: Performance Comparison– V2: Brief introduction

• Open Question: Computation Granularity

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Thanks!Q&A