Gem5 Intro - Zhejiang ......

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Transcript of Gem5 Intro - Zhejiang ......

  • Gem5  Intro

    Wenzhi Chen, Zhongyong Lu

    [email protected]

  • 系统结构实验室

    Gem5

    l Abstract l Basics  of  gem5 l Simulation  modes

    - SE  &  FS

    l Benchmarks  on  gem5 - A  Mickey  mouse  benchmark - PAESEC  benchmark - Obtained  Statistics

  • 系统结构实验室

    Abstract

    l gem5  Simulator - The  gem5  simulation  is  the  merger  of  the  best  aspects  of   the  M5    and  GEMS    simulators.

    l M5  Simulator - M5  provides  a  configurable  simulation  framework  ,   multiple  ISAs,    diverse  CPU  models.

    l GEMS  simulator - GEMS  complements  these  features  with  a  detailed  and   flexible  memory  system,  including  support  for  multiple   cache  coherence  protocols  and  interconnect  models.

  • 系统结构实验室

    Abstract

    l Gem5  has  been  a  multi-­‐year  effort  from  both  academy   and  industry.

    l Main  goals - Open  source  tool  focused  on  architectural  modeling - Flexibility

    p Multiple   CPU  models,  memory  systems,  and  device  models p Across  the  speed  vs  accuracy  spectrum

    - Availability p For  both  academic  and  corporate  researchers p No  dependence  on  proprietary  code p BSD  license

    - Collaboration p Combined  effort  of  many  with  different  specialties p Active  community  leveraging  collaborative  technologies

  • 系统结构实验室

    High-­‐level  Features

    l Configurable  CPU  models - Simple  one-­‐IPC  (SimpleAtomic/Timing) - Detailed  in-­‐order  execution  (InOrder) - Detailed  out-­‐of-­‐order  execution  (O3)

    l Pluggable  memory  system - Classic  memory  model - Ruby  memory  model

    l Device  Models - Enough  device  models  to  boot  Linux

    l Boot  real  operating  systems - Linux,  Android

    l Many  ISAs - ARM,  ALPHA,  MIPS,  SPARC,  POWER,  X86

  • 系统结构实验室

    Basic  of  gem5

    l Compile  targets - scons build// - ISAs:  ARM,  ALPHA,  MIPS,  SPARC,  POWER,  X86

    l Binaries - gem5.debug debug  build,  symbols,  tracing,  assert - gem5.opt optimized  build,  symbols,  tracing,  assert - gem5.fastoptimized  build,  no  debugging,  no   symbols,  no   tracing,  no  assertions

    - gem5.prof gem5.fast  +  profiling  support

  • 系统结构实验室

    Simulation  modes

    l Syscall emulation  (SE) - For  running  individual  applications,  or  set  of  applications  on  MP - Models  user-­‐visible  ISA  plus  common  system  calls - System  calls  emulated,  typically  by  calling  host  OS - Simplified  address  translation  model,  no  scheduling

    l Full  system  (FS) - For  booting  operating  systems - Models  bare  hardware,  including  devices - Interrupts,  exceptions,  privileged  instructions,  fault  handlers - Simulated  UART  output - Simulated  frame  buffer  output

  • 系统结构实验室

    Simulation  mods  -­‐ System  Call  Emulation

  • 系统结构实验室

    Simulation  modes  -­‐ Full  System  (Linux  on  ARM)

  • 系统结构实验室

    Benchmarks  on  gem5  -­‐ PARSEC

    l The  Princeton  Application  Repository  for  Shared-­‐ Memory  Computers  (PARSEC)  is  a  benchmark  suite   composed  of  multithreaded  programs.

    l The  suite  focuses  on  emerging  workloads  and  was   designed  to  contain  a  diverse  selection  of   applications  that  is  representative  of  next-­‐ generation  shared-­‐memory  programs  for  chip-­‐ multiprocessors.

  • 系统结构实验室

    Benchmarks  on  gem5  -­‐ configuration

    l CPU:  x86,  4-­‐core,  in-­‐order l L1  I-­‐Cache

    - 32  KB,  2-­‐way  set-­‐associative,  latency  3  cycles l L1  D-­‐Cache

    - 64  KB,  2-­‐way  set-­‐associative,  latency  3  cycles l L2  Cache

    - Unified,  2  MB  8-­‐way  set-­‐associative,  latency  15  cycles,  MESI   CMP  directory  cache  coherence  protocol

    l Cacheline size:  64B l Memory  size:  2GB l OS:  Linux  2.6.28.4.smp

  • 系统结构实验室

    Benchmarks  on  gem5  -­‐ cache  statistics

    L1 ICache Miss Rate (%)

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    0.2

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    0.8

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    1.2

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  • 系统结构实验室

    Benchmarks  on  gem5  -­‐ cache  statistics

    L1 DCache Miss Rate (%)

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    Core 0

    Core 1

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  • 系统结构实验室

    Benchmarks  on  gem5  -­‐ cache  statistics

    L2 Cache Miss Rate (%)

    0

    10

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    bla cks ho les

    flu ida nim ate

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    can ne al

    ded up

    str eam clu ste r

    ave rag e

  • 系统结构实验室