Dr. John M. Emmert

SCHOLARSHIP

PUBLICATIONS

1. V. J. Patel, J. M. Emmert, B. Dupaix, W. Khalil, “Poly-phased, Time-Interleaved Digital-to-Analog Converter,” IEEE Transactions on Circuits and Systems, In-preparation 2017.

2. J. D. Pelan and J. M. Emmert, “Pulse Descriptor Word Multi-Signal Tracker for FPGA Implementation,” IEEE Transactions on Aerospace and Electronic Systems, Submitted 2016.

3. D. Bowman and J. M. Emmert, “Hardware Trojans Based on Parasitic Bipolar Junction Transistor Circuits,” GOMACTech-17, March 2017.

4. C. Taylor and J. M. Emmert, “Two-Stage Voltage Divider for Logic Reduction in an Asynchronous Register Feedback Loops,” The Institution of Engineering and Technology Electronics Letters, (Under Revision), Submitted 2014.

5. S. Ren and J. M. Emmert, “A Successive Approximation Pipelined (SAP) ADC with one clock cycle conversion rate,” The Institution of Engineering and Technology Electronics Letters, 2012.

6. S. Ren, J. M. Emmert, and R. E. Siferd, “Design and Performance of a Robust 180nm CMOS Standalone VCO and Integrated PLL,” Journal of Analog Integrated Circuits and Signal Processing, Volume 68, pp. 285-298, September 2011.

7. T. Pemberton, H. Axtell, T. Hopkins, and J. M. Emmert, “Radiation Hardened Digital Single Sideband Modulator ASIC,” GOMACTech-11, April 2011.

8. R. Wang, B. Brakus, H. Gopalakrishnan, and J. M. Emmert, “A Substrate Noise Sensing Circuit for Noise Tolerance in Mixed-Signal Systems-on-a-Chip,” IEEE North Atlantic Test Workshop, May 2008.

9. J. Buck, J. Tsui, S. Hary, C. Shreffler, D. Schwab, and J. M. Emmert, “Monobit Receiver Architecture and Signal Threshold Determination,” GOMACTech-07, March 2007.

10. P. Buxa, G. Creech, and J. M. Emmert, “Parameterizable Digital Receiver with Decimation Filter for High Update Rate,” GOMACTech-07, March 2007.

11. J. M. Emmert, M. Abramovici, and C. E. Stroud, “On-line, Fault Tolerance for FPGA Logic Blocks,” IEEE Transactions on VLSI Systems, Volume 15, pp. 216-226, February 2007.

12. J. Emmert, J. Cheatham, and H. Axtell, “Analysis and Test of a Spectral, Mixed Signal BIST Technique for Systems on a Chip Applications,” IEEE North Atlantic Test Workshop, May 2006.

13. J. A. Cheatham, J. M. Emmert, and S. R. Baumgart, “A Survey of Fault Tolerant Methodologies for FPGAs,” ACM Transactions on Design Automation of Computer Systems, Volume 11, Number 2, pp. 501-533, April 2006.

14. S. Singh, A. Roy, K. Rattan, and J. M. Emmert, “Performance Tradeoffs of Hardware/Software Implementation of a Fuzzy Logic Controller on Programmable Hardware,” 2005 IEEE North American Fuzzy Information Processing Society Soft Computing for Real World Applications Conference, June 2005.

15. J. M. Emmert and J. A. Cheatham, “Integrated Spectral BIST Technique for IRFFE Systems,” GOMACTech-05, April 2005.

16. M. Abramovici, C. E. Stroud, J. M. Emmert, “On-line BIST and BIST Based Diagnosis of FPGA Logic Blocks,” IEEE Transactions on VLSI Systems, Volume 12, Number 12, pp. 1284-1294, December 2004.

Curriculum Vita John M. Emmert Page 2 of 6 17. J. M. Emmert and J. A. Cheatham, “A Monolithic Spectral BIST Technique for Control or Test of

Analog or Mixed-Signal Circuits,” 2003 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 2003.

18. J. M. Emmert, J. A. Cheatham and B. Jagannathan, “An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals,” 2003 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 2003.

19. J. M. Emmert, S. Lodha, and D. K. Bhatia, “On Using Tabu Search for Design Automation for VLSI Systems,” Journal of Heuristics, Volume 9, Number 1, pp. 75-90, January 2003.

20. M. Abramovici, C. E. Stroud, and J. M. Emmert, “Using Embedded FPGAs for SoC Yield Enhancement,” Proceedings of the 2002 ACM/IEEE Design Automation Conference, 2002.

21. J. M. Emmert and D. K. Bhatia, “Two-Dimensional Placement Using TABU Search,” Journal of VLSI Design, Volume 12, Number 1, pp. 13-23, December 2001.

22. J. M. Emmert, C. E. Stroud, S. R. Baumgart, P. Kataria, and M. Abramovici, “On-line Fault Tolerance for FPGA Interconnect with Roving STARs,” Proceedings of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2001.

23. J. M. Emmert and J. A. Cheatham, “On-line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router,” Proceedings of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2001.

24. M. Abramovici, J. M. Emmert, and C. E. Stroud, “Roving STARs: An Integrated Approach to On-Line Testing, Diagnosis, and Fault Tolerance for FPGAs in Adaptive Computing Systems,” Proceedings of the IEEE Evolvable Hardware Conference, pp. 75-94, July 2001.

25. C. E. Stroud, M. Lashinsky, J. Nall, J. Emmert, and M. Abramovici, “On-line BIST and Diagnosis of FPGA Interconnect Using Roving STARs,” Proceedings of the IEEE International Online Test Workshop, 2001.

26. C. E. Stroud, J. M. Emmert, A. Taylor, and J. T. Ferry, “Recovering Faulty Processing Elements in VLSI Processor Arrays,” Autotestcon, September 2001. (received Best Paper Award)

27. P. Kataria and J. M. Emmert, “Window Rip-up for Faster Testing and Fault Tolerance in FPGAs,” Autotestcon, September 2001.

28. T. Slaughter, C. Stroud, J. Emmert, and B. Skaggs, “Fault Injection Emulator for Field Programmable Gate Arrays,” Proceedings of the International Society of Optical Engineering ITCOM, pp. 1-9, 2001.

29. J. R. Heath, N. J. Vocke, C. E. Stroud, and J. M. Emmert, “Routing Algorithms for Programmable Logic Device Design and Manufacturing Test Development,” Autotestcon, September 2001.

30. J. M. Emmert and D. K. Bhatia, “A Fault Tolerant Technique for FPGAs,” in Journal of Electronic Testing Theory and Applications, Volume 16. Number 6, pp. 591-606, December 2000.

31. C. E. Stroud, J. R. Bailey, and J. M. Emmert, “A New Method for Testing Re-programmable Programmable Logic Arrays,” in Journal of Electronic Testing Theory and Applications, Volume 16. Number 6, pp. 635-640, December 2000.

32. C. E. Stroud, J. M. Emmert, J. Bailey, D. Nikolic, and K. S. Chhor, “Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development,” International Test Conference, 2000.

33. M. Abramovici, C. E. Stroud, B. Skaggs, and J. M. Emmert, “Improving On-Line BIST-Based Diagnosis for Roving STARs,” Proceedings of the IEEE International Online Test Workshop, pp. 31-39, 2000.

34. J. M. Emmert, C. E. Stroud, and J. Bailey, “A New Bridging Fault Model for More Accurate Fault Behavior,” Autotestcon, September, pp. 481-485, 2000.

Curriculum Vita John M. Emmert Page 3 of 6 35. J. M. Emmert, C. E. Stroud, J. Cheatham, A. Taylor, P. Kataria, and M. Abramovici, “Performance

Penalty for Fault Tolerance in Roving Self Testing Areas (STARs),” Lecture Notes in Computer Science, Springer-Verlag , Volume 1896, pp. 545-554, August 2000.

36. J. M. Emmert, C. E. Stroud, and M. Abramovici, “Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration,” The Eighth Annual IEEE Symposium on Field-Programmable Custom Computing Machines, April 2000.

37. J. M. Emmert and D. K. Bhatia, “Tabu Search: Ultra Fast Placement for FPGAs,” Lecture Notes in Computer Science, Springer-Verlag, Volume 1673, pp. 81-90, September 1999.

38. J. M. Emmert, S. Blanacha, and D. K. Bhatia, “Physical Layout Techniques for Field Programmable Gate Arrays,” invited paper, IEEE, ACM, SIGDA Design and Test Workshop, 1999.

39. J. M. Emmert and D. K. Bhatia, “A Methodology for Fast FPGA Floorplanning,” ACM Seventh International Symposium on Field-Programmable Gate Arrays, February, pp. 49-56, 1999.

40. J. M. Emmert and D. K. Bhatia, “Fast Timing Driven Placement Using TABU Search,” IEEE International Symposium on Circuits and Systems, May, pp. I302-I305, 1999.

41. J. M. Emmert and D. K. Bhatia, “Incremental Routing in FPGAs,” 11th Annual IEEE International Application Specific Integrated Circuit Conference, September, pp. 217-221, 1998.

42. J. M. Emmert, A. Randhar, and D. K. Bhatia, “Fast Floorplanning for FPGAs,” Lecture Notes in Computer Science, Springer-Verlag, Volume 1482, pp. 129-138, September 1998.

43. J. M. Emmert and D. K. Bhatia, “Reconfiguring FPGA Mapped Circuits,” CERC/VIUF/IEEE Computer Society Workshop on 21st Century Electronics Systems Design: Breakthroughs in Quality and Productivity, December 1997.

44. J. M. Emmert and D. K. Bhatia, “Reconfiguring FPGA Mapped Designs with Applications to Fault Tolerance and Reconfigurable Computing,” Lecture Notes in Computer Science, Springer-Verlag, Volume 1304, pp. 141-150, August 1997.

45. B. C. Read, D. Barker, R. G. Bishop, L. M. Concha, J. M. Emmert, R. L. Ewing, G. L. Fecher, P. Jarusiewic, G. D. Peterson, M. Rubeiz, A. M. Sayson, “Developing the Next Generation Cockpit Display System,” 48th National Aerospace & Electronics Conference, Dayton, Ohio, May 1996.

US PATENTS

1. Digital Receiver Instantaneous Dynamic Range Enhancement. United States Patent # 7,769,108, August 3, 2010.

2. Kernel Function Approximation Receiver. United States Patent # 7,440,989, October 21, 2008.

3. Fault Tolerant Operation of Field Programmable Gate Arrays. Unites States Patent # 6,973,608. December 6, 2005.

4. Fault Tolerant Operation of Reconfigurable Devices Utilizing an Adjustable System Clock. United States Patent # 6,874,108. March 29, 2005.

5. Quadbit Kernel Function Algorithm and Receiver. United States Patent # 6,690,315. February 10, 2004.

6. On-Line Fault Tolerant Operation via Incremental Reconfiguration of Field Programmable Gate Arrays. United States Patent # 6,530,049. March 4, 2003.

BOOK CHAPTER SECTION

1. Book Section: “15.5 FFT-Based Mixed Signal BIST,” System on Chip Test Architectures, Elsevier, ISBN: 978-0-12-373973-5, 2008.

Curriculum Vita John M. Emmert Page 4 of 6 TECHNICAL REPORTS

1. J. M. Emmert, “Active Transmit Attenuation and Cancellation (ATAC), Air Force Office of Scientific Research (AFOSR), 2012.

2. J. M. Emmert, J. A. Cheatham, and B. Jagannathan, “Built-In-Self-Test for Automatic Insertion into Mixed Signal Systems (BIST AIMS), Air Force Research Laboratory (AFRL), 2003.

3. M. Abramovici, C. E. Stroud, and J. M. Emmert, “On-Line Testing and Reconfiguration of FPGAs for Fault Tolerant Applications in Adaptive Computing Systems, Air Force Research Laboratory (AFRL), 2002.

4. J. M. Emmert and D. K. Bhatia, “TABU Search for Fast Timing Driven Placement of Circuits on FPGAs,” University of Cincinnati Technical Report Number: TR219/09/98/ECECS, 1998.

5. J. M. Emmert and D. K. Bhatia, “Partial FPGA Routing for Fault Tolerance,” University of Cincinnati Technical Report Number: TR209/10/97/ECECS, 1997.

6. J. M. Emmert and D. K. Bhatia, “Partial Reconfiguration of FPGA Mapped Designs,” University of Cincinnati Technical Report Number: TR202/01/97/ECECS, 1997.

PROGRAMATIC BRIEFINGS (Facilitated establishment of RAPCEval program at Wright State)

1. “NEWSTARs Electronic Warfare Program,” United States House of Representatives Staffers for Austria (Ohio) and Turner (Ohio), and United States Senate Staffers for Voinovich (Ohio) and Brown (Ohio), February 2009.

2. “NEWSTARs Electronic Warfare Program,” United States House of Representatives Staffers for Hobson (Ohio) and Turner (Ohio), and United States Senate Staffers for Voinovich (Ohio) and Brown (Ohio), February 2008.

3. “NEWSTARs Electronic Warfare Program,” United States House of Representatives Staffers for Hobson (Ohio) and Turner (Ohio), and United States Senate Staffers for Voinovich (Ohio) and Brown (Ohio), January 2007.

4. “NEWSTARs Electronic Warfare Program,” Nine United States Senate/Representative Delegations, United States Capitol. January 2006.

5. “Electronic Warfare Receiver On-a-Chip (EWROC),” United States Senate Staffers for DeWine (Ohio), United States Capitol. February 2004.

6. “Receiver Processing and Concepts Evaluation (RAPCEval) Program,” Senate Armed Services Committee (SASC) Majority and Minority Professional Staffers, United States Capitol. February 2004.

7. “Electronic Warfare Receiver On-a-Chip (EWROC),” United States House of Representatives Staffers for Hobson (Ohio), Turner (Ohio), Kingston (Georgia), and United States Senate Staffers for Chambliss (Georgia), (2 February 2004); and United States Senate Staffers for DeWine (Ohio), February 2004.

ABSTRACT, WORKSHOP, AND INVITED PRESENTATIONS

1. “Enabling Highly Integrated mm-Wave Phased Array,” Defense Advanced Research Projects Agency (DARPA), Chip-Scale Avionics Workshop, February 2007.

2. “Built-In-Self-Test for Automatic Insertion into Mixed-Signal Systems (BIST AIMS),” Defense Advanced Research Projects Agency (DARPA) IRFFE PI Meetings, May, 2002 (Kick-off); February, 2003; October, 2003; June, 2004, March 2005.

3. “A Comprehensive Design and Test Methodology for Mixed-Signal Microsystems,” Defense Advanced Research Projects Agency (DARPA) NeoCAD Program Kick-off Meeting, August 2001.

Curriculum Vita John M. Emmert Page 5 of 6 4. “FPGA Layout Techniques,” Invited Tutorial, IEEE/ACM/SIGDA Third International Design and Test

Workshop, 1999.

5. “Poster Title: Reconfiguring FPGA Mapped Designs with Applications to Fault Tolerance and Reconfigurable Computing,” ACM Fifth International Symposium on Field-Programmable Gate Arrays, February 1997.

GRANTS FUNDED

RBS Technologies LLC

1. Siferd, Emmert, George and Ren, Phase I and II SBIR, Low Power Multi-Channel RF and Digital GPS Anti-Jam ASIC, United States Air Force, 2013-2017.

2. Siferd, Emmert, George and Ren, Phase I and II SBIR, High Resolution Wideband Direct Conversion Receiver, United States Air Force, 2011-2013.

3. Siferd, Emmert and Ren, Phase I and II SBIR, Multi Channel RFASIC for Handheld GPS Receiver Anti-JAM Enhancement, United States Air Force, 2008-2011.

4. Siferd, Emmert and Ren, Phase I and II SBIR, Digital Antijam (AJ) Processing Application Specific Integrated Circuits (ASIC) for Hand-held Global Positioning Satellite (GPS) Receiver, United States Air Force, 2007-2010.

Wright State University

5. Emmert, Design Framework and CAD Tools for Hardware Security and Trust, $400,000 Edaptive Computing Systems, 2017-2020 (pending).

6. Rigling, Emmert and Shaw, Target Recognition and Adaption in Contested Environments (TRACE), $1,015,000 Defense Advanced Research Projects Agency (DARPA), 2015-2017.

7. Zhang, Saunders, Emmert, Bryant, Xie, Regionally Aligned Priorities In Delivering Skills (RAPIDS), $541,294/$999,894 State of Ohio, 2016.

8. Emmert, Active Transmit Attenuation and Cancellation (ATAC), $73,000 Air Force Office of Scientific Research, 2011-2012.

9. Emmert, Electronic, Optical and Electro-Optical Materials Research: Mixed-Signal Component Design, $755,000, Air Force Research Laboratory (AFRL), 2007-2010.

10. Emmert and Garber, New Electronic Warfare Specialists Through Advanced Research by Students (NEWSTARs), $250,000 (`06), $250,000 (`07), and $500,000 (`09), Congress (Start Date 1 July 2006).

11. Emmert, Anti-jam ASIC for Handheld GPS, $200,000, RBS Technologies, 2008-2010.

12. Emmert, RF ASIC for GPS, $30,000, RBS Technologies, 2008.

13. Emmert, Generic EW/RF Digital Design Toolbox Development, $94,788, Air Force Research Laboaratory (AFRL), 2006-2008.

14. Chen and Emmert, Electronic Warfare Receiver on a Chip (EWROC), $300,000, Air Force Research Laboratory (AFRL), 2003-2004.

15. Emmert, Built-In-Self-Test (BIST) for Mixed Signal Microsystems, $400,000, Defense Advanced Research Projects Agency (DARPA), 2002-2005.

16. Emmert, FPGA Based Quadbit Receiver Design, $40,500, Air Force Research Laboratory (AFRL), Sensors Directorate (SN), 2002-2003.

17. Emmert, FPGA Based Monobit Receiver Design, $15,000, Ball Engineering, 2002.

Curriculum Vita John M. Emmert Page 6 of 6 18. Emmert, FPGA Lab Hardware Update, $11,370, Wright State University, 2002.

University of North Carolina at Charlotte

19. Emmert and Stroud, On-Line Testing and Reconfiguration of FPGAs for Fault Tolerance in Adaptive Computing Systems, $300,000, Lucent Technologies, subcontract under a DARPA grant for $1,509,000, 2000-2001.

20. Emmert, FPGA Based MonoBIT Receiver Design, $55,000, Ball Engineering, 2000-2001.

University of Kentucky

21. Emmert, On-Line Reconfiguration of FPGAs for Fault Tolerant Applications in Adaptive Computing Systems, $177,000, Lucent Technologies, subcontract under a DARPA grant for $1,509,000, 1999-2000.

22. Stroud and Emmert, CPLD Based Embedded Logic Analyzer, $35,000, Cypress Semiconductor, 1999-2001.