0S4 0000 00100H Chili Module Datasheet

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Copyright CHILIdevices International 2010. All Rights Reserved.

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CHILImodule CDM1540xHardware Datasheet


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Copyright CHILIdevices International 2010. All Rights Reserved.

2

CONTENTS

CONTENTS .............................................................. 2 FIGURES ................................................................. 5 TABLES ................................................................... 7 REVISION HISTORY ................................................ 8 DATA SHEET STATUS .............................................. 9 DEFINITIONS AND ABBREVIATIONS .................... 10

GENERAL DESCRIPTION ....................................... 11 DEVICE DETAILS ................................................... 13 PRINCIPLES OF OPERATION ................................. 15

Power Supply ............................................................................ 15Wireless Communications ......................................................... 15 Processor and Memory .............................................................. 16Fixed Interfaces ........................................................................ 16Field Programmable Logic Array (FPGA) ................................... 17 Softw are ................................................................................... 18

APPLICATIONS ..................................................... 19 ORDERING INFORMATION .................................... 20 FUNCTIONAL BLOCK DIAGRAM ............................. 21 HARDWARE .......................................................... 22

Terminal Functions .................................................................... 22

Pin Diagrams ........................................................................................ 22Pin Descriptions .................................................................................... 22

Functional Description............................................................... 30General ............................................................................................... 30

Reset Input / Output ................................................................. 33Power Supply ............................................................................ 34Processor .................................................................................. 38


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Copyright CHILIdevices International 2010. All Rights Reserved.3

Direct Connections from P rocessor ........................................... 38 FLASH ........................................................................................ 39 SDRAM ...................................................................................... 40 EEPROM ..................................................................................... 40 REAL TI ME CLOCK ..................................................................... 40 FPGA ......................................................................................... 41

I/O Standards ....................................................................................... 42FPGA Clock Signals ................................................................................ 43FPGA GPIO Specifications ....................................................................... 44FPGA Configuration Loader ..................................................................... 44Using External Configuration Memory ....................................................... 45Using ByteBlaster II Download Cable ....................................................... 45

Module Interfaces ..................................................................... 46USB .................................................................................................... 46I2C ..................................................................................................... 47SDIO ................................................................................................... 47WLAN (IEEE 802.11b) ............................................................................ 48

Integrated Antenna ......................................................................... 49External Antenna ............................................................................ 49WEP Encryption/Decryption and AES Security Algorithms ...................... 49

ZigBee (IEEE 802.15.4) ......................................................................... 49External Batteries ................................................................................. 51Li Battery Charging ............................................................................... 52

Charger operation ........................................................................... 52Charge current and safety timer ........................................................ 52Maximum charge current .................................................................. 54Current threshold setting ................................................................. 55Temperature qualified charging ......................................................... 55Status outputs ................................................................................ 55Battery Charge Monitoring ................................................................ 56

System Clocks ...................................................................................... 57JTAG/Debugging (PXA270) ..................................................................... 57JTAG/Debugging (FPGA)......................................................................... 59

Absolute Maximum Ratings ....................................................... 60 Recommended Operating Conditions ......................................... 61 Electrical Characteristics ........................................................... 61Package Outl ine ........................................................................ 62

ADDITIONAL INFORMATION ................................ 65 Chemical Content ...................................................................... 65Contact Information .................................................................. 65

APPLICATION GUIDELINES .................................. 66 Appl ication Examples ................................................................ 66


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Getting Started with the CHILImodule .................................................... 66FPGA Recovery Image............................................................................ 67MMC/SD Card Interface .......................................................................... 68USB Client Device Interface .................................................................... 71USB Host Controller Interface ................................................................. 72

Appl ication Notes ...................................................................... 73Using Custom Clock Frequencies with FPGA .............................................. 73Using External Antennas ........................................................................ 73Lithium Battery Considerations ................................................................ 73Using External Ethernet Devices .............................................................. 75Using External CAN Devices .................................................................... 76System Debugging and Driver Development Guidelines .............................. 76

Boot Device Selection Guidelines .............................................. 77Printed Circuit Board Design Guidelines .................................... 77

Base Substrate Selection ........................................................................ 77Land Pattern Recommendations .............................................................. 77Escape Pattern for CHILImodule............................................................. 78Layout Guidelines .................................................................................. 78Via Design ........................................................................................... 79PCB Finish ............................................................................................ 79Paste Stencil Design .............................................................................. 80

Assembly Guidel ines ................................................................. 80General ............................................................................................... 80

Unpack the Module .......................................................................... 80Solder Base Board to the Application Board ......................................... 80Insert Radio Board .......................................................................... 81Mount Enclosure ............................................................................. 82

Moisture Preconditioning ........................................................................ 82Solder Paste ......................................................................................... 83Reflow Profile ....................................................................................... 83Rework and Component Removal ............................................................ 86

DISCLAIMERS ....................................................... 87 APPENDIX ............................................................ 88

CHILImodule - FPGA Connections Cross Reference ................. 88


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Figure 35 USB Host Device Interface ......................................................................... 72Figure 36 Typical Lithium Cell Charge Profile .............................................................. 74Figure 37 Example of the Lithium Cell Capacity Vs. Temperature ................................... 75Figure 38 External Ethernet MAC + PHY ..................................................................... 75Figure 39 Using External CAN Transceiver .................................................................. 76Figure 40 Pad Style Definitions ................................................................................. 77Figure 41 Padstack Recommendation ........................................................................ 78Figure 42 Package Layout Pattern ............................................................................. 78Figure 43 Land Pattern And Via Design ...................................................................... 79Figure 44 Paste Stencil Recommendation ................................................................... 80Figure 45 Base Board .............................................................................................. 81Figure 46 Examples of Reflow Profiles........................................................................ 84Figure 47 Another Reflow Profile Example .................................................................. 85


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TABLESTable 1 Ordering Information ................................................................................... 20Table 2 Pin Descriptions .......................................................................................... 22Table 3 MR# Input Specifications .............................................................................. 33Table 4 Master Reset MR# ....................................................................................... 34Table 5 RSO# Output Specifications .......................................................................... 34Table 6 Power Source in Use .................................................................................... 35Table 7 Power Source Selection by External Signal ...................................................... 35Table 8 BATT_LOW# and BATT_FAULT# Specifications ................................................ 36Table 9 VCC_OUT and VCC_BAT Specifications ........................................................... 36Table 10 RTC_PWR Specifications ............................................................................. 37Table 11 FPGA Configurations .................................................................................. 41Table 12 I/O Standards of the CHILImodule / Altera FPGA .......................................... 42Table 13 I/O Specifications of Altera Cyclone .............................................................. 44Table 14 Altera Serial Configuration Devices ............................................................... 45Table 15 WLAN Interface Specifications ..................................................................... 48Table 16 Antenna Selection (WLAN, ZigBee) ............................................................... 48Table 17 ZigBee Interface Specifications .................................................................... 51Table 18 Charge Currents ........................................................................................ 53Table 19 Battery Charging Specifications ................................................................... 54Table 20 Status Output Specifications (VCC = 5V) ....................................................... 56Table 21 Absolute Maximum Ratings ......................................................................... 60Table 22 Recommended Operating Conditions ............................................................ 61Table 23 Module Electrical Characteristics .................................................................. 61Table 24 The CHILImodule Package Information ........................................................ 63Table 25 The CHILImodule Package Properties .......................................................... 64Table 26 Recommended Baking Procedure ................................................................. 83Table 27 Reflow Profile Recommendations .................................................................. 83Table 28 Heating Zone Temperatures (Example) ......................................................... 85


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DEFINITIONS AND ABBREVIATIONSAES Advanced Encryption StandardBCD Binary-Coded DecimalBGA Ball Grid Array

BST Boundary Scan TestEEPROM Electrically Erasable Programmable Read Only MemoryFFD Full Function DeviceFPGA Field Programmable Gate ArrayGPIO General Purpose I/OGPS Global Positioning SystemHDI High Density InterconnectHDI High Density InterconnectIOE (Altera) Input/Output ElementIP Intelligent PropertyJTAG Joint Test Action GroupLVCMOS Low Voltage CMOSLVTTL Low Voltage TTLMMC MultiMedia CardNSMD Non-Soldermask Defined Pads

OSP Organic Solder ProtectiveOTG On-the-GoRF Radio FieldRFD Reduced Function DeviceRoHS Restriction of Hazardous SubstancesRTC Real Time ClockSiP System-in-PackageSMD Surface Mounted Device; Soldermask Defined PadsSoC System-on-ChipUSB Universal Serial BusVHDL Vlsic Hardware Description LanguageWEP Wireless Equivalent PrivacyWLAN Wireless Local Area Network


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GENERAL DESCRIPTIONThe CHILImodule is an advanced, highly flexible system core module built in a small 2.0mm pitch Ball Grid Array (BGA) System-in-Package (SiP).

The module types available are CHILImodule Professional (CDM15400) CHILImodule Standard (CDM15401)

The main features of the CDM15400/15401 are as follows

Pow er Supply

Single Power Supply (+3.5V...+5VDC) Low Power (1...3W typ.) Operation Regulated Supply Voltage Output (+3.3V/700mA

max.)

Battery Support (CDM15400 only)

Built-In Li-Ion/Li-Polymer Battery Charger

Built-In Fuel Gauge (Battery Monitor)

Processor

Intel XScale PXA270, ARM9 Based 32-bit RISC CPUof 312MHz (CDM15401) or 416MHz (CDM15400)

Memory

FLASH for Program Memoryo CDM15401: 16MByteso CDM15400: 64MBytes

SDRAM for Program & Data Memoryo CDM15401: 16MByteso CDM15400: 64MBytes

Wireless Interfaces (CDM15400 only)

Built-In WLAN (IEEE 802.11b) Built-In ZigBee (IEEE 802.15.4)

Programmable Logic

Field Programmable Gate Array (FPGA) with 4kLE(CDM15401) or 12kLE (CDM15400) Capacity

Mass Storage

Support for Memory Cards (Compact Flash, MMC,SD)

System Peripherals

Real Time Clock (RTC) EEPROM

Interfaces

116 Programmable General Purpose I/O Pins 32-Bit Processor Bus (via FPGA device) PCMCIA / PC Card / Compact Flash LCD (STN, TFT) Up to SVGA Resolution 16-Bit Audio I/O I2C SPI

I2S SDIO USB 1.1 Host/Client + USB 2.0 OTG Support

Software Support Built-In Self Diagnostics UBoot Bootloader Built-In FPGA Configuration Loader Linux V2.6 Operating System JFFS2 File System Qt Graphics Library Drivers for Various Peripherals

FPGA IP Support

Processor Resource Routing

Wishbone Bus Interface for IP Extensions UART 16550 Serial Peripheral Interconnect (SPI) Controller Inter Integrated Circuit (I2C) Controller Ethernet MAC 10/100 MBit/s

Additional Features

High Speed / Low Power Operation (No ForcedCooling or Fan Required)

Support for Boundary Scan (IEEE 1149.1) Test,Debug and Program (Processor and FPGA)

Robust and Easy-to-Route 2.0 mm Pitch Ball GridArray (BGA) Package

The CHILImodule provides embedded system designer a rich set of features to utilize in acommercial product. By hiding the implementation details inside of the module interface,the CHILImodule helps to reduce the development risks and allows the designer to staywithin time and budget limits during the actual design process.

The device comprises of ARM9 based CPU (Intel XScale PXA270) with FLASH (up to64MBytes) and SDRAM (up to 64MBytes) memories required for the application software,Field Programmable Gate Array (FPGA) for flexible and configurable module interface,integrated wireless communication interfaces (only in CDM15400) for both wireless localarea networks (WLAN; IEEE 802.11) and for power efficient control networks based on


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ZigBee (IEEE 802.15.4). Module contains integrated antennas for both of the RF interfacesas well as miniature RF coaxial connectors for using external antennas as applicable.

By utilizing either the CPU resources or FPGA intelligent property (IP) peripherals, thesystem level design may be efficiently created. FPGA resources can be used for extending

the CPU peripheral set, further interfacing custom devices to the CHILImodule

, or simplyfor gaining more performance due to hardware acceleration (signal processing applicationsetc.). In addition to wireless interfaces, the CHILImodule is capable for providing widerange of standard wired interfaces like Ethernet, USB 1.1 (Client, Host) including USB 2.0OTG Support, CAN, UART (RS-232, RS-485, RS422), SPI, I2C...

In addition to various communication interfaces, the CHILImodule devices also supportmemory cards (MMC/SD/SDIO) for implementing local storage capability for the embeddedsystem.

The support for multimedia applications and various user interface solutions iscomprehensive: the CHILImodule can drive small, character based COG LCD displays aswell as full color (up to SVGA/800x600 pixels) TFT LCD displays. Adding audio (in/out)

interface to the solution is matter of only adding simple AC97 compatible codec to thesystem.

The power management and supervisory including the power-down mode support havebeen fully incorporated in the CHILImodule resulting small form factor moduleimplementation that can be run from single +3.5...+5VDC power supply (+4.5...+5VDC forLithium-Ion or Lithium-Polymer battery charging).

In addition to using external power supply, the CHILImodule can be run from the Lithium-Ion or Lithium-Polymer batteries. The built-in Lithium battery charger of the CHILImodule

can be used to charge battery fast and easy. Remaining battery capacity can be read fromintegrated fuel gauge (battery monitor). For stand-alone applications, the module provides+3.3V/700mA power supply for the surrounding circuitry for design simplicity.

Thanks to the large pitch (2.0 mm) and small dimensions (70.5 x 46.5 x 10 mm) theCHILImodulecan easily designed-in to the application - typically, a 4-layer printed circuitboard with 0.5 mm via holes will be sufficient for most of the designs.

From the software point of view, the CHILImodule comes pre-installed bootloader, FPGAconfiguration loader and operating system. The software bundle includes the device driversfor built-in peripherals and for some external peripherals.

The CHILImodule supports using open source FPGA IP blocks based on Wishbone businterface as well as creating your very own FPGA IPs. The FPGA may be used for eithersignal routing, for extending system with new peripheral types or even for hardwareacceleration to gain more system performance.

The bootloader, Linux operating system, FPGA configuration loader and the ready-to-use

FPGA IP blocks come with full source code (C, VHDL) to make it easier for an applicationdesigner to create custom designs. In addition to Linux based systems, other bootloaderand operating system versions available for the CHILImodule will be released either insource code or in binary format, depending on the licensing model.


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DEVICE DETAILSFeatures CHILImodule Standard

CDM15401

CHILImodule ProfessionalCDM15400

Basic Hardware Features

Power Supply +3.5...5.5DC +3.5...5.5VDC

Processor Intel XScale PXA270 312 MHz Intel XScale PXA270 416 MHz

Program Memory (Flash) 16MBytes 64MBytesData Memory (SDRAM) 16MBytes 64MBytes

Data Memory (SRAM; included in the PXA270) 256kBytes 256kBytesField Programmable Gate Array (FPGA) Altera Cyclone EP1C4 Altera Cyclone EP1C12

Programmable I/O Ports Totally 116 I/O Totally 116 I/ODirect Battery Support NA Lithium-Ion/Lithium-Polymer

4.2VBattery Charger with Built-In Charge Timer NA 4.2V/1.35A max.

Battery Monitor (Fuel Gauge) NA YesEEPROM 32kBits 32kBits

Real Time Clock with External 3.0V Backup

Battery

Yes Yes

Fixed Interfaces I2CMMC/SD/SDIO

USB Client

I2CMMC/SD/SDIO

USB Client

Wireless Features

ZigBee Interface NA IEEE 802.15.4(Int./Ext. Antenna)

WLAN Interface NA IEEE 802.11b(Int./Ext. Antenna)

Mechanical SpecificationsPackage 324 Pin BGA (2.0 mm Pitch) 324 Pin BGA (2.0 mm Pitch)

Dimensions 70.5 x 46.5 x 10 mm 70.5 x 46.5 x 10 mm

FPGA IP FeaturesWishbone Compatible Bus Interface Yes Yes

Ethernet MAC 10/100 NA YesCAN 2.0 MAC NA YesUART 16550 Yes Yes

SPI Controller Yes YesI2C Controller Yes Yes

(CPU Resource Routing) Yes YesCustom IP Yes Yes

External Peripheral Support

Power Supply Output +3.3VDC/700mA +3.3VDC/700mAResistive Touchscreen Yes Yes

LCD Interface (COG, STN/TFT, QVGA, VGA,SVGA...)

Yes Yes

Audio Interface (AC97 Codec: Sp, Mic, LineOut, Line In)

Yes Yes

Compact Flash Card Interface (PCMCIA) Yes Yes

MMC/SD Card Interface Yes YesSDIO Interface Yes YesI2C Interface Yes Yes

Ethernet Controller (LAN91C111) Yes YesCAN 2.0 Controller (PCP2515) Yes Yes

GPIO (CPU GPIO) Yes Yes

Software Features

Built-In Self Diagnostics Yes Yes

Bootloader Yes Yes


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Features CHILImodule StandardCDM15401

CHILImodule ProfessionalCDM15400

FPGA Configuration Loader Yes YesOperating System Yes Yes

Device Drivers for Peripherals, IPs andExternal Devices

Yes Yes

File System Yes YesGraphical User Interface Yes Yes


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PRINCIPLES OF OPERATIONThe CHILImodule is a complete ready-to-use, commercial off-the-self (COTS) system corefor building embedded systems and applications. All the primary functions of an embedded

system have been included in the high density system-in-package (SiP) of theCHILImodule.

In addition to wired communication standards, like RS232/422/485, Ethernet or USB, thepossibilities of wireless communication interfaces (WLAN and ZigBee) are available in theCHILImodule Professional version of the device.

Pow er SupplyFor the operation, the CHILImodule device (CDM15400, 15401) requires only single powersupply voltage of +3.5...5VDC. In addition to main power supply, optional backup battery(3.0V Lithium battery) can be connected to the CHILImodule for preserving the real timeclock (RTC) time keeping during the sleep or power-down modes of the CPU.

The CHILImodule contains all the circuitry needed for generating, sequencing andcontrolling internal power supplies as needed without any user intervention. TheCHILImodule is powered-up by connecting the external power supply to the device ifdevice is run from external power only. The internal power supply of the CHILImodule alsosupports the dynamic power control features of the processor for battery-poweredapplications.

In addition to the external power supply, the CHILImodule Professional can also bepowered from a single 4.2V Lithium-Ion or Lithium-Polymer cell. The CHILImoduleProfessional contains built-in battery charger that controls the recharging of the battery ifthe VCC power supply is available, and battery monitor (fuel gauge) for tracking theremaining capacity of the battery. The charge current and safety timer timeout period can

be set according to the desired battery cell type.For design simplicity, the CHILImodule devices provide regulated +3.3VDC supply voltage(up to 700mA) for the surrounding circuitry and external peripherals, and thus eliminatingthe need of additional supply voltage regulators.

The continuous power output of 3.3V (10 mA max.) may be used for powering up debuggerinterface. Continuous power output is available when either VCC or battery cell voltage ispresent.

Wireless CommunicationsThe CHILImodule Professional (CDM15400) contains ready-to-use radio transceivers andMACs for both Wireless LAN (WLAN; IEEE 802.11b) and ZigBee (IEEE 802.15.4)

communications.

Standard WLAN interface offers the benefits of wireless local area network connections thatpreviously were available only for the more expensive devices and computers. The WLANenables connecting the embedded device to the common local area network infrastructurevia wireless access points, gateways and routers.

The high bandwidth of the WLAN interface allows transferring large amounts of data quicklyfrom the embedded device to another device or computer and vice versa.

The ZigBee communication standard is aimed for cost-efficient, low power sensor andcontrol networks. As the CHILImodule has capability of ZigBee Full Function Device (FFD),it can easily be configured either as a member of the ZigBee network or even the ZigBee


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network Coordinator. With all the resources of the CHILImodule it can easily function as anetwork gateway or router to interface ZigBee networks to standard local area networksand even Internet.

The CHILImodule system software includes device drivers and protocol stacks for both of

these wireless communications. The WLAN interface provides the modernencryption/decryption standards (WEP, AES) for secure wireless network communications.The ZigBee interface that is aimed for cost effective sensor and control networks, and theimplementation provides AES encryption/decryption.

Processor and MemoryThe CHILImodule is based on low power, high performance Intel XScale PXA270 processordesigned for embedded applications. The CPU has rich set of integrated peripherals,including support for example USB, serial ports, mass media (like memory cards), audio andvarious displays. In addition to this, many processor pins may be configured as generalpurpose I/O lines.

The power dissipation of the processor is typically below 500mW, and the processorsupports dynamic frequency and voltage management for saving power in battery poweredapplications.

The CHILImodule contains 16MBytes (CDM15401) or 64MBytes (CDM15400) FLASHmemory for the program code storage or Flash data file system and 16MBytes (CDM15401)or 64MBytes (CDM15400) SDRAM memory for data storage or fast program execution.

Fixed InterfacesIn addition to completely configurable digital I/O interfaces, the CHILImodule provides afew fixed interfaces for easy system design and for enabling fail-safe system configurations.

Fixed interfaces that have not been routed via the built-in FPGA device comprise of

I2C Interface (for FPGA fail-over handling) SDIO Interface (for connecting SDIO compatible SD/MMC Cards to the system without

hassle) USB 1.1 Client Interface (for implementing USB 1.1 Full Speed Client application with no

extra devices)

As failures in FPGA design may prevent some system designs from booting properly, theCHILImodule devices support fail-over functionality. Driving the I2C bus SDA-line lowduring the power-up sequence forces the CHILImodule to fall back to the 'known goodconfiguration' of the FPGA. This allows system designer to provide a minimum FPGAconfiguration as a fail-over backup configuration.

SDIO interface signals may be routed directly to external SD/MMC Card connector (socket) .This allows system to use SD/MMC Card for system update during boot sequence. The mainsystem updates images include FPGA image upload - for uploading new FPGA configuration to the module Linux Kernel image upload - for uploading new Linux Kernel image to the module Linux RootFS image upload - for uploading new Linux RootFS image to the module

Thanks to the CHILImodule design, implementing a simple USB 1.1 interface is only matterof connecting USB signals to USB client connector.


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Field Programmable Logic Array (FPGA)The CHILImodule device interface comprises of large Field Programmable Logic Array(FPGA) device that has great impact of the CHILImodule's flexibility and adaptability invarious systems - the move from 'hard' to 'soft' design content opens up new horizons for a

system designer.

Totally, there are 116 freely programmable I/O lines in the CHILImodule, in addition to thefixed interfaces already mentioned. The direction, operation and functionality of these I/Olines are defined by the actual FPGA configuration (aka FPGA image) that can be uploadedfrom an external device to the CHILImodule during the boot-up sequence.

Depending on the CHILImodule device type, there are two FPGA logic capacities available Altera Cyclone EP1C4 (4kLE, up to 78 336 RAM Bits): CHILImodule Standard

(CDM15401) Altera Cyclone EP1C12 (12kLE, up to 239 616 RAM Bits): CHILImodule Professional

(CDM15400)

The FPGA logic of the CHILImodule

forms a flexible ('soft') interface between theCHILImodule internal circuitry and the external systems. The Altera Cyclone FPGA providesall the benefits of large programmable logic to the system designer.

In addition to this, the FPGA logic device allows deciding the CHILImodule componentpinout by means of routing signals in the FPGA logic to the appropriate device pins. Thismay further reduce printed circuit board design complexity and therefore save design costs.Using simple printed circuit board also saves money compared to complex HDI (high densityinterconnect) PCB boards.

Both FPGA devices (EP1C4 and EP1C12) support a variety of single-ended I/O standardssuch as LVTTL, LVCMOS, PCI etc. They also offer differential I/O support via LVDS andRSDS I/O standards. Each channel is capable of operating LVDS signals at up to 640 MBit/s.

The FPGA I/O lines also support hot-swap functionality.With up to six outputs from two phase-locked loops (PLLs) per device and a hierarchicalclocking structure, Cyclone FPGAs offer extensive clock management circuitry for complexdesigns as well as fast and easy signal pass-through routing.

By means of utilizing the configurable and programmable FPGA I/O interface of theCHILImodule, the system developer can optionally Arrange the CHILImodule device pinout for making the base board routing easy and

straightforward Route the CPU resources to selected external peripherals and connectors as required by

the rest of the system Control the system performance by sharing the system load between the CPU

peripherals and FPGA IP block implemented peripherals

Extend or upgrade system capabilities by moving the required digital hardware intoFPGA domain by means of soft IP blocks

Interface custom circuitry directly to the CHILImodule without using external glue-logicdevices

Increase performance of the system by allocating selected functionality to FPGA IPblocks (hardware acceleration)

The clock signal for the FPGA device is generated internally in the CHILImodule. In additionto this default clocking mode, two external clock signals can be connected to theCHILImodule FPGA device.


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The integrated FPGA device can be programmed by Altera ByteBlaster programmer interface connected directly to the CHILImodule uploading the FPGA image to the module directly from external source (Ethernet, MMC

Card etc.)

SoftwareIn addition to the module hardware, the CHILImodule devices come with an extensive setof software, including Bootloader FPGA configuration loader software Operating system File system Device drivers for built-in peripherals and a few external devices FPGA IP blocks (with source code)

For further information, please consult the CHILImodule software documentation.


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APPLICATIONSThe application of the CHILImodules (CDM15400 or 15401) include Wireless Mobile Communication Devices

Industrial Measurement Systems User Interfaces Machine Interfaces Home Automation Handhelds (GPS, POS Terminal) Consumer Electronics Office Equipment System Routers and Gateways Telecommunications

Note that the list above is not meant to be extensive or exclusionary. Thanks to theirflexibility, configurability and the rich set of features, the CHILImodule devices fit into a

broad range of applications across various product areas.

See also section GENERAL DESCRIPTION starting from page 11 and section APPLICATIONSstarting from page 19 for more information.


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ORDERING INFORMATIONTABLE 1ORDERING INFORMATION

CHILImodule Device Type

Antennas

Temperature

Range

Ordering

CodeCDM15401 (CHILImodule Standard)(Tray of 6 devices)

(NA) -25C...+70C CDM15401-A000-C000-B00-C-1

(NA) -40C...+85C CDM15401-A000-C000-B00-I-1

CDM15400 (CHILImodule Professional)(Tray of 6 devices)

Built-In -25C...+70C CDM15400-A001-C001-B01-C-1

Built-In -40C...+85C CDM15400-A001-C001-B01-I-1


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FUNCTIONAL BLOCK DIAGRAMThe CHILImodule devices comprise of mixed embedded design implemented in highdensity interconnect (HDI) substrates. The design contains mixed type signaling, including

power supplies, high-speed digital signals and RF-signals at 2.4GHz.

Intel XScalePXA270

416MHz/312MHzFLASH

16/32/64MBytes

Supervisory, Reset

Li Battery Charger

Fuel Gauge

USB 1.1 +USB 2.0 OTG Support

SDRAM32/64MBytes

Real Time Clock (RTC)

Power Control

EEPROM 32kbit

SystemReset

InternalSupplyVoltages

Field ProgrammableGate Array (FPGA)

Totally116ProgrammableI/O

Pin

s

SRAM256kB

WishboneBus IF

ZigBee(802.15.4)

WLAN

(802.11b)

USB 1.1(Client, Host, OTG)

To Ext. Antenna

I2C

SDIO

RTC_PWR(3.0V)

Li-Ion/Li-PolymerBattery

VCC (3.5...5.5V)

Ext. CLK1

JTAG/IEEE 1149.1

Altera ByteBlaster II

CHILImodule Professional

CDM15400

USB VBUS

ADJ_CHRG_TIMEADJ_CHRG_CURR

FAULT#NTC

CHRG#

VCC_OUT (3.3V/0.7A)

MR#

CLK

48MHz

IP

IP

IP

(Signal Routing)

Opt.WishboneBus

Ext. CLK2

Charge_EN

Status

ID

PWR_CTL

RDY

Address Bus

Data Bus

PWR_STAT

RSO#

JTAG/IEEE 1149.1

PowerSupply

PowerPath

Adj.

Backup Batt Reg. V(BKBT)

Zi:Zo

RegPWR

Temp

SRAM 56Bytes

EEPROM

Capacity

Temp

EN_CCHRG_CURRCHRG_RATE_DET

To Ext. AntennaZi:Zo

Int. Ant.

Int. Ant.

ZigBee_EXT#

WLAN_EXT#

I, U

VCC_BAT (3.3V) ZigBee IF

WLAN IF

FIGURE 1FUNCTIONAL BLOCK DIAGRAM -CHILIMODULEPROFESSIONAL

The CHILImodule Standard (CDM15401) is similar to the CHILImodule Professional exceptthe following main differences The CPU operating frequency is lower (312MHz) The size of the FPGA is smaller (EP1C4) The FLASH memory capacity is limited to 16MBytes

The SDRAM memory capacity is limited to 16MBytes There are no wireless interfaces (WLAN, ZigBee) available There is no Lithium battery support (charger, fuel gauge) available

Due to the smaller memory and FPGA resources, the CHILImodule Standard support forFPGA/IP peripherals and graphics libraries may be somewhat limited compared to theCHILImodule Professional.


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HARDWARE

Terminal Functions

Pin Diagrams

The I/O pins (BGA ball pads) have been dispersed across the CHILImodule deviceaccording to their functionalities to provide an easy-to-route land pattern for the basesubstrate (printed circuit board) layout design.

Top View

Li+Li-

+5V

1 5 1 0 15 2 0 2 5

29

58

88

119

127

135

143

151

159

167

175

183

191

199

207

23 8

26 8

297

28

57

87

11 8

12 6

13 414 2

15 0

15 8

16 6

17 4

18 2

19 0

19 8

20 6

23 7

26 7

29 6

32 43 00 3 05 3 10 315 3 20

RFUPins Reserved for Future

+3.3VOUT

2 15 220 225 2 30

95 1 00 1 05 1 10

ByteBlaster II InterfaceMMC/SD/SDIO Interface

Power Supply Input (+5V)

Li Battery Interface

Device Controland Status Interface

FPGA External Clock Inputs

+3.3V Output

+3.3V Output

+3.3V Output

I2C Interface

+3.3V Output

PXA JTAG Interface

USB Host/Client Interface

RSO#RDY

FPGA JTAG Interface

FPGA_IOBidirectional FPGA I/O

130

138

146

154

162

170

178

186

194

131139

147

155

163

171

179

187

195

+3.3VOUT

+3.3VOUT

Digital GroundDGND

Cont. Pwr Interface+3.3V (Cont.)

FIGURE 2P IN DIAGRAM

Digital ground (DGND) is common for both power supply and I/O signals. Note also, thatthe pins that have been reserved for future should be left floating.

Pin Descriptions

The pin / signal descriptions of the CHILImodule device are in the following table. See thenotes [1], [2], [3] below the table.

TABLE 2P IN DESCRIPTIONS

Not Connected Pins

Symbol Pin Type Reset Description

NC 1 Reserved for future use - leave pin unconnected

NC 2 Reserved for future use - leave pin unconnectedNC 3 Reserved for future use - leave pin unconnectedNC 4 Reserved for future use - leave pin unconnected

NC 5 Reserved for future use - leave pin unconnectedNC 6 Reserved for future use - leave pin unconnected





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Pow er Supply Outputs


VCC_OUT 9 O +3.3V supply voltage outputVCC_OUT 66 O +3.3V supply voltage output


VCC_OUT 123 O +3.3V supply voltage output

VCC_OUT 124 O +3.3V supply voltage outputVCC_OUT 126 O +3.3V supply voltage outputVCC_OUT 131 O +3.3V supply voltage output


VCC_OUT 212 O +3.3V supply voltage outputVCC_OUT 213 O +3.3V supply voltage outputVCC_OUT 225 O +3.3V supply voltage output



Continuous Pw r Output

VCC_BAT 178 O +3.3V continuous low power output

Module Supply Voltage Input

VCC 202 P Module supply voltage input - main power supply of +5V

VCC 210 P Module supply voltage input - main power supply of +5VVCC 239 P Module supply voltage input - main power supply of +5V

VCC 269 P Module supply voltage input - main power supply of +5VVCC 297 P Module supply voltage input - main power supply of +5V

VCC 298 P Module supply voltage input - main power supply of +5V

Digital Ground

DGND 31 G Digital ground - common for all power supplies

DGND 33 G Digital ground - common for all power suppliesDGND 35 G Digital ground - common for all power supplies


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DGND 57 G Digital ground - common for all power suppliesDGND 59 G Digital ground - common for all power suppliesDGND 61 G Digital ground - common for all power supplies


























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timer runs out or the input supply of the device is removed, theCHRG# pin is forced to high impedance state. A temperaturefault causes this pin to blink.

FAULT 144 O Battery fault status output. This pin is logic high if a shortedbattery is detected or if temperature fault is detected. Atemperature fault occurs with the temperature monitor circuit is

enabled and the thermistor temperature is either below 0C orabove 50C (typical).

IDET 151 I Charge rate detection threshold. Connecting a resistor from thispin to DGND programs the charge rate detection threshold. IfIDET is left floating, charge rate detection threshold is 100mA.

NTC 169 X Input to NTC (negative temperature coefficient) thermistortemperature monitoring circuit. NTC shall be tied from this pinto DGND and a resistor of equal value from NTC pin to VCC.The NTC function may be disabled by connecting this pin toDGND.

EN_CCHRG_CURR 170 I This signal programs the charge current.If EN_CCHRG_CURR is driven low, the charge current dependson parallel connection of internal and external resistors. If theEN_CCHRG_CURR is driven high, the external resistorconnected to the ADJ_CHRG_CURR pin defines the charge

current.

Pow er Path Selection


PWR_CTL 175 I Power supply path selection signal. Driving CTL signal highforces the main power supply (+5V) to be selected as a powersupply. If CTL is driven low or left floating, the CHILImoduleuses the higher voltage of the main power supply or batterycell.

ByteBlaster II Connections


FPGA_CE# 311 I Output control signal from Cyclone FPGA that drives low whenconfiguration is complete.

FPGA_CONFIG# 308 I Cyclone FPGA configuration control input

FPGA_CSO# 283 O Output control signal from Cyclone FPGA to serial configurationdevice in AS configuration for enabling the serial configurationdevice

FPGA_ASDO 307 O Output control signal from Cyclone FPGA to serial configurationdevice in AS configuration

FPGA_CONF_DONE 310 OD Open drain FPGA configuration status output (internally pulled-up with 10k)

FPGA_DATA0 281 I Cyclone FPGA data inputFPGA_DCLK 309 I/O Cyclone FPGA clock signal (input in Cyclone PS configuration,

output in Cyclone AS configuration)

FPGA Clock Signals


FPGA_CLK1 223 I External FPGA clock signal input (connected to Cyclone CLK1pin)

FPGA_CLK2 224 I External FPGA clock signal input (connected to Cyclone CLK2pin)

FPGA I/ O Signals


FPGA_IO000 315 B Programmable I/O signal from the FPGA [4]FPGA_IO001 314 B Programmable I/O signal from the FPGA [4]

FPGA_IO002 313 B NOTE: Optional DEV_OE input pin for overriding all tri-stateson the device in addition to general purpose I/O pin.1.8V only logic levels. [4]

FPGA_IO003 285 B NOTE: Optional DEV_CLRn input pin for overriding all clears onall device registers in addition to general purpose I/O.1.8V only logic levels. [4]


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I2C Interface


PXA_SCL 216 OD Open drain I2C bus clock signal (internal pull-up)PXA_SDA 215 OD Open drain I2C bus data signal (internal pull-up)

FPGA JTAG In terfaceFPGA_TCK 276 I Boundary Scan (IEEE 1149.1) clock signal to FPGAFPGA_TMS 304 I Boundary Scan (IEEE 1149.1) mode selection signal for FPGA

FPGA_TDI 303 I Boundary Scan (IEEE 1149.1) data input to FPGAFPGA_TDO 302 O Boundary Scan (IEEE 1149.1) data output from FPGA

PXA JTAG I nterface


PXA_TRST# 249 I Boundary Scan (IEEE 1149.1) reset signal to PXA270PXA_TDO 251 O Boundary Scan (IEEE 1149.1) data output from PXA270

PXA_TCK 279 I Boundary Scan (IEEE 1149.1) clock signal to PXA270PXA_TDI 305 I Boundary Scan (IEEE 1149.1) data input to PXA270

PXA_TMS 277 I Boundary Scan (IEEE 1149.1) mode selection signal for PXA270

USB Client InterfaceSymbol Pin Type Reset Description

USB_VBUS0 214 P External USB bus voltage (+5V) for battery chargerUSB_VBUS1 245 P External USB bus voltage (+5V) for battery charger

PXA_USBC_N 221 B USB Client port negative pin of differential pairPXA_USBC_P 220 B USB Client port positive pin of differential pair

PXA_USBH_N 219 B USB Host controller port positive pin of differential pairPXA_USBH_P 218 B USB Host controller port positive pin of differential pair

PXA_USBHPEN1 217 O Signal to control external USB bus power supply for USB Hostimplementations

PXA_USBHPWR1 247 O Signal to monitor USB bus power supply faults

Module Control Signals


PXA_RDY 275 I Variable latency input signal of the PXA270 for inserting wait

states (internal pull-up). Also connected to FPGA deviceL WaitH VLIO is ready

MR# 160 I Master reset input signal for the device (internal pull-up)

RSO# 306 OD Open drain reset output signal (internally pulled up by 1M toVCC_BAT)

Notes:

[1] Pins named as PXA_* have been routed directly to the PXA270 device pins[2] To avoid permanent damages, the charge current is limited to 1.35A. If operating

temperature is high, you should probably decrease the charge current rate.[3] P = Power, G = Ground, I = Input, O = Output, OD = Open-drain, B = Bi-directional,

X = Passive[4] Pins named as FPGA_* have been routed directly to the Altera Cyclone device pins

Note

The I/O pin leakage current of Altera Cyclone before and during configuration may be higherthan during the normal operation.

In order to ensure low level at FPGA driven I/O signals before and during configuration,Altera recommends using pull-down resistors (2k max.). Please, consult Altera Cyclonedocumentation for further details.


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In addition to the BGA ball pad connections at the bottom of the CHILImodule devices, theCHILImodule Professional (CDM15400) offers built-in wireless connections (WLAN, ZigBee).

Following antenna options are available for the system designer Built-In chip type antenna for WLAN

Built-In chip type antenna for ZigBee Coaxial antenna connector (Hirose U.FL) for connecting external WLAN antenna Coaxial antenna connector (Hirose U.FL) for connecting external ZigBee antenna

WLAN(IEEE 802.11)

ZigBee(IEEE 802.15.4)

FIGURE 3ANTENNAS AND RF CONNECTORS

Chip type antennas are good solution for compact system designs and for relatively shortoperating ranges. An external antenna may be connected to the CHILImodule device tofurther extend the operating range or for the applications that require sealed conductiveenclosures. The antenna connections (coaxial connectors) locate under the top cover of thepackage.

Software device drivers control antenna selection. Note, that due to antenna multiplexerboth internal and external antennas cannot be used at the same time.

Functional Description

General

The CHILImodule combines the high performance ARM9 based 32-bit RISC processor (IntelXScale PXA270), FLASH/SDRAM memories with the flexible FPGA device and completepower management in a small size surface mounted SiP package. The device requires onlysingle supply voltage for the operation. The processor is characterized by its low power andhigh performance in addition to rich set of peripherals and features.

In addition to capability of driving wired peripherals the CHILImodule Professional alsocontains support for Lithium-Ion or Lithium-Polymer batteries and provides modern wirelesscommunication interfaces of IEEE 802.11b (WLAN) and IEEE 802.15.4 (ZigBee). In addition

to the integrated antennas, the device provides coaxial connectors for using externalantennas.

The CHILImodule comes with bootloader, operating system and full set of libraries anddevice drivers to help the user to get the products on markets fast.

Transferring your equipment into mobile domain could not be easier: it is only matter ofconnecting a Lithium-Ion or Lithium-Polymer battery to the CHILImodule. TheCHILImodule contains all battery support circuitry, including battery charger and fuelgauge. External power supply of the CHILImodule is used to provide power for chargingthe battery.


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The CHILImodule is designed to be used in a wide range of embedded applications,including mobile terminals, user interfaces, measurement systems and automationcontrollers, industrial and commercial solutions etc. Multiple communication options allowthe CHILImodule to be easily used as a smart link between different system levels (likeInternet and low level sensor networks, as an example).

RS232

Binary I/O

CHILImodule ProfessionalBinary I/O

+3.3V


Li+ LCD +Touchscreen

+3.3V

SD Card

Heating


TemperatureWLANHumidity

GPS


LCD +Touchscreen

WLANLi+

FIGURE 4SIMPLE APPLICATION EXAMPLES


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The CHILImodule device may be used as a gateway or router between various networkinfrastructures (wireless or wired configurations). Mass storage card (like SD Card may beused for data logging or reporting applications).

ZigBee

CHILImodule ProfessionalBinary I/O

WLAN

RS232


RS485

CAN

SD Card

FIGURE 5NETWORK GATEWAY/ ROUTER APPLICATIONS

The CHILImodule based applications may access standard Ethernet networks by means ofeither the IP MAC or external MAC+PHY device depending on the choice.

Ethernet10/100Base-T

Actuators


Sensors

ETHMAC+PHY

FIGURE 6ETHERNET CONNECTIVITY BY EXTERNAL MAC+PHY DEVICE

The CHILImodule contains features and peripherals that allow system designer to provideequipment with audio subsystems and/or graphical user interfaces fast and easy.

SP


CODEC

AMP

ZigBee

Li+ USB

CMOSImage Sensor

CHILImodule ProfessionalOptics

LCD +Touchscreen

WLAN

FIGURE 7MULTIMEDIA APPLICATION EXAMPLES

In industrial systems, the CHILImodule may function as a system monitor, controller orregulator. The choice of the role is mainly matter of the application software. Thanks to its


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low power, the CHILImodule device does not require heat sinks or fans to keep it cool.Therefore the module may be used in applications that will be used in harsh environmentsas well as light, portable equipments.

USB


Sensors

DRV

M

Motor

ZigBee

ETHMAC+PHY


FIGURE 8SYSTEM CONTROLLER APPLICATION

The CHILImodule devices may be used in complex networks or measurement systems dueto the high performance and adaptability of the device.

RS232

AnalogInputs


Binary I/O

A

D

RS422

CANOpen

GSM Modem

ETHPHY

WLAN

+3.3V


FIGURE 9ADVANCED MEASUREMENT SYSTEM

As a summary: the CHILImodule devices offer power of high performance CPU with theflexibility of the field programmable gate array logic (FPGA) and the freedom of the wirelesscommunication interfaces of WLAN and ZigBee in a small package.

Reset Input / Output

The CHILImodule

has single external master reset control input (MR#). Driving the MR#line low forces the processor to cold-reset. During the cold reset, the SRAM content of theprocessor will be maintained.

TABLE 3MR#INPUT SPECIFICATIONS

Symbol Parameter Conditions Min Typ Max Units

VinL(MR#) MR# Input Low Voltage Input leakage current < 1A 0.4 V

VinH(MR#) MR# Input High Voltage Input leakage current < 1A 1.6 5.5 V


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TABLE 4MASTER RESET MR#

MR# Description

Low Driving MR# low forces the processor to resetHigh Keeping the MR# high has no effect to the CHILImodule

The MR# line is internally pulled up by 100k in the CHILImodule, so the MR# input maybe left floating.

There is an open drain reset output signal (RSO#) available from the CHILImodule. TheRSO# signal will be driven low When main power supply (VCC) is first applied to the CHILImodule device with no

backup battery When main power supply is removed in configuration with no backup battery If the backup battery voltage falls below 2.25V threshold when the main power supply is

off or out of regulation If the MR# input is driven low

The reset output RSO# may be used for resetting the external circuitry (peripherals etc.) ofthe CHILImodule. The open drain signal RSO# has weak (1M) internal pull-up toVCC_BAT in the CHILImodule. Care should be paid to not to load RSO# signal excessively.

TABLE 5RSO#OUTPUT SPECIFICATIONS


VOL(RSO#) RSO# Output Low Voltage Iout < 1mA 0.4 VIl(RSO#) RSO# Output High Leakage

Current0.2 A

The RSO# has timer that delays release until 65 ms (typ.) after the battery voltage exceeds2.3V when the main input voltage is above 2.4V. If main input voltage is below 2.4V, when

the battery voltage exceeds 2.3V, RSO# deasserts immediately with no 65 ms delay.When MR# goes low, RSO# asserts for a minimum of 65 ms. The RSO# deassert delay isminimum 61 ms over the specified temperature range.

Pow er SupplyThe CHILImodule (CDM15400/CDM15401) operates from a single supply voltage rail. Thedevice contains all the power management circuitry to create internally needed voltagesfrom the main input voltage. The power supply of the module fully supports dynamicalpower control options of the processor to further decrease power consumption in power-down and sleep modes. Note, as the 32kHz crystal is not connected to processor, allprocessor sleep modes are not supported. Please, consult Intel XScale processor

documentation for further details.Lithium-Ion or Lithium-Polymer battery (4.2V) can be directly connected to theCHILImodule Professional (CDM15400) for implementing battery-powered systems. TheCHILImodule Professional selects automatically external power supply input (VCC) insteadof the battery, if the voltage is present for maintaining the battery capacity.

The processor of the CHILImodule can resolve the automatically voltage source by readingthe internal PWR_STAT signal level.


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TABLE 6POWER SOURCE IN USE

PWR_STAT Description

Low VCC input is selected as power supply (wall adapter or external power supply is supplying loadcurrent)

High Battery is selected as power supply (battery is supplying load current)

The power source to be used may be selected (forced) by the external signal PWR_CTL (seethe table below).

TABLE 7POWER SOURCE SELECTION BY EXTERNAL SIGNAL

PWR_CTL Description

Float See note [2]Low If the VCC is present, it will be selected to supply load current. If VCC is not connected the

battery is selected to supply load currentHigh Battery is forced to be disconnect from the system and VCC input is selected to supply load

current [1]

[1] Only when the battery voltage is higher than the VCC voltage, will taking PWR_CTLlow switch back to battery power, otherwise the VCC stays connected

[2] A 3.5 A internal pull-down current on the PWR_CTL pin will insure a logical low levelinput if the PWR_CTL is left floating

The VCC input voltage of the CHILImodule is continuously monitored. Two separate VCCinput voltage thresholds have been defined for adjusting system response for low inputvoltage levels BATT_LOW# (higher threshold level) BATT_FAULT# (lower threshold level)

Signal BATT_LOW# (active-low) is connected to PXA270 GPIO103, and this signal may beused to detect low input voltage levels by the software. Note, that the BATT_LOW# signaldoes not automatically create any system events, but desired operations may be initializedby software.

Active-low output BATT_FAULT# indicates that the main power is low or has been removedfrom the system. BATT_FAULT# is connected to nBATT_FAULT pin of the CPU, and itindicates that the main regulator of the CHILImodule may go out of regulation due to lowinput voltage.

Assertion of the BATT_FAULT# signal causes CPU to enter sleep mode 1 or, if CPU registerPMCR[BIDAE] is set, forces an imprecise-data abort, which cannot be masked (for more

1Note though, that the CHILImodule has no 32.768kHz oscillator available for the sleep modes, but all operation isbased on 13MHz oscillator.


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information, please consult the PXA270 documentation). Once BATT_FAULT# has beenasserted, the CPU recognizes only GPIO0 or GPIO1 as wake-up sources.

TABLE 8BATT_LOW# AN D BATT_FAULT#SPECIFICATIONS


BATT_LOW# VCC Input Voltage LowThreshold

3.51 3.6 3.69 V

BATT_FAULT# VCC Input Voltage FaultThreshold

3.02 3.15 3.28 V

The CHILImodule provides regulated 3.3V output voltage (VCC_OUT) for powering thesurrounding circuitry. The maximum current of the VCC_OUT is 700mA.

NoteThe 3.3V output voltage is turned off when CHILImodule device enters one of the followingoperating modes Reset asserted (by driving the MR# pin) Internal watchdog reset asserted

Entering various sleep modes

When device returns to normal mode operation, the 3.3V output is turned on again.

Turning power off and on again typically resets external devices. Turning powerautomatically off during the sleep modes helps saving energy thus extending operation timein battery powered systems.

Additionally, the VCC_BAT pin of the CHILImodule sources continuous 3.3V output forpowering up the debugger interface (see later in this document). The VCC_BAT is capable ofproviding up to 15 mA source current. The VCC_BAT voltage is present, when theCHILImodule is powered from either VCC (primary voltage source) or Lithium battery cell.If primary voltage is disconnected, the VCC_BAT is automatically generated from battery

voltage.Note, that typically debugger interface should be powered from VCC_BAT instead of theVCC_OUT, as the VCC_BAT voltage is present and independently of the CHILImoduleinternal power supply regulator state.

TABLE 9VCC_OUT AND VCC_BATSPECIFICATIONS


VVCC_OUT Regulated Power Supply OutputVoltage

IVCC_OUT < 500mA 2.97 3.3 3.63 V

VVCC_BAT Continuous 3.3V Power SupplyOutput

IVCC_BAT < 10mA 3.2 3.3 3.4 V

The CDM15400 device offers integrated power management and charge monitor for theexternal battery. In addition to this, the CHILImodule has built-in battery charger that iscapable for supplying up to 1.35A charge current to the battery from the external powersupply. The CHILImodule may provide charge current while powered from the USBinterface, but the charge current rate is lower because of the limitations of USB interface.

Note, that the maximum allowable charge current rate depends on the system operatingtemperature range. Typically, maximum charge current output falls in the range of1.0...1.35A.


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Default charge current rate depends on the power supply in use If the power is drawn from the external power supply, the CHILImodule provides

463mA default charge current If the power is drawn from the USB interface only, the CHILImodule provides 93mA

default charge current depending on the application software from the connected USB

bus supply voltage (VBUS).

These default charge current rate may be modified with an external resistor (see chapter LiBattery Charging starting from page 52).

Note, that the input voltage (VCC) should be in the range of +4.5V...+5.5V in order to beable to charge the Lithium-Ion battery.

CDM1540x

CHILImodule

LI+

LI-

Power Supply

Processor

PWR_STAT

3.7/4.2V Lithium Cell(for the CDM15400 only)

3.0V Li

RTCPWR

VCC (+3.5...5.5VDC)VCC

GND

VUSBVUSB

PWR_CTLPWR_CTL

BatteryCharger

(CDM15400)

+3.3VDC/700mA

+3.3VDC/10mA

VCC_OUT

VCC_BAT

FIGURE 10 POWER SUPPLY OPTIONS FOR THE CDM15400 DEVICES

The CHILImodule contains real-time clock/calendar for time keeping applications. The RTCrequires external 3.0V battery (for example a coin cell battery) backup to maintain the timeduring power-down and sleep modes.

TABLE 10 RTC_PWR SPECIFICATIONS


VRTC_PWR Input Voltage 1.3 3.0 3.7 V

IRTC_PWR RTC_PWR Current VCC OFF; Oscillator ON 1.4 AIR_RTC_PWR Data Retention Current VCC OFF; Oscillator OFF 10 100 nA

Il_RTC_PWR Leakage Current VCC ON 25 100 nA

Note, that the RTC_PWR power supply is used for maintaining time and calendarinformation only if the main power supply (VCC) is not in use.

Low power consumption of the real time clock allows using small size batteries fortimekeeping during power-down. As an example, the lifetime of the battery (1632 typebattery with 120mAh capacity) would be in a range of about 10 years, depending mainly onthe temperature.


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ProcessorThe CHILImodule is based on low power, high performance Intel XScale processor.

The main features of the PXA270 processor are Based on Intel XScale Microarchitecture with Intel Wireless MMXTM Technology

7 stage pipeline 32kB data and instruction cache Extensive data buffering 256kBytes internal SRAM (Static RAM) for high speed code or data storage preserved

during low-power states Integrated hardware debug features (IEEE JTAG interface with boundary scan) Real time clock (RTC) Operating system timers Integrated LCD controller Low power (less than 500mW typical internal dissipation) Dynamic frequency and voltage management

Intel XScale is capable of providing rich peripheral set for both industrial and mobileapplications, including AC97 audio port I2S audio port USB Client/Host/OTG controller Three high speed UARTs (two with hardware control) FIR and SIR infrared communications port SD/MMC Card support PC Card/Compact Flash Card support Memory Stick card controller SPI bus Two I2C controllers

Four pulse-width modulators (PWM) Keypad interface with both direct and matrix keys support Most peripheral pins double as GPIOs

Direct Connections from P rocessorSome of the processor interfaces have been connected directly to the CHILImodule pininterface for easiness.

Direct interface connections include I2C bus signals (SDA, SCK) SDIO bus signals (for direct interface to MMC/SD Card socket) USB bus signals (for direct interface to USB Client type connector)

RDY signal (for fast asynchronous interfaces)

The I2C bus signals are open drain type signals (SDA, SCK) for connecting externalperipherals to the CHILImodule. The I2C SDA signal have been used for system recoveryfunctionality as described in the section FPGA Recovery on page 67.

The processor SDIO interface signals have not been connected to FPGA but provide directglueless module interface for the SD/MMC Memory card connectors.

The RDY signal may be utilized for fast asynchronous accesses to external devices (forexample, to external Ethernet MAC/PHY devices). The RDY signal is also connected to the


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FPGA device so, that the RDY signal of the CPU may be controlled by both external deviceand FPGA (e.g. by FPGA IP devices).

CHILImoduleCDM1540x

RDY

FPGA

+3.3

1k

1 PXA_RDY

CPU

t =5nsPD

FIGURE 11 RDY CONNECTIONS FOR VARIABLE LATENCY I/ OINTERFACE

FLASHThe CHILImodule devices offer up to 64MBytes Intel Strata NOR Flash memory capacity forprogram code storage and Flash file system. The Common Flash Interface (CF) compatibleFlash memory is connected to processor by 32-bit wide data bus.

The initial access speed of the Flash memory is 85 ns. Synchronous burst-read mode clock-to-data output delay is 17s, and asynchronous-page read cycle is 25 ns. Programmingspeed of the Flash is 7 s/byte (typ.).

The Flash memory offers following security features for the applications

128-bit protection register 64-bit unique factory device identifier 64-bit user programmable OTP registers Additional 2048 user-programmable OPT bits Selectable OTP space in main array Individual block lock-down Block erase/program lockout during power transitions

Flash memory has asymmetrically-blocked architecture with four 32kByte parameter blocksand 128kByte main blocks. The Flash memory has guaranteed minimum of 100K erasecycles per block.

Flash memory has been connected to XScale PXA270 processor address space to providefollowing memory map for user applications.


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0x0000 0000

0x0400 0000

0xA000 0000

0xA400 0000

0x0000 0000

0x0100 0000

0xA000 0000

FLASH16 MBytes

0xA100 0000

CDM15400 CDM15401

SDRAM16 MBytes

FLASH64 MBytes

SDRAM64 MBytes

FIGURE 12 MEMORY MAP -CDM15400/ CDM15401

SDRAMFor data storage and program code execution, the CHILImodule devices offer up to64MBytes of SDRAM memory. The SDRAM memory is connected to processor by 32-bit widedata bus.

The access speed of the SDRAM memory is 10 ns.

For system memory map, please refer the Figure 12 Memory Map - CDM15400/CDM15401.

EEPROMThe CHILImodule contains totally 32kBits non-volatile, electrically erasable memory(EEPROM) for application software data and configuration storage.

EEPROM memory has been connected to I2C bus, and the device slave address is 0x00.

REAL TIME CLOCKThe CHILImodule contains fully binary-coded decimal (BCD) real-time clock/calendar(RTC). The leap year compensation of the real time clock is valid up to year 2100.The RTCcontains 56 bytes of battery-backed, non-volatile RAM memory (NVRAM) for additional datastorage.

An external 3.0V power supply (battery) is needed for timekeeping during the power-down(see also section Power Supply on page 15).

RTC device has been connected to I2C bus, and the device 7-bit slave address is x1101000.


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FPGAThe CHILImodule device interface comprises of large Field Programmable Logic Array(FPGA) device that has great impact of the CHILImodule's flexibility and adaptability invarious systems - the move from 'hard' to 'soft' design content opens up new horizons for

the designer.

Totally, there are 116 freely programmable I/O lines in the CHILImodule in addition to thefixed interface already mentioned. The direction, operation and functionality of these I/Olines is defined by the FPGA configuration (e.g. FPGA image), that can be loaded/updated inthe CHILImodule during the boot sequence. All programmable I/O lines operate on 3.3Vlogic levels, except FPGA_IO002 and FPGA_IO003 that operate on 1.8V logic levels.

Depending on the CHILImodule device type, there are two FPGA sizes available accordingto the following table.

TABLE 11 FPGACONFIGURATIONS

CHILImodule Device FPGA DeviceCHILImoduleStandard

CDM15401

Altera Cyclone EP1C4 (4 kLE, up to 78 336 RAM Bits)

CHILImoduleProfessionalCDM15400

Altera Cyclone EP1C12 (12 kLE, up to 239 616 RAM Bits)

The FPGA device of the CHILImodule forms a flexible interface between the CHILImoduleinternal circuitry and external peripherals. The built-in Altera Cyclone FPGA provides all thebenefits of programmable logic to the system designer.

Both FPGA devices (EP1C4 and EP1C12) support a variety of single-ended I/O standardssuch as LVTTL, LVCMOS, PCI etc. They also offer differential I/O support via LVDS andRSDS I/O standards. Each channel is capable of operating LVDS signals at up to 640 MBit/s.

With up to six outputs from two phase-locked loops (PLLs) per device and a hierarchicalclocking structure, Cyclone FPGAs offer extensive clock management circuitry for complexdesigns as well as fast and easy signal pass-through routing.

By means of utilizing the configurable and programmable interface of the CHILImodule, thesystem developer can optionally Arrange the CHILImodule device pinout for easy and straightforward routing of base

board Route the CPU resources to selected external peripherals and connectors as required by

the system Control the system loading by sharing peripherals between the CPU and FPGA IP block

implemented peripherals Extend or upgrade system capabilities by moving the required digital hardware into

FPGA domain by means of soft IP blocks

Interface custom devices directly to the CHILImodule

with no glue-logic Increase performance of the system by allocating selected functionality to FPGA IP

blocks (hardware acceleration)

The default clock signal for the FPGA device (CLK0 = 48MHz) is generated internally in theCHILImodule. In addition to this default clocking, external clock signal can be connected tothe CHILImodule.


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Note:

As always with programmable devices, attention should be paid to checking the I/Oconfiguration of the FPGA device (especially signal directions).

False configuration of FPGA may prevent the CHILImodule device from booting or updating

the FPGA configuration (deadlock) (see also section I2C starting on page 47).

Loading CPU or other devices connected to FPGA device excessively (e.g. connecting CPUoutputs to FPGA outputs) may cause permanent damages to the CHILImodule device.

I/ O Standards

Altera Cyclone device I/O blocks (IOE) can support many features, including: Differential and single-ended I/O standards 3.3V, 64- and 32-bit, 66- and 33-MHz PCI compliance Output drive strength control Weak pull-up resistors during configuration

Slew-rate control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors in user mode Programmable input and output delays Open-drain outputs JTAG (Joint Test Action Group) boundary scan test (BST) support

Cyclone device input / output element (IOE) contain a bidirectional I/O buffer and threeregisters for complete embedded bidirectional single data rate transfer.

The VCCIO pins of the Altera Cyclone device have been internally connected to +3.3VDC. This

arrangement allows the IOEs of the device to support the I/O standards described in thefollowing table.

TABLE 12 I/ OSTANDARDS OF THE CHILIMODULE/ ALTERA FPGA

Inpu t Signal Output Signal

1.5V 1.8V 2.5V 3 .3V 5.0V 1.5V 1.8V 2.5V 3.3V 5.0V

X[5] X[1] X X[2] X[3] X[3] X[3] X X[4]

[1] With this arrangement, the VCCIO supply current will be slightly larger than expected

[2] External resistor and the internal PCI clamp diode are required for the Cyclonedevice to be 5V tolerant

[3] 3.3V tolerant inputs are required for the 1.5V, 1.8V and 2.5V devices. Note, thatCHILImodule pins FPGA_IO002 and FPGA_IO003 use 1.8V logic levels.

[4] Cyclone device can drive a device with 5V LVTTL inputs but no 5V LVCMOS inputs

[5] Note, that CHILImodule pins FPGA_IO002 and FPGA_IO003 use 1.8V logic levels

For more information about the Altera Cyclone I/O levels and features, please consult theAltera Cyclone documentation.


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FPGA Clock Signals

There are three main options for using clocks with the FPGA device Built-in default clock of 48MHz External clock signal FPGA_CLK1

External clock signal FPGA_CLK2

The built-in default 48MHz clock signal is connected to dedicated EP1C04/EP1C12 FPGAclock input CLK0.

There are two dedicated clock inputs in the CHILImodule device (FPGA_CLK1 andFPGA_CLK2) that have been connected to FPGA clock inputs CLK1 and CLK2 respectively.

CDM1540x

CHILImodule

Altera CycloneFPGA

CLK2

CLK1

External Clock Oscillator

GPIO

CLK048 MHz

FPGA_CLK1

FPGA_CLK2

FIGURE 13 FPGACLOCK OPTIONS

Although clock signals can be connected to module via standard I/O pins of the FPGAdevice, using dedicated clock signal inputs (FPGA_CLK1, FPGA_CLK2) is recommended sincethese clock inputs drive the global clock network in Altera Cyclone device.

The global clock network can provide clocks for all resources within the device (IOEs, LEs,and memory blocks). The global clock lines can also be used for control signals, such asclock enables and synchronous and asynchronous clears, fed from the external pin, or DQSsignals for DDR SDRAM or FCRAM interfaces. For more information, please consult theAltera Cyclone FPGA documentation.

Note also, that any FPGA I/O pin (FPGA_IO[00...115]) may be used to connect externalclock signal to FPGA internal structure, but using these pins may lead to increased delays inclock signal routing.


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Using External Configuration Memory

Sometimes, the system designer desires to use external configuration memory, and skip theFLASH based FPGA image storage and software based FPGA configuration concept. Thisrequires adding an external serial configuration device to the system and using

automatically FPGA configuration scheme instead as shown in the following figure.NoteUsing external memory device for FPGA configuration is not supported as default. Being ableto use external configuration memory requires custom version of the CHILImodule. Please,consult CHILIdevices International for such a customization if needed.

Typically, using built-in Flash memory and associated FPGA configuration loader softwareshould be the most cost efficient method for FPGA configuration.

CDM1540x

CHILImodule

Altera CycloneFPGA Device

FPGA_CONF_DONEFPGA_CONFIG#FPGA_CE#FPGA_DATA0FPGA_DCLKFPGA_CSO#FPGA_ASDO

AlteraSerial Configuration Device

3.3VDGND

DATA0DCLKCSO#

ASDOGND

VCC

FIGURE 14 CONNECTING EXTERNAL CONFIGURATION DEVICE

Serial configuration devices for the CHILImodule have specified in the following table.

TABLE 14 ALTERA SERIAL CONFIGURATION DEVICES

Module Type Serial Configuration Device

CDM15401 EPCS1 (1 MBit capacity) for EP1C4 FPGA deviceCDM15400 EPCS4 (4 MBit capacity) for EP1C12 FPGA device

Using ByteBlaster II Download Cable

The Altera ByteBlaster II download cable may be used to program the FPGA device inside of

the CHILImodule

.As mentioned above, note that due to SRAM technology of the FPGA, this configuration willbe lost during power-down. To keep the configuration, make sure it will be stored in eitherFLASH memory of the module, or in external serial configuration memory device.


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CDM1540x

CHILImodule

Altera CycloneFPGA Device

FPGA_CONF_DONEFPGA_CONFIG#

FPGA_CE#

FPGA_DATA0

FPGA_DCLK

FPGA_CSO#

FPGA_ASDO

35

Altera

ByteBlaster II Connector

7

1

9

468

2

10

DGND

DGND

3.3V

FIGURE 15 CONNECTING BYTEBLASTER II DOWNLOAD CABLE

Note: For preparing your application for the external serial device or Altera ByteBlaster IIdownload cable, please consult the documentation provided by Altera Corporation.

Module InterfacesThe following pages discuss in details of the CHILImodule interface options. Note, that

0S4 0000 00100H Chili Module Datasheet

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